From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:4864:20::144; helo=mail-it1-x144.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-it1-x144.google.com (mail-it1-x144.google.com [IPv6:2607:f8b0:4864:20::144]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 412B320886F22 for ; Fri, 1 Mar 2019 02:32:40 -0800 (PST) Received: by mail-it1-x144.google.com with SMTP id z131so19384330itf.5 for ; Fri, 01 Mar 2019 02:32:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=b7JibGtxO5PZsrnnLKof5QHtpULYcjV/KId/ZDuLGK4=; b=EuHFYSMaUdfOmy7U2QrZcEd/gPWhtoNg8PMXq4ynnk7xnvUfnBtbkFl4vSqKC09Kja oMfXI2fLjom29i5nNYIVYsRFD3hG5/GG9tnzapmnxA7SsH7kpEX/Kmtjevlqwe19DGQE IoRawdUfjMP02TPBDszmNmdFvplTMkadDYHQjj6cT61lNHbbwx3GJuXZPuqpcjpoYVlN yLIO0xPKLDLC332X3+zl5DpkVuNifcksdaRYMl3wbmJnkHykJVC0GLI9HhQse0oigDpY 42d12oD7wTq/RlX+ff/HblOlwlGxZv0aGOHHWCtD68dXDqV/Q7S/zN2la+hkEx/MY4FE iTNA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=b7JibGtxO5PZsrnnLKof5QHtpULYcjV/KId/ZDuLGK4=; b=AFSo4HqwpkGeiOvz8SxjeBT8Hf1AlMo++SUfixpskg+r2GFcTC5PTcq/lyKW7fNN2/ bMH8MAeSMW00nmZOVrdnuFUcOEzOJR4bMeI39e/poV0NT024S3dL0tS9nbwoqK0ZjBqL Bx4H7aB3FsKrgycRAcjQDs3rieoPWmgX8paFr0ks7FdrLYnyYjciNep6HBIjiVpFoGHY NYVOjApxPiIgHaTMVMj7cVF+iPU+fxWfne/qMo+DJ01LKNuCVDEOr7XEM5kvZIB6vg3l P/9Xej6zTm1FvlMpoJE5VXZMbV6iP1V8RobYtCpxu+2vlccrUWDeRo3MpruvTbqearyx G/Jg== X-Gm-Message-State: APjAAAUPSZRCZQrxpAxGEZYeYtdA6Du+pT7Ad88rjJrKuZS/XoZGO46o CSo0W+4ZMvzt/RofbJe2dVvmvERy4CC/3y301WzaxQ== X-Google-Smtp-Source: APXvYqz25uXCL7qRhblSZKEEBWiTC4Ju7TPPixpEk61sJE0o+7g03VzGcEmdB9lR87ppMEOvoV1Bg9lm7nEX+WZRMtc= X-Received: by 2002:a05:6638:2a1:: with SMTP id d1mr2184094jaq.2.1551436359550; Fri, 01 Mar 2019 02:32:39 -0800 (PST) MIME-Version: 1.0 References: In-Reply-To: From: Ard Biesheuvel Date: Fri, 1 Mar 2019 11:32:27 +0100 Message-ID: To: Ashish Singhal Cc: "Cohen, Eugene" , "Wu, Hao A" , "edk2-devel@lists.01.org" Subject: Re: [PATCH] MdeModulePkg/SdMmcPciHcDxe: Fix DMA on SDHC v3 64-bit systems X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 01 Mar 2019 10:32:41 -0000 Content-Type: text/plain; charset="UTF-8" On Fri, 1 Mar 2019 at 01:19, Ashish Singhal wrote: > > Eugene, > > Small question. Did the issue appear after the V4 patch went in? Looking at the code before that patch, we were enabling 64b dma in pci based on capability register already despite of driver supporting only 32b dma. > I think this may have been an oversight on my part when I originally added the DUAL_ADDRESS_CYCLE handling. The following commit added EFI_PCI_ATTRIBUTE_DUAL_ADDRESS_CYCLE to the host bridge driver commit e58a71d9c50ba641b5ab19f5ce2cbf772187de4d Author: Ard Biesheuvel Date: Mon Sep 5 09:55:16 2016 +0100 MdeModulePkg/PciHostBridgeDxe: restrict 64-bit DMA to devices that support it Currently, the EFI_PCI_ATTRIBUTE_DUAL_ADDRESS_CYCLE attribute is completely ignored by the PCI host bridge driver, which means that, on an implementation that supports DMA above 4 GB, allocations above 4 GB may be provided to devices that have not expressed support for it. and the SDHCI driver was fixed accordingly in Author: Ard Biesheuvel Date: Mon Sep 5 09:51:48 2016 +0100 MdeModulePkg/SdMmcPciHcDxe: enable 64-bit PCI DMA PCI controller drivers must set the EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE attribute if the controller supports 64-bit DMA addressing. So before these changes, we were in the exact same situation, but since PC platforms never enable DMA above 4 GB in the first place, nobody ever noticed until we started running this code on arm64 platforms that have no 32-bit addressable DRAM to begin with. The obvious conclusion is that the driver should not set the EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE attribute if the device does not support it, or, which seems to be our case, if the driver does not implement the 64-bit DMA mode that the driver does support. However, since there are platforms for which bounce buffering is not an option (since there is no 32-bit addressable memory to bounce to), this is not just a performance optimization, and so it would be useful to fix the code so it can drive all 64-bit DMA capable hardware.