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From: Ard Biesheuvel <ard.biesheuvel@linaro.org>
To: Marcin Wojtas <mw@semihalf.com>
Cc: Leif Lindholm <leif.lindholm@linaro.org>,
	edk2-devel-01 <edk2-devel@lists.01.org>,
	 Nadav Haklai <nadavh@marvell.com>,
	Neta Zur Hershkovits <neta@marvell.com>,
	 Kostya Porotchkin <kostap@marvell.com>,
	Hua Jing <jinghua@marvell.com>,
	 semihalf-dabros-jan <jsd@semihalf.com>
Subject: Re: [platforms: PATCH 09/10] Marvell/Drivers: XenonDxe: Fix base clock frequency
Date: Thu, 26 Oct 2017 14:55:58 +0100	[thread overview]
Message-ID: <CAKv+Gu_t7LHhbRtB1XCqL1zxLGDNLmLup61V2SAy6aeQvrzeCA@mail.gmail.com> (raw)
In-Reply-To: <CAPv3WKeGhZmmucubFBptR2hyDe3tHfOtVdj3QoKi2g-qTgZxMg@mail.gmail.com>

On 26 October 2017 at 14:54, Marcin Wojtas <mw@semihalf.com> wrote:
> 2017-10-26 15:46 GMT+02:00 Leif Lindholm <leif.lindholm@linaro.org>:
>> On Thu, Oct 26, 2017 at 03:19:36AM +0200, Marcin Wojtas wrote:
>>> Incorrectly the clock divisor was calculated relatively
>>> to 255MHz instead of actual 400MHz.
>>
>> This describes the specific symptom, not the problem with the existing
>> code.
>>
>>> Fix this.
>>>
>>> Contributed-under: TianoCore Contribution Agreement 1.1
>>> Signed-off-by: Marcin Wojtas <mw@semihalf.com>
>>> ---
>>>  Platform/Marvell/Drivers/SdMmc/XenonDxe/SdMmcPciHci.c | 4 ++--
>>>  1 file changed, 2 insertions(+), 2 deletions(-)
>>>
>>> diff --git a/Platform/Marvell/Drivers/SdMmc/XenonDxe/SdMmcPciHci.c b/Platform/Marvell/Drivers/SdMmc/XenonDxe/SdMmcPciHci.c
>>> index ccbf355..0b9328b 100644
>>> --- a/Platform/Marvell/Drivers/SdMmc/XenonDxe/SdMmcPciHci.c
>>> +++ b/Platform/Marvell/Drivers/SdMmc/XenonDxe/SdMmcPciHci.c
>>> @@ -16,6 +16,7 @@
>>>  **/
>>>
>>>  #include "SdMmcPciHcDxe.h"
>>> +#include "XenonSdhci.h"
>>>
>>>  /**
>>>    Dump the content of SD/MMC host controller's Capability Register.
>>> @@ -703,9 +704,8 @@ SdMmcHcClockSupply (
>>>    //
>>>    // Calculate a divisor for SD clock frequency
>>>    //
>>> -  ASSERT (Capability.BaseClkFreq != 0);
>>>
>>> -  BaseClkFreq = Capability.BaseClkFreq;
>>
>> Why is Capability.BaseClkFreq the wrong frequency to use?
>>
>
> The Capability.BaseClkFreq is UINT8 and can hold up to 0xff -> 255MHz.
> An alternative would be change this generic type to UINT16 and update
> field properly during initialization - do you prefer that?
>

Isn't that value read from device registers?


  reply	other threads:[~2017-10-26 13:52 UTC|newest]

Thread overview: 35+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-10-26  1:19 [platforms: PATCH 00/10] Armada 7k/8k - misc improvements pt.2 Marcin Wojtas
2017-10-26  1:19 ` [platforms: PATCH 01/10] Marvell/Drivers: MvI2cDxe: Abort transaction immediately upon fail Marcin Wojtas
2017-10-26 12:51   ` Leif Lindholm
2017-10-26 13:19     ` Marcin Wojtas
2017-10-26 13:54       ` Leif Lindholm
2017-10-26 13:55         ` Marcin Wojtas
2017-10-26  1:19 ` [platforms: PATCH 02/10] Marvell/Drivers: MvI2cDxe: Fix returning status in MvI2cStartRequest Marcin Wojtas
2017-10-26 13:11   ` Leif Lindholm
2017-10-26 13:22     ` Marcin Wojtas
2017-10-26 13:55       ` Leif Lindholm
2017-10-26  1:19 ` [platforms: PATCH 03/10] Marvell/Drivers: MvI2cDxe: Reduce bus occupation time Marcin Wojtas
2017-10-26 13:13   ` Leif Lindholm
2017-10-26  1:19 ` [platforms: PATCH 04/10] Marvell/Library: MppLib: Prevent overwriting PCD values Marcin Wojtas
2017-10-26 13:15   ` Leif Lindholm
2017-10-26  1:19 ` [platforms: PATCH 05/10] Marvell/Library: MppLib: Disable the stack protector Marcin Wojtas
2017-10-26 13:26   ` Leif Lindholm
2017-10-26 13:29     ` Ard Biesheuvel
2017-10-26 13:57       ` Leif Lindholm
2017-10-26  1:19 ` [platforms: PATCH 06/10] Marvell/Library: MppLib: Take 0xFF placeholders into account Marcin Wojtas
2017-10-26 13:30   ` Leif Lindholm
2017-10-26  1:19 ` [platforms: PATCH 07/10] Marvell/Drivers: Pp2Dxe: Change settings for the always-up link Marcin Wojtas
2017-10-26 13:38   ` Leif Lindholm
2017-10-26  1:19 ` [platforms: PATCH 08/10] Marvell/Drivers: XenonDxe: Fix UHS signalling mode setting Marcin Wojtas
2017-10-26 13:41   ` Leif Lindholm
2017-10-26  1:19 ` [platforms: PATCH 09/10] Marvell/Drivers: XenonDxe: Fix base clock frequency Marcin Wojtas
2017-10-26 13:46   ` Leif Lindholm
2017-10-26 13:54     ` Marcin Wojtas
2017-10-26 13:55       ` Ard Biesheuvel [this message]
2017-10-26 13:59         ` Marcin Wojtas
2017-10-26 14:02       ` Leif Lindholm
2017-10-26 14:29         ` Marcin Wojtas
2017-10-26 14:52           ` Leif Lindholm
2017-10-26 15:07             ` Marcin Wojtas
2017-10-26  1:19 ` [platforms: PATCH 10/10] Marvell/Drivers: XenonDxe: Do not modify FIFO default values Marcin Wojtas
2017-10-26 13:47   ` Leif Lindholm

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