From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:4001:c06::243; helo=mail-io0-x243.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-io0-x243.google.com (mail-io0-x243.google.com [IPv6:2607:f8b0:4001:c06::243]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 494D820352609 for ; Thu, 26 Oct 2017 06:52:13 -0700 (PDT) Received: by mail-io0-x243.google.com with SMTP id 134so5536147ioo.0 for ; Thu, 26 Oct 2017 06:55:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc; bh=ZOGcfX73n9t8lrGNAx5Lplc5x5D0jEcQY5ypMIdXzp4=; b=PGjZ3pJawTaBOPK8dBmsWPMBZvwyfBRKt8xt5PuHAqQ+6n3DqPgAQj+CFSZz0MlYBy YFkHH3XI8NLA74lilFlyYvUVcWxlcAE5CKdHU0IZKLlLViED6M8GKE0Ypkphjw1nFADM fo3Dnbkx9PbhYf9aJQHIwALMj6E8vg7E1sNvY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=ZOGcfX73n9t8lrGNAx5Lplc5x5D0jEcQY5ypMIdXzp4=; b=n6u5Y52/Aw6pdMiuTbwzh+KkjRtxlOo/DxG8abX216lBQVe/KgCAnHCZisHFR7Ni8j d1sgDIgSRioEZyWwweKJHncCRKfHVbBIM8ohDtRDvqJVa6HqD1N9ncuFpg2PMSm8Fv/T HHToq007zRGkBFL4abMYg1Kd6WrNPxAxgH9mB5ZgwAoCnbY+n9DlhNslcyk7W/UQEzyo UZPLnNt6Liyw7tiv8R2+taEmyYU5n1X+IvqDSK5od5hzNqckGrgpSxgA/VmBw23tbu2W WgsoImXKuSbkCA2Z/Q90CXLUYCkjk12/hx2dOV0Ktnk43meoULGCeNyM/Hgk4cCUZ9a5 6FOw== X-Gm-Message-State: AMCzsaW2HF8S75ZvbkQKDRPQ7Ehw51F+UcEELG7neHVz9iN61r+4P/6S 52LcBSWSBGABJISnh5CEYXzSbIUrYw/6Rxv1+IWRbQ== X-Google-Smtp-Source: ABhQp+SKN0ZkzUo/voFeBBTu9UFNCFxmVu6Wn/0m2iE+IzpqJw3alElyKWa6J0qKvJkwEYjJ+GW5kDAw4k6kWF9/QNs= X-Received: by 10.36.210.198 with SMTP id z189mr2389961itf.65.1509026158845; Thu, 26 Oct 2017 06:55:58 -0700 (PDT) MIME-Version: 1.0 Received: by 10.107.131.167 with HTTP; Thu, 26 Oct 2017 06:55:58 -0700 (PDT) In-Reply-To: References: <1508980777-29006-1-git-send-email-mw@semihalf.com> <1508980777-29006-10-git-send-email-mw@semihalf.com> <20171026134612.nro2lhy2l3qvm7pq@bivouac.eciton.net> From: Ard Biesheuvel Date: Thu, 26 Oct 2017 14:55:58 +0100 Message-ID: To: Marcin Wojtas Cc: Leif Lindholm , edk2-devel-01 , Nadav Haklai , Neta Zur Hershkovits , Kostya Porotchkin , Hua Jing , semihalf-dabros-jan Subject: Re: [platforms: PATCH 09/10] Marvell/Drivers: XenonDxe: Fix base clock frequency X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 26 Oct 2017 13:52:13 -0000 Content-Type: text/plain; charset="UTF-8" On 26 October 2017 at 14:54, Marcin Wojtas wrote: > 2017-10-26 15:46 GMT+02:00 Leif Lindholm : >> On Thu, Oct 26, 2017 at 03:19:36AM +0200, Marcin Wojtas wrote: >>> Incorrectly the clock divisor was calculated relatively >>> to 255MHz instead of actual 400MHz. >> >> This describes the specific symptom, not the problem with the existing >> code. >> >>> Fix this. >>> >>> Contributed-under: TianoCore Contribution Agreement 1.1 >>> Signed-off-by: Marcin Wojtas >>> --- >>> Platform/Marvell/Drivers/SdMmc/XenonDxe/SdMmcPciHci.c | 4 ++-- >>> 1 file changed, 2 insertions(+), 2 deletions(-) >>> >>> diff --git a/Platform/Marvell/Drivers/SdMmc/XenonDxe/SdMmcPciHci.c b/Platform/Marvell/Drivers/SdMmc/XenonDxe/SdMmcPciHci.c >>> index ccbf355..0b9328b 100644 >>> --- a/Platform/Marvell/Drivers/SdMmc/XenonDxe/SdMmcPciHci.c >>> +++ b/Platform/Marvell/Drivers/SdMmc/XenonDxe/SdMmcPciHci.c >>> @@ -16,6 +16,7 @@ >>> **/ >>> >>> #include "SdMmcPciHcDxe.h" >>> +#include "XenonSdhci.h" >>> >>> /** >>> Dump the content of SD/MMC host controller's Capability Register. >>> @@ -703,9 +704,8 @@ SdMmcHcClockSupply ( >>> // >>> // Calculate a divisor for SD clock frequency >>> // >>> - ASSERT (Capability.BaseClkFreq != 0); >>> >>> - BaseClkFreq = Capability.BaseClkFreq; >> >> Why is Capability.BaseClkFreq the wrong frequency to use? >> > > The Capability.BaseClkFreq is UINT8 and can hold up to 0xff -> 255MHz. > An alternative would be change this generic type to UINT16 and update > field properly during initialization - do you prefer that? > Isn't that value read from device registers?