From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:4001:c0b::243; helo=mail-it0-x243.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-it0-x243.google.com (mail-it0-x243.google.com [IPv6:2607:f8b0:4001:c0b::243]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id E7192220EE133 for ; Tue, 12 Dec 2017 09:46:40 -0800 (PST) Received: by mail-it0-x243.google.com with SMTP id 68so288940ite.4 for ; Tue, 12 Dec 2017 09:51:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc; bh=zlARWfCP/HxaOpcesWzROZY+jMGugLqA6HnBSi3wtz4=; b=VqRs34JiWCSohGIRngOmfeC+zFNKuqRGT5f8glGZWDGA26UpD53P2Wpx3nfLwiHu1F L5d7+Z7KVv/MBcgU19yucqvGiBfywVA8QHFta2BkcXO8hFNGlY0hmZlAAoCxdJjhIDFP uYOJfsOWXabho77RjXcqtYPKkYTMLZPEyfp10= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=zlARWfCP/HxaOpcesWzROZY+jMGugLqA6HnBSi3wtz4=; b=bftycPsvz8rkYSN8wHSoaEhrXqoZMKxHmNE/sZqo9e45OJell7nbW2dyCtQhxuKKV/ jEcO5IX7o8kpIZyOCD2gLkrU4wvstO8T6KQCK4Z3LzmY5JXXkZjoDRaxXppAfO49vyIC 3sZQ7zyXMssifgxiX2fLNdjMsa27WRT8wj977tSL2TxTrU3XyzG3IAVaMVrOyDlH5K6a j+7kxr7edIrnulk+4EcZsXbOvhunmSwt08KjfRA6JzOwIFjUXZnTSyljRGuAUU25PRgh 0/1LVtOlL7ASi123MDVEl/HSRROdlCaiScMZOoOPnQ3BaA4e/USCdmJodZryNnNpwS4w /X5g== X-Gm-Message-State: AKGB3mJDXth22x1copv2p6D+qxeF5lWE/yR8/ezPb+mQNPerGzxpYYzk yNhjUVAt3rg7pKwIC1vojvXtq2jt5PwpxucdCOXAwg== X-Google-Smtp-Source: ACJfBosXRDEKh409qu3d7bmgwvOpSeTjZygBh3SBqaR4lMWlfHc7Su6lEfcH9E9LpsFyG6B4cWyRcp6ICqbwwSpx6Xg= X-Received: by 10.36.219.214 with SMTP id c205mr489217itg.65.1513101079224; Tue, 12 Dec 2017 09:51:19 -0800 (PST) MIME-Version: 1.0 Received: by 10.107.104.16 with HTTP; Tue, 12 Dec 2017 09:51:18 -0800 (PST) In-Reply-To: <20171212174718.mbbrhh7opjbqmxs6@bivouac.eciton.net> References: <20171212103807.18836-1-ard.biesheuvel@linaro.org> <20171212103807.18836-9-ard.biesheuvel@linaro.org> <20171212174718.mbbrhh7opjbqmxs6@bivouac.eciton.net> From: Ard Biesheuvel Date: Tue, 12 Dec 2017 17:51:18 +0000 Message-ID: To: Leif Lindholm Cc: "edk2-devel@lists.01.org" , Daniel Thompson , Masami Hiramatsu Subject: Re: [PATCH edk2-platforms 8/8] Silicon/SynQuacer/PlatformDxe: retrain PCIe switch links to Gen2 speed X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 12 Dec 2017 17:46:41 -0000 Content-Type: text/plain; charset="UTF-8" On 12 December 2017 at 17:47, Leif Lindholm wrote: > On Tue, Dec 12, 2017 at 10:38:07AM +0000, Ard Biesheuvel wrote: >> For some reason, the Asmedia 118x PCIe switch needs a little help to >> make sure that the downstream links train at Gen2 speed. So add a >> PCI I/O protocol notifier that implements this for each PCIe downstream >> port that is present on the system. >> >> Contributed-under: TianoCore Contribution Agreement 1.1 >> Signed-off-by: Ard Biesheuvel >> --- >> Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/Pcie.c | 140 ++++++++++++++++++++ >> Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.c | 13 +- >> Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.h | 37 ++++++ >> Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.inf | 3 + >> 4 files changed, 184 insertions(+), 9 deletions(-) >> >> diff --git a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/Pcie.c b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/Pcie.c >> new file mode 100644 >> index 000000000000..b069b42d0a42 >> --- /dev/null >> +++ b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/Pcie.c > > Bikeshedding time: > This driver would likely be needed for any other platform including > this switch as well, right? > > While it may be premature to create a standalone driver under > Silicon/Asmedia ... how about calling this file something to make it > clear that it is specifically intended to handle Asmedia 118x devices, > to make it easier* to do so in the future? I.e. Asmedia118x.c? > > * by avoiding accruing other random bits of platform-specific PCI > hackery in the same file. > To be honest, I am not entirely sure. I need this hack for the standalone card as well as the onboard switch, so it is not related to a board level defect on developerbox. However, it could be related to how the Synopsys IP manages the reset and training etc. But I agree, let's move this to Asmedia118x.c and not create a generic looking file that invites more PCI quirks to be parked there