From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:4864:20::143; helo=mail-it1-x143.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-it1-x143.google.com (mail-it1-x143.google.com [IPv6:2607:f8b0:4864:20::143]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id CCF442116DA13 for ; Fri, 12 Oct 2018 08:36:50 -0700 (PDT) Received: by mail-it1-x143.google.com with SMTP id i76-v6so18773539ita.3 for ; Fri, 12 Oct 2018 08:36:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc; bh=dqFa8AvVoKee6FG0iN8lkqj4mv18pqvfh9YWY8dBh70=; b=PTbs9C4uyqcJRwar/z4N33qOm+NMKP6zH38siVZdtYRuc9XCFTlVjjeLTCS9U7ixo3 Txml4AnlnXCq+yP1AEl2o3sjcAgj3GuFDVvVovcjml5ptdzHcV6wRyBzOFOvth8gfg7i Kn3unIgsf2VieFaLjF3mWLWN+9sgjdJ+odE8A= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=dqFa8AvVoKee6FG0iN8lkqj4mv18pqvfh9YWY8dBh70=; b=R7BqEXx8wosMFZZxomg9CcGmjz9piqA6gKVAka5NelvcoEdynIT+OA2EbzTg4lAANd /w2ZTriZKqcaOTApKPygsDJj7UieLKDb2P0ijrpqynnk30FxXxR/P/a7764erQPSpXU3 pq9ztlEpYJyekgt+0IX5mF3+HvzERV2jeUmk4jlvz9I+Y/tf0yipyGaT/gPUpBkTxDYH yqNxP7Zo8jN8QU0jSNw5X62AgjyAP13TvkfmBwb3nVbvJ2TZ0VcT1QC1Vnuf3x+gZWJs usGpG5luq1eM7sI8wQy2bBhvnCyTE5wA8ieXi2kG1EibziLeEjEiWfRKkzr8s/GNTzLK KwAg== X-Gm-Message-State: ABuFfogJwi0RCkjM+F/cgRxOpHzG0i4tXcgMPAvE8TFg55QbPV17evya haehNImSxphGZsKNFxrPpAHiKq9oXGJ5gCO/bz+4SYXwHvs= X-Google-Smtp-Source: ACcGV62dI8fEeCuARTxB0QjxkAAVy+0xa3g6luU8BwCrLxszSgOs+BBVpCIU4uPP9dgbQRLq9DRycCkbRrVDOa7Cr6g= X-Received: by 2002:a05:660c:383:: with SMTP id x3mr4597258itj.121.1539358609844; Fri, 12 Oct 2018 08:36:49 -0700 (PDT) MIME-Version: 1.0 Received: by 2002:a6b:5910:0:0:0:0:0 with HTTP; Fri, 12 Oct 2018 08:36:49 -0700 (PDT) In-Reply-To: <1539333136-28509-1-git-send-email-mw@semihalf.com> References: <1539333136-28509-1-git-send-email-mw@semihalf.com> From: Ard Biesheuvel Date: Fri, 12 Oct 2018 17:36:49 +0200 Message-ID: To: Marcin Wojtas Cc: "edk2-devel@lists.01.org" , Leif Lindholm , Steve Capper , Nadav Haklai , =?UTF-8?B?SmFuIETEhWJyb8Wb?= , Grzegorz Jaszczyk Subject: Re: [platforms: PATCH 1/1] Marvell/Armada7k8k: DeviceTree: Use fixed clocks X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 12 Oct 2018 15:36:51 -0000 Content-Type: text/plain; charset="UTF-8" On 12 October 2018 at 10:32, Marcin Wojtas wrote: > This patch enables relying on clocks configured by firmware. > Configure the device tree in a way, that all consumers use > a fixed-clock tree instead of the real cp110-system-controller > driver. > > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Marcin Wojtas Reviewed-by: Ard Biesheuvel Pushed as a82113852ae1..124073e4d440 > --- > Silicon/Marvell/Armada7k8k/DeviceTree/armada-cp110.dtsi | 142 ++++++++++++++------ > 1 file changed, 99 insertions(+), 43 deletions(-) > > diff --git a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-cp110.dtsi b/Silicon/Marvell/Armada7k8k/DeviceTree/armada-cp110.dtsi > index 3337034..5e8e524 100644 > --- a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-cp110.dtsi > +++ b/Silicon/Marvell/Armada7k8k/DeviceTree/armada-cp110.dtsi > @@ -40,9 +40,9 @@ > CP110_LABEL(ethernet): ethernet@0 { > compatible = "marvell,armada-7k-pp22"; > reg = <0x0 0x100000>, <0x129000 0xb000>; > - clocks = <&CP110_LABEL(clk) 1 3>, <&CP110_LABEL(clk) 1 9>, > - <&CP110_LABEL(clk) 1 5>, <&CP110_LABEL(clk) 1 6>, > - <&CP110_LABEL(clk) 1 18>; > + clocks = <&CP110_LABEL(ppv2_clk)>, <&CP110_LABEL(ppv2_clk)>, > + <&CP110_LABEL(ppv2_clk)>, <&CP110_LABEL(core_clk)>, > + <&CP110_LABEL(core_clk)>; > clock-names = "pp_clk", "gop_clk", > "mg_clk", "mg_core_clk", "axi_clk"; > marvell,system-controller = <&CP110_LABEL(syscon0)>; > @@ -135,8 +135,8 @@ > #size-cells = <0>; > compatible = "marvell,orion-mdio"; > reg = <0x12a200 0x10>; > - clocks = <&CP110_LABEL(clk) 1 9>, <&CP110_LABEL(clk) 1 5>, > - <&CP110_LABEL(clk) 1 6>, <&CP110_LABEL(clk) 1 18>; > + clocks = <&CP110_LABEL(ppv2_clk)>, <&CP110_LABEL(ppv2_clk)>, > + <&CP110_LABEL(core_clk)>, <&CP110_LABEL(core_clk)>; > status = "disabled"; > }; > > @@ -145,8 +145,8 @@ > #size-cells = <0>; > compatible = "marvell,xmdio"; > reg = <0x12a600 0x10>; > - clocks = <&CP110_LABEL(clk) 1 5>, > - <&CP110_LABEL(clk) 1 6>, <&CP110_LABEL(clk) 1 18>; > + clocks = <&CP110_LABEL(ppv2_clk)>, <&CP110_LABEL(ppv2_clk)>, > + <&CP110_LABEL(core_clk)>; > status = "disabled"; > }; > > @@ -178,6 +178,7 @@ > > CP110_LABEL(clk): clock { > compatible = "marvell,cp110-clock"; > + status = "disabled"; > #clock-cells = <2>; > }; > > @@ -219,8 +220,8 @@ > dma-coherent; > interrupts = ; > clock-names = "core", "reg"; > - clocks = <&CP110_LABEL(clk) 1 22>, > - <&CP110_LABEL(clk) 1 16>; > + clocks = <&CP110_LABEL(core_clk)>, > + <&CP110_LABEL(core_clk)>; > status = "disabled"; > }; > > @@ -231,8 +232,8 @@ > dma-coherent; > interrupts = ; > clock-names = "core", "reg"; > - clocks = <&CP110_LABEL(clk) 1 23>, > - <&CP110_LABEL(clk) 1 16>; > + clocks = <&CP110_LABEL(core_clk)>, > + <&CP110_LABEL(core_clk)>; > status = "disabled"; > }; > > @@ -242,8 +243,8 @@ > reg = <0x540000 0x30000>; > dma-coherent; > interrupts = ; > - clocks = <&CP110_LABEL(clk) 1 15>, > - <&CP110_LABEL(clk) 1 16>; > + clocks = <&CP110_LABEL(core_clk)>, > + <&CP110_LABEL(core_clk)>; > status = "disabled"; > }; > > @@ -253,8 +254,8 @@ > dma-coherent; > msi-parent = <&gic_v2m0>; > clock-names = "core", "reg"; > - clocks = <&CP110_LABEL(clk) 1 8>, > - <&CP110_LABEL(clk) 1 14>; > + clocks = <&CP110_LABEL(core_clk)>, > + <&CP110_LABEL(x2core_clk)>; > }; > > CP110_LABEL(xor1): xor@6c0000 { > @@ -263,8 +264,8 @@ > dma-coherent; > msi-parent = <&gic_v2m0>; > clock-names = "core", "reg"; > - clocks = <&CP110_LABEL(clk) 1 7>, > - <&CP110_LABEL(clk) 1 14>; > + clocks = <&CP110_LABEL(core_clk)>, > + <&CP110_LABEL(x2core_clk)>; > }; > > CP110_LABEL(spi0): spi@700600 { > @@ -273,8 +274,8 @@ > #address-cells = <0x1>; > #size-cells = <0x0>; > clock-names = "core", "axi"; > - clocks = <&CP110_LABEL(clk) 1 21>, > - <&CP110_LABEL(clk) 1 17>; > + clocks = <&CP110_LABEL(slow_io_clk)>, > + <&CP110_LABEL(x2core_clk)>; > status = "disabled"; > }; > > @@ -284,8 +285,8 @@ > #address-cells = <1>; > #size-cells = <0>; > clock-names = "core", "axi"; > - clocks = <&CP110_LABEL(clk) 1 21>, > - <&CP110_LABEL(clk) 1 17>; > + clocks = <&CP110_LABEL(slow_io_clk)>, > + <&CP110_LABEL(x2core_clk)>; > status = "disabled"; > }; > > @@ -296,8 +297,8 @@ > #size-cells = <0>; > interrupts = ; > clock-names = "core", "reg"; > - clocks = <&CP110_LABEL(clk) 1 21>, > - <&CP110_LABEL(clk) 1 17>; > + clocks = <&CP110_LABEL(slow_io_clk)>, > + <&CP110_LABEL(x2core_clk)>; > status = "disabled"; > }; > > @@ -308,8 +309,8 @@ > #size-cells = <0>; > interrupts = ; > clock-names = "core", "reg"; > - clocks = <&CP110_LABEL(clk) 1 21>, > - <&CP110_LABEL(clk) 1 17>; > + clocks = <&CP110_LABEL(slow_io_clk)>, > + <&CP110_LABEL(x2core_clk)>; > status = "disabled"; > }; > > @@ -320,8 +321,8 @@ > interrupts = ; > reg-io-width = <1>; > clock-names = "baudclk", "apb_pclk"; > - clocks = <&CP110_LABEL(clk) 1 21>, > - <&CP110_LABEL(clk) 1 17>; > + clocks = <&CP110_LABEL(slow_io_clk)>, > + <&CP110_LABEL(x2core_clk)>; > status = "disabled"; > }; > > @@ -332,8 +333,8 @@ > interrupts = ; > reg-io-width = <1>; > clock-names = "baudclk", "apb_pclk"; > - clocks = <&CP110_LABEL(clk) 1 21>, > - <&CP110_LABEL(clk) 1 17>; > + clocks = <&CP110_LABEL(slow_io_clk)>, > + <&CP110_LABEL(x2core_clk)>; > status = "disabled"; > }; > > @@ -344,8 +345,8 @@ > interrupts = ; > reg-io-width = <1>; > clock-names = "baudclk", "apb_pclk"; > - clocks = <&CP110_LABEL(clk) 1 21>, > - <&CP110_LABEL(clk) 1 17>; > + clocks = <&CP110_LABEL(slow_io_clk)>, > + <&CP110_LABEL(x2core_clk)>; > status = "disabled"; > }; > > @@ -356,8 +357,8 @@ > interrupts = ; > reg-io-width = <1>; > clock-names = "baudclk", "apb_pclk"; > - clocks = <&CP110_LABEL(clk) 1 21>, > - <&CP110_LABEL(clk) 1 17>; > + clocks = <&CP110_LABEL(slow_io_clk)>, > + <&CP110_LABEL(x2core_clk)>; > status = "disabled"; > }; > > @@ -374,8 +375,8 @@ > #size-cells = <0>; > interrupts = ; > clock-names = "core", "reg"; > - clocks = <&CP110_LABEL(clk) 1 2>, > - <&CP110_LABEL(clk) 1 17>; > + clocks = <&CP110_LABEL(nand_clk)>, > + <&CP110_LABEL(x2core_clk)>; > marvell,system-controller = <&CP110_LABEL(syscon0)>; > status = "disabled"; > }; > @@ -386,8 +387,8 @@ > reg = <0x760000 0x7d>; > interrupts = ; > clock-names = "core", "reg"; > - clocks = <&CP110_LABEL(clk) 1 25>, > - <&CP110_LABEL(clk) 1 17>; > + clocks = <&CP110_LABEL(x2core_clk)>, > + <&CP110_LABEL(x2core_clk)>; > status = "okay"; > }; > > @@ -396,7 +397,7 @@ > reg = <0x780000 0x300>; > interrupts = ; > clock-names = "core", "axi"; > - clocks = <&CP110_LABEL(clk) 1 4>, <&CP110_LABEL(clk) 1 18>; > + clocks = <&CP110_LABEL(sdio_clk)>, <&CP110_LABEL(core_clk)>; > dma-coherent; > status = "disabled"; > }; > @@ -413,8 +414,8 @@ > interrupt-names = "mem", "ring0", "ring1", > "ring2", "ring3", "eip"; > clock-names = "core", "reg"; > - clocks = <&CP110_LABEL(clk) 1 26>, > - <&CP110_LABEL(clk) 1 17>; > + clocks = <&CP110_LABEL(x2core_clk)>, > + <&CP110_LABEL(x2core_clk)>; > dma-coherent; > }; > }; > @@ -442,7 +443,7 @@ > interrupts = ; > num-lanes = <1>; > clock-names = "core", "reg"; > - clocks = <&CP110_LABEL(clk) 1 13>, <&CP110_LABEL(clk) 1 14>; > + clocks = <&CP110_LABEL(core_clk)>, <&CP110_LABEL(x2core_clk)>; > status = "disabled"; > }; > > @@ -470,7 +471,7 @@ > > num-lanes = <1>; > clock-names = "core", "reg"; > - clocks = <&CP110_LABEL(clk) 1 11>, <&CP110_LABEL(clk) 1 14>; > + clocks = <&CP110_LABEL(core_clk)>, <&CP110_LABEL(x2core_clk)>; > status = "disabled"; > }; > > @@ -498,7 +499,62 @@ > > num-lanes = <1>; > clock-names = "core", "reg"; > - clocks = <&CP110_LABEL(clk) 1 12>, <&CP110_LABEL(clk) 1 14>; > + clocks = <&CP110_LABEL(core_clk)>, <&CP110_LABEL(x2core_clk)>; > status = "disabled"; > }; > + > + /* 1 GHz fixed main PLL */ > + CP110_LABEL(mainpll): CP110_LABEL(mainpll) { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-frequency = <1000000000>; > + }; > + > + CP110_LABEL(x2core_clk): CP110_LABEL(x2core_clk) { > + compatible = "fixed-factor-clock"; > + clocks = <&CP110_LABEL(mainpll)>; > + #clock-cells = <0>; > + clock-mult = <1>; > + clock-div = <2>; > + }; > + > + CP110_LABEL(core_clk): CP110_LABEL(core_clk) { > + compatible = "fixed-factor-clock"; > + clocks = <&CP110_LABEL(mainpll)>; > + #clock-cells = <0>; > + clock-mult = <1>; > + clock-div = <2>; > + }; > + > + CP110_LABEL(sdio_clk): CP110_LABEL(sdio_clk) { > + compatible = "fixed-factor-clock"; > + clocks = <&CP110_LABEL(mainpll)>; > + #clock-cells = <0>; > + clock-mult = <2>; > + clock-div = <5>; > + }; > + > + CP110_LABEL(nand_clk): CP110_LABEL(nand_clk) { > + compatible = "fixed-factor-clock"; > + clocks = <&CP110_LABEL(mainpll)>; > + #clock-cells = <0>; > + clock-mult = <2>; > + clock-div = <5>; > + }; > + > + CP110_LABEL(ppv2_clk): CP110_LABEL(ppv2_clk) { > + compatible = "fixed-factor-clock"; > + clocks = <&CP110_LABEL(mainpll)>; > + #clock-cells = <0>; > + clock-mult = <1>; > + clock-div = <3>; > + }; > + > + CP110_LABEL(slow_io_clk): CP110_LABEL(slow_io_clk) { > + compatible = "fixed-factor-clock"; > + clocks = <&CP110_LABEL(mainpll)>; > + #clock-cells = <0>; > + clock-mult = <1>; > + clock-div = <4>; > + }; > }; > -- > 2.7.4 >