From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-it0-x231.google.com (mail-it0-x231.google.com [IPv6:2607:f8b0:4001:c0b::231]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id C604281E9D for ; Fri, 20 Jan 2017 09:52:41 -0800 (PST) Received: by mail-it0-x231.google.com with SMTP id c7so25067263itd.1 for ; Fri, 20 Jan 2017 09:52:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc; bh=fiSLbXWpSarmKeMGFS0S06Qyh4eVKQotNJnj8Z1eJ2k=; b=I+9gVzQ1mS1YZRgUTDr3su5eZ/FDGArWu94hJEbINAdOmpMNP07FaqbGDeD76yFaLx HOfnTyF7a11OAC8/DWuT/RLvruD7A96McTxLcQ27UGqY1wqHRfsmjjvhicADawcZ4NZE ka06TNOsFtcGeXXoGoAQWU/J90MmO/kxf6zyQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=fiSLbXWpSarmKeMGFS0S06Qyh4eVKQotNJnj8Z1eJ2k=; b=nhDBzVckxeCt2GGA77KYcFulTudC4rcJ+vqGjLG2HhOerM/rQmUgDZlGoI0pl8GDO8 e5YkCheUCrgFaDmy2PiODGCAjvGtJUWVbzQuipFChyzObdZExho7PRbZl5a2O6aj31kM 3fgIeaC5h/POQ05IoVvdnwTifp9rf8ZOK1+TC3KrmTLTQFNff7sp1MbWopYloZ/fVa5c VdCs6Bg7cds+pTEExVawTIoWSSyFEFw4RfulPRxACmGUsUrg/y5ZoW6sHPe/if7Nc+Cm Syhvpuf6VL0owTEs2VpNS2LC3nlaIBFb+0Qel3DjlOl5VFxICUtoaLcoCNLyrXUzBcgR i7PQ== X-Gm-Message-State: AIkVDXJ2gBCF1XY4Bf8yC+z1XngBbVADKHysp405pcbP/uKi+BIPVtCZsFsUCsfK3U/fGTfNCpK7DOwYvfJUHLRk X-Received: by 10.36.133.133 with SMTP id r127mr4463413itd.37.1484934761106; Fri, 20 Jan 2017 09:52:41 -0800 (PST) MIME-Version: 1.0 Received: by 10.107.144.135 with HTTP; Fri, 20 Jan 2017 09:52:40 -0800 (PST) In-Reply-To: <20170120174949.GH25883@bivouac.eciton.net> References: <1484931946-11648-1-git-send-email-ard.biesheuvel@linaro.org> <20170120174949.GH25883@bivouac.eciton.net> From: Ard Biesheuvel Date: Fri, 20 Jan 2017 17:52:40 +0000 Message-ID: To: Leif Lindholm Cc: "edk2-devel@lists.01.org" , Laszlo Ersek , Heyi Guo , Andrey Shedel Subject: Re: [PATCH] ArmPkg/ArmMmuLib: Revert "use a pool allocation for the root table" X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 20 Jan 2017 17:52:42 -0000 Content-Type: text/plain; charset=UTF-8 On 20 January 2017 at 17:49, Leif Lindholm wrote: > On Fri, Jan 20, 2017 at 05:05:46PM +0000, Ard Biesheuvel wrote: >> This reverts commit d32702d2c2aa23e828363a7f88829b78ce36c3af. >> >> Using a pool allocation for the root translation table seemed like >> a good idea at the time, but as it turns out, such allocations are >> handled in a way that makes them unsuitable for this purpose: they >> are backed by HOBs that don't remain in the same place during the >> various PI phase changes, which means the address programmed into >> the TTBR register is no longer valid, and may refer to memory that >> is reported as available to the OS. >> >> So switch back to using a page based allocation. >> >> Contributed-under: TianoCore Contribution Agreement 1.0 >> Signed-off-by: Ard Biesheuvel > > Given the discussion on the other thread: > Reviewed-by: Leif Lindholm > Pushed, thanks. >> --- >> ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c | 29 ++++---------------- >> 1 file changed, 6 insertions(+), 23 deletions(-) >> >> diff --git a/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c b/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c >> index c78297084207..540069a59b2e 100644 >> --- a/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c >> +++ b/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c >> @@ -553,12 +553,10 @@ ArmConfigureMmu ( >> ) >> { >> VOID* TranslationTable; >> - VOID* TranslationTableBuffer; >> UINT32 TranslationTableAttribute; >> UINT64 MaxAddress; >> UINTN T0SZ; >> UINTN RootTableEntryCount; >> - UINTN RootTableEntrySize; >> UINT64 TCR; >> RETURN_STATUS Status; >> >> @@ -643,19 +641,8 @@ ArmConfigureMmu ( >> // Set TCR >> ArmSetTCR (TCR); >> >> - // Allocate pages for translation table. Pool allocations are 8 byte aligned, >> - // but we may require a higher alignment based on the size of the root table. >> - RootTableEntrySize = RootTableEntryCount * sizeof(UINT64); >> - if (RootTableEntrySize < EFI_PAGE_SIZE / 2) { >> - TranslationTableBuffer = AllocatePool (2 * RootTableEntrySize - 8); >> - // >> - // Naturally align the root table. Preserves possible NULL value >> - // >> - TranslationTable = (VOID *)((UINTN)(TranslationTableBuffer - 1) | (RootTableEntrySize - 1)) + 1; >> - } else { >> - TranslationTable = AllocatePages (1); >> - TranslationTableBuffer = NULL; >> - } >> + // Allocate pages for translation table >> + TranslationTable = AllocatePages (1); >> if (TranslationTable == NULL) { >> return RETURN_OUT_OF_RESOURCES; >> } >> @@ -669,10 +656,10 @@ ArmConfigureMmu ( >> } >> >> if (TranslationTableSize != NULL) { >> - *TranslationTableSize = RootTableEntrySize; >> + *TranslationTableSize = RootTableEntryCount * sizeof(UINT64); >> } >> >> - ZeroMem (TranslationTable, RootTableEntrySize); >> + ZeroMem (TranslationTable, RootTableEntryCount * sizeof(UINT64)); >> >> // Disable MMU and caches. ArmDisableMmu() also invalidates the TLBs >> ArmDisableMmu (); >> @@ -689,7 +676,7 @@ ArmConfigureMmu ( >> DEBUG_CODE_BEGIN (); >> // Find the memory attribute for the Translation Table >> if ((UINTN)TranslationTable >= MemoryTable->PhysicalBase && >> - (UINTN)TranslationTable + RootTableEntrySize <= MemoryTable->PhysicalBase + >> + (UINTN)TranslationTable + EFI_PAGE_SIZE <= MemoryTable->PhysicalBase + >> MemoryTable->Length) { >> TranslationTableAttribute = MemoryTable->Attributes; >> } >> @@ -718,11 +705,7 @@ ArmConfigureMmu ( >> return RETURN_SUCCESS; >> >> FREE_TRANSLATION_TABLE: >> - if (TranslationTableBuffer != NULL) { >> - FreePool (TranslationTableBuffer); >> - } else { >> - FreePages (TranslationTable, 1); >> - } >> + FreePages (TranslationTable, 1); >> return Status; >> } >> >> -- >> 2.7.4 >>