From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: mx.groups.io; dkim=pass header.i=@linaro.org header.s=google header.b=ZfuHqfwj; spf=pass (domain: linaro.org, ip: 209.85.166.66, mailfrom: ard.biesheuvel@linaro.org) Received: from mail-io1-f66.google.com (mail-io1-f66.google.com [209.85.166.66]) by groups.io with SMTP; Thu, 16 May 2019 01:05:37 -0700 Received: by mail-io1-f66.google.com with SMTP id p2so1880912iol.2 for ; Thu, 16 May 2019 01:05:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=5A5wdw7zznZNXAyOXYCHGXq4ErGV+B7c3ee6HyajQI0=; b=ZfuHqfwjA1Q9AMR497q+RcKo4H5KRO2tsB453XDBoqkIxom2JvSwx31K+MN9AEDjmw ug9qLy+rXGERdIL1nu6FwUJVqgj6Ao7aAJQtl6QGUBwn8a5Se7FJgxLHrxuiwh54oQAa 3PKCFdsbuYC1G9sVnfMUmsASKvzssGAUqNZ97py/Xm+Harl+29jT1GXzMMDgPg4nsiUN iQKtI+pyVqG+XjiyBAu4g4sLkoEL/YutkJzbLNA9gnOJB2rcaszvqXy9dh4cyKx8M/Rc ETsrppT4hLMEedydKMW9ruRfgo5hCDmXYq2bKH3bvHKdVzqiS88Mc0h+23hM+BHuR2Gn i6TA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=5A5wdw7zznZNXAyOXYCHGXq4ErGV+B7c3ee6HyajQI0=; b=bUMFGUd+h/+E6fpSIV5D+nyQE5Pk5LNhC6oXmX/aVXInjMsOlS/K3rbBUS2Zg9+TKd LXrSFjKSQHx5Nb4Yep272lAieLMf21KZvZgC932K47qSQGwW0uyj2K7YL/RD1kSQ4Cv9 PAuXGOW/FrY8T7EZ6Sxm4A37VQhxeUY/pQNLn9uybBR9CDEfJBKixiAYmaAQtr0asEgj U0rfInEGcYQd9RXGYZHctFBfKManaOTXUW1QM0jRwyf57+QREKSIlRuqX7Wcwa/91czD 8HJGHNkkkDZGnHTf2HrXXQQX3ze3y2CaKoxWbTzegkt1VJ7a4Ug0hDERQEUzxFivBZ1T n86A== X-Gm-Message-State: APjAAAVe+zkupBRJ6BZw3/+vX7wn+TrfGXnv/PmcXaE7kAYe45UiKhFl 0d90i6E3SZRdBayX83lZ//bf7JfAb/xBY3pM+hAbGA== X-Google-Smtp-Source: APXvYqzahkFRK9//PE+vQ2z9lJiabQdbEGlDZgKpusIWWgeJrrU3smtSTakPKfozXbs4d/MrlXpHkye173CIYJwW3sc= X-Received: by 2002:a5d:93da:: with SMTP id j26mr26515454ioo.170.1557993936851; Thu, 16 May 2019 01:05:36 -0700 (PDT) MIME-Version: 1.0 References: <20190504000716.7525-1-lersek@redhat.com> <20190504000716.7525-5-lersek@redhat.com> In-Reply-To: <20190504000716.7525-5-lersek@redhat.com> From: "Ard Biesheuvel" Date: Thu, 16 May 2019 10:05:24 +0200 Message-ID: Subject: Re: [PATCH 4/4] OvmfPkg/PlatformPei: fix MTRR for low-RAM sizes that have many bits clear To: Laszlo Ersek Cc: edk2-devel-groups-io , Gerd Hoffmann , Jordan Justen Content-Type: text/plain; charset="UTF-8" On Sat, 4 May 2019 at 02:07, Laszlo Ersek wrote: > > Assume that we boot OVMF in a QEMU guest with 1025 MB of RAM. The > following assertion will fire: > > > ASSERT_EFI_ERROR (Status = Out of Resources) > > ASSERT OvmfPkg/PlatformPei/MemDetect.c(696): !EFI_ERROR (Status) > > That's because the range [1025 MB, 4 GB) that we try to mark as > uncacheable with MTRRs has size 3071 MB: > > 0x1_0000_0000 > -0x0_4010_0000 > -------------- > 0x0_BFF0_0000 > > The integer that stands for the uncacheable area size has 11 (eleven) bits > set to 1. As a result, covering this size requires 11 variable MTRRs (each > MTRR must cover a naturally aligned, power-of-two sized area). But, if we > need more variable MTRRs than the CPU can muster (such as 8), then > MtrrSetMemoryAttribute() fails, and we refuse to continue booting (which > is justified, in itself). > > Unfortunately, this is not difficult to trigger, and the error message is > well-hidden from end-users, in the OVMF debug log. The following > mitigation is inspired by SeaBIOS: > > Truncate the uncacheable area size to a power-of-two, while keeping the > end fixed at 4 GB. Such an interval can be covered by just one variable > MTRR. > > This may leave such an MMIO gap, between the end of low-RAM and the start > of the uncacheable area, that is marked as WB (through the MTRR default). > Raise the base of the 32-bit PCI MMIO aperture accordingly -- the gap will > not be used for anything. > > On Q35, the minimal 32-bit PCI MMIO aperture (triggered by RAM size 2815 > MB) shrinks from > > 0xE000_0000 - 0xAFF0_0000 = 769 MB > > to > > 0xE000_0000 - 0xC000_0000 = 512 MB > > On i440fx, the minimal 32-bit PCI MMIO aperture (triggered by RAM size > 3583 MB) shrinks from > > 0xFC00_0000 - 0xDFF0_0000 = 449 MB > > to > > 0xFC00_0000 - 0xE000_0000 = 448 MB > > Cc: Ard Biesheuvel > Cc: Gerd Hoffmann > Cc: Jordan Justen > Ref: https://bugzilla.redhat.com/show_bug.cgi?id=1666941 > Ref: https://bugzilla.redhat.com/show_bug.cgi?id=1701710 > Signed-off-by: Laszlo Ersek Reviewed-by: Ard Biesheuvel > --- > OvmfPkg/PlatformPei/Platform.h | 2 ++ > OvmfPkg/PlatformPei/MemDetect.c | 23 +++++++++++++++++--- > OvmfPkg/PlatformPei/Platform.c | 4 +--- > 3 files changed, 23 insertions(+), 6 deletions(-) > > diff --git a/OvmfPkg/PlatformPei/Platform.h b/OvmfPkg/PlatformPei/Platform.h > index 81af8b71480f..4476ddd871cd 100644 > --- a/OvmfPkg/PlatformPei/Platform.h > +++ b/OvmfPkg/PlatformPei/Platform.h > @@ -114,4 +114,6 @@ extern UINT32 mMaxCpuCount; > > extern UINT16 mHostBridgeDevId; > > +extern UINT32 mQemuUc32Base; > + > #endif // _PLATFORM_PEI_H_INCLUDED_ > diff --git a/OvmfPkg/PlatformPei/MemDetect.c b/OvmfPkg/PlatformPei/MemDetect.c > index e890e36408a6..ae73c63d27d5 100644 > --- a/OvmfPkg/PlatformPei/MemDetect.c > +++ b/OvmfPkg/PlatformPei/MemDetect.c > @@ -42,6 +42,8 @@ STATIC UINT32 mS3AcpiReservedMemorySize; > > STATIC UINT16 mQ35TsegMbytes; > > +UINT32 mQemuUc32Base; > + > VOID > Q35TsegMbytesInitialization ( > VOID > @@ -663,6 +665,8 @@ QemuInitializeRam ( > // cover it exactly. > // > if (IsMtrrSupported ()) { > + UINT32 Uc32Size; > + > MtrrGetAllMtrrs (&MtrrSettings); > > // > @@ -689,11 +693,24 @@ QemuInitializeRam ( > > // > // Set memory range from the "top of lower RAM" (RAM below 4GB) to 4GB as > - // uncacheable > + // uncacheable. Make sure one variable MTRR suffices by truncating the size > + // to a whole power of two. This will round the base *up*, and a gap (not > + // used for either RAM or MMIO) may stay in the middle, marked as > + // cacheable-by-default. > // > - Status = MtrrSetMemoryAttribute (LowerMemorySize, > - SIZE_4GB - LowerMemorySize, CacheUncacheable); > + Uc32Size = GetPowerOfTwo32 ((UINT32)(SIZE_4GB - LowerMemorySize)); > + mQemuUc32Base = (UINT32)(SIZE_4GB - Uc32Size); > + if (mQemuUc32Base != LowerMemorySize) { > + DEBUG ((DEBUG_VERBOSE, "%a: rounded UC32 base from 0x%x up to 0x%x, for " > + "an UC32 size of 0x%x\n", __FUNCTION__, (UINT32)LowerMemorySize, > + mQemuUc32Base, Uc32Size)); > + } > + > + Status = MtrrSetMemoryAttribute (mQemuUc32Base, Uc32Size, > + CacheUncacheable); > ASSERT_EFI_ERROR (Status); > + } else { > + mQemuUc32Base = (UINT32)LowerMemorySize; > } > } > > diff --git a/OvmfPkg/PlatformPei/Platform.c b/OvmfPkg/PlatformPei/Platform.c > index fd8eccaf3e50..c064b4ed9b8f 100644 > --- a/OvmfPkg/PlatformPei/Platform.c > +++ b/OvmfPkg/PlatformPei/Platform.c > @@ -174,14 +174,12 @@ MemMapInitialization ( > AddIoMemoryRangeHob (0x0A0000, BASE_1MB); > > if (!mXen) { > - UINT32 TopOfLowRam; > UINT64 PciExBarBase; > UINT32 PciBase; > UINT32 PciSize; > > - TopOfLowRam = GetSystemMemorySizeBelow4gb (); > PciExBarBase = 0; > - PciBase = (TopOfLowRam < BASE_2GB) ? BASE_2GB : TopOfLowRam; > + PciBase = (mQemuUc32Base < BASE_2GB) ? BASE_2GB : mQemuUc32Base; > if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) { > // > // The 32-bit PCI host aperture is expected to fall between the top of > -- > 2.19.1.3.g30247aa5d201 >