From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:4864:20::d41; helo=mail-io1-xd41.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-io1-xd41.google.com (mail-io1-xd41.google.com [IPv6:2607:f8b0:4864:20::d41]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 7AC73211C7F39 for ; Sun, 3 Feb 2019 04:39:34 -0800 (PST) Received: by mail-io1-xd41.google.com with SMTP id c2so9646441iom.12 for ; Sun, 03 Feb 2019 04:39:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=vdUL/wIDJPYVwhMKh1ESZ/JOCXZumM/nshfwcS977JY=; b=e3gdcmrXtb561+NsxygtKMgAFCpUkbMjwQCiWrvALbYyH44dupvObXGAju/BekzNqN lHGxmp/EB90gB4877L7zFrVFxAgAbuVO5v6uZQpQDd7VoqGbwfuB9Qiut1tY7BN+f4i2 Y/itP4uC8dwyAspFywetPAWMfuGmBMdy+e2wc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=vdUL/wIDJPYVwhMKh1ESZ/JOCXZumM/nshfwcS977JY=; b=Thova+LqznUg42LB0/eAYdnHRqr8MUI7au0ydBkQM5W6uXAyAM9eNQO2ZOXKiQDn1F vrwFE0CmjdtsTskVOs6sedAmfrH5laaWjGB9jNLwiJOp6TE4xPEwFp1d3K1U8WItTJ34 cGP+uCy0wr8dE5LIg8X4+ZjiGrhZm5FtM1h4QlXliFqaCn7FK1rGG9tY9LoeD+Hgjp2g ER9Fgv/tHCx4hNV09CNj0jXOcoF5N7u+0uZbgW3Gi9NkPvIHBGR7XGuyoTMDJKyEFW9a P35wrxusGNfDOAEp6YxQfqdoT78bLpmVXoG4KRqLAPLtOBgKXj1OnmtC3OtrG4fUZsjX dPFw== X-Gm-Message-State: AHQUAub2AARUreKIK7iZhHYU0lJ0nP9yRKxmNqU3s65vxxn/J64c1RL6 SeTgNNr0BS/WgdNHLbF+V+ZQjZOAnKVczliCcZ42eQ== X-Google-Smtp-Source: AHgI3IZf8/k27WJ7UQVlmoxw7OJJI91sdyPZTRWRIyeOACAwbKDAxUp5sVTjmRikpK3AVNlzYH+ujNtxDQW06sPxDKQ= X-Received: by 2002:a6b:5d01:: with SMTP id r1mr12743104iob.170.1549197573278; Sun, 03 Feb 2019 04:39:33 -0800 (PST) MIME-Version: 1.0 References: <7a0d5c95fdeee0e68f54c8a6a0fbe37c85e76774.1548892644.git.jbrasen@nvidia.com> In-Reply-To: From: Ard Biesheuvel Date: Sun, 3 Feb 2019 13:39:21 +0100 Message-ID: To: "Wu, Hao A" Cc: Jeff Brasen , "edk2-devel@lists.01.org" , Edgar Handal , Marcin Wojtas Subject: Re: [PATCH] MdeModulePkg/SdMmcPciHcDxe: Use 16/32-bit IO widths X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 03 Feb 2019 12:39:34 -0000 Content-Type: text/plain; charset="UTF-8" On Fri, 1 Feb 2019 at 06:55, Wu, Hao A wrote: > > > -----Original Message----- > > From: edk2-devel [mailto:edk2-devel-bounces@lists.01.org] On Behalf Of Jeff > > Brasen > > Sent: Thursday, January 31, 2019 7:59 AM > > To: edk2-devel@lists.01.org > > Cc: Edgar Handal; Jeff Brasen > > Subject: [edk2] [PATCH] MdeModulePkg/SdMmcPciHcDxe: Use 16/32-bit IO > > widths > > > > From: Edgar Handal > > > > Use 16-bit and 32-bit IO widths for SDMMC MMIO to prevent all register > > accesses from being split up into 8-bit accesses. > > > > The SDHCI specification states that the registers shall be accessable in > > byte, word, and double word accesses. > Acked-by: Ard Biesheuvel I think we should always prefer accessing MMIO registers using their native size, unless there are pressing reasons not to. > Hi, > > Thanks for the contribution. The change seems good to me. > > Just curious, if the accesses are always slit into byte(8-bit), is there any > issue or performance impact is encountered during your usage? > > It will be helpful to get more information on the purpose of the patch. > Thanks. > > Best Regards, > Hao Wu > > > > > Contributed-under: TianoCore Contribution Agreement 1.1 > > Signed-off-by: Jeff Brasen > > --- > > MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c | 25 > > ++++++++++++++++++++---- > > 1 file changed, 21 insertions(+), 4 deletions(-) > > > > diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c > > b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c > > index 5aec8c6..82f4493 100644 > > --- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c > > +++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c > > @@ -152,19 +152,36 @@ SdMmcHcRwMmio ( > > ) > > { > > EFI_STATUS Status; > > + EFI_PCI_IO_PROTOCOL_WIDTH Width; > > > > if ((PciIo == NULL) || (Data == NULL)) { > > return EFI_INVALID_PARAMETER; > > } > > > > - if ((Count != 1) && (Count != 2) && (Count != 4) && (Count != 8)) { > > - return EFI_INVALID_PARAMETER; > > + switch (Count) { > > + case 1: > > + Width = EfiPciIoWidthUint8; > > + break; > > + case 2: > > + Width = EfiPciIoWidthUint16; > > + Count = 1; > > + break; > > + case 4: > > + Width = EfiPciIoWidthUint32; > > + Count = 1; > > + break; > > + case 8: > > + Width = EfiPciIoWidthUint32; > > + Count = 2; > > + break; > > + default: > > + return EFI_INVALID_PARAMETER; > > } > > > > if (Read) { > > Status = PciIo->Mem.Read ( > > PciIo, > > - EfiPciIoWidthUint8, > > + Width, > > BarIndex, > > (UINT64) Offset, > > Count, > > @@ -173,7 +190,7 @@ SdMmcHcRwMmio ( > > } else { > > Status = PciIo->Mem.Write ( > > PciIo, > > - EfiPciIoWidthUint8, > > + Width, > > BarIndex, > > (UINT64) Offset, > > Count, > > -- > > 2.7.4 > > > > _______________________________________________ > > edk2-devel mailing list > > edk2-devel@lists.01.org > > https://lists.01.org/mailman/listinfo/edk2-devel > _______________________________________________ > edk2-devel mailing list > edk2-devel@lists.01.org > https://lists.01.org/mailman/listinfo/edk2-devel