From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-wm1-f65.google.com (mail-wm1-f65.google.com [209.85.128.65]) by mx.groups.io with SMTP id smtpd.web12.6519.1574947789924290140 for ; Thu, 28 Nov 2019 05:29:50 -0800 Authentication-Results: mx.groups.io; dkim=pass header.i=@linaro.org header.s=google header.b=fluhvfMe; spf=pass (domain: linaro.org, ip: 209.85.128.65, mailfrom: ard.biesheuvel@linaro.org) Received: by mail-wm1-f65.google.com with SMTP id s14so4879274wmh.4 for ; Thu, 28 Nov 2019 05:29:49 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=QHkSo8zsDnyP99FXMXKFicq4qaxE9tDEwGhKwWdbC9o=; b=fluhvfMeX1Xk0AvxMkk9m/jHX/evniN7mwY4l3k4nclMtFs3VpDvvPZ/yBMRRuiAoC vs0bMUi8o15KwVzbqwuT2dPg1zGeYj0NZePOlfszCtLigGcq17gnHkvFgTupjtH3JgE/ crSFQRTWnqj1pFffZAloQ/RD5a/mh+vpJxrvYQ4Cc5qTaxR0ACiGdQQyhi+z4Spac4iJ JeSNONLG0IG8s50UngsDgG79C3p6ypUMY/yJ6rEU6uPATWSCe/eCVG5jRWWbmdAYEeet dJKi3l9QDsKejt3HMu+av0lx4g0oSfa4JsGFr3KBaQ2tCuNxQik3EHMe/mIAaXqqkLWa 3WBQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=QHkSo8zsDnyP99FXMXKFicq4qaxE9tDEwGhKwWdbC9o=; b=CBHSDM2Im0qAkKPLgTCcfTQE0rqvZR51zFTwdff78lvqCEJlOYePGHjGRUQQ12T79V jxN9XcmzwKZw9sU6xRW4SqXPiluELB1F1/P/ewSI+C2bvqXA013zRLX+qbhj4HzWWKer T7sAjNyFDliPtGJ+iuQg2Ry5GVn4yGyDFayZkC+xQI42VuuNQgMLzFUdPm4pgyAmOEj+ GOEdpYZfZ+b2Lu4IR5n07gHYwWRUUry1SvS+VKdkT1vCoHWYzHLtF7qNlkxoZsiOMRUe BUYPI/6cD+rICim+3MiUljtumuL4g9cgn4dJp4XsN7ahXyoncA30Zynb4irtsPbJvNUi N7Cg== X-Gm-Message-State: APjAAAWY/XB6e7O7ntYeR3T5ImROcH44qluzKkdBoWHDj6+LkmaXtJlD SWSFtgtHS1KZOirPC9PA2aVYWrCF3SSeudwokrqpBA== X-Google-Smtp-Source: APXvYqw8dZdGPv8z04fz/PSxEmv7HOVtxEg4/kI9jcQwFxkH5UGmiOCdp/TU/xqmuliUidvDLVUbS7jpJwwAw4xI0jc= X-Received: by 2002:a1c:49c3:: with SMTP id w186mr9644372wma.53.1574947788323; Thu, 28 Nov 2019 05:29:48 -0800 (PST) MIME-Version: 1.0 References: <20191127184439.16793-1-ard.biesheuvel@linaro.org> <20191127184439.16793-6-ard.biesheuvel@linaro.org> <20191128132244.GO7359@bivouac.eciton.net> In-Reply-To: <20191128132244.GO7359@bivouac.eciton.net> From: "Ard Biesheuvel" Date: Thu, 28 Nov 2019 14:29:52 +0100 Message-ID: Subject: Re: [PATCH edk2-platforms v2 5/8] Silicon/AMD/StyxDtbLoaderLib: add interrupt-affinity property to PMU node To: Leif Lindholm Cc: edk2-devel-groups-io Content-Type: text/plain; charset="UTF-8" On Thu, 28 Nov 2019 at 14:22, Leif Lindholm wrote: > > On Wed, Nov 27, 2019 at 19:44:36 +0100, Ard Biesheuvel wrote: > > AMD Seattle uses a range of SPIs to signal PMU events, and this requires > > a description in the DT which SPI maps to which CPU. This requires us to > > defer the generation of the PMU node to a point where the CPU phandles > > have been allocated. > > Ah, so these were previously populated with garbage? Oops. > No, not really. Moving the code obfuscates it a bit, but the new code has an additional fdt_appendprop_cell() to set "interrupt-affinity" which was missing entirely before. > > Signed-off-by: Ard Biesheuvel > > Reviewed-by: Leif Lindholm > Thanks, > > --- > > Silicon/AMD/Styx/Library/StyxDtbLoaderLib/StyxDtbLoaderLib.c | 55 ++++++++++---------- > > 1 file changed, 28 insertions(+), 27 deletions(-) > > > > diff --git a/Silicon/AMD/Styx/Library/StyxDtbLoaderLib/StyxDtbLoaderLib.c b/Silicon/AMD/Styx/Library/StyxDtbLoaderLib/StyxDtbLoaderLib.c > > index 261b5f59c8df..2f7b5e2a7b25 100644 > > --- a/Silicon/AMD/Styx/Library/StyxDtbLoaderLib/StyxDtbLoaderLib.c > > +++ b/Silicon/AMD/Styx/Library/StyxDtbLoaderLib/StyxDtbLoaderLib.c > > @@ -331,33 +331,6 @@ PrepareFdt ( > > // Get Id from primary CPU > > MpId = (UINTN)ArmReadMpidr (); > > > > - // Create /pmu node > > - PmuNode = fdt_add_subnode(Fdt, 0, "pmu"); > > - if (PmuNode >= 0) { > > - fdt_setprop_string (Fdt, PmuNode, "compatible", "arm,armv8-pmuv3"); > > - > > - // append PMU interrupts > > - for (Index = 0; Index < ArmCoreCount; Index++) { > > - MpId = (UINTN)GET_MPID (ArmCoreInfoTable[Index].ClusterId, > > - ArmCoreInfoTable[Index].CoreId); > > - > > - Status = AmdMpCoreInfoProtocol->GetPmuSpiFromMpId (MpId, &PmuInt.IntId); > > - if (EFI_ERROR (Status)) { > > - DEBUG ((DEBUG_ERROR, > > - "FDT: Error getting PMU interrupt for MpId '0x%x'\n", MpId)); > > - return Status; > > - } > > - > > - PmuInt.Flag = cpu_to_fdt32 (PMU_INT_FLAG_SPI); > > - PmuInt.IntId = cpu_to_fdt32 (PmuInt.IntId); > > - PmuInt.Type = cpu_to_fdt32 (PMU_INT_TYPE_HIGH_LEVEL); > > - fdt_appendprop (Fdt, PmuNode, "interrupts", &PmuInt, sizeof(PmuInt)); > > - } > > - } else { > > - DEBUG ((DEBUG_ERROR, "FDT: Error creating 'pmu' node\n")); > > - return EFI_INVALID_PARAMETER; > > - } > > - > > // Create /cpus noide > > Node = fdt_add_subnode (Fdt, 0, "cpus"); > > if (Node >= 0) { > > @@ -449,6 +422,34 @@ PrepareFdt ( > > return EFI_INVALID_PARAMETER; > > } > > > > + // Create /pmu node > > + PmuNode = fdt_add_subnode(Fdt, 0, "pmu"); > > + if (PmuNode >= 0) { > > + fdt_setprop_string (Fdt, PmuNode, "compatible", "arm,armv8-pmuv3"); > > + > > + // append PMU interrupts > > + for (Index = 0; Index < ArmCoreCount; Index++) { > > + MpId = (UINTN)GET_MPID (ArmCoreInfoTable[Index].ClusterId, > > + ArmCoreInfoTable[Index].CoreId); > > + > > + Status = AmdMpCoreInfoProtocol->GetPmuSpiFromMpId (MpId, &PmuInt.IntId); > > + if (EFI_ERROR (Status)) { > > + DEBUG ((DEBUG_ERROR, > > + "FDT: Error getting PMU interrupt for MpId '0x%x'\n", MpId)); > > + return Status; > > + } > > + > > + PmuInt.Flag = cpu_to_fdt32 (PMU_INT_FLAG_SPI); > > + PmuInt.IntId = cpu_to_fdt32 (PmuInt.IntId); > > + PmuInt.Type = cpu_to_fdt32 (PMU_INT_TYPE_HIGH_LEVEL); > > + fdt_appendprop (Fdt, PmuNode, "interrupts", &PmuInt, sizeof(PmuInt)); > > + fdt_appendprop_cell (Fdt, PmuNode, "interrupt-affinity", Phandle[Index]); > > + } > > + } else { > > + DEBUG ((DEBUG_ERROR, "FDT: Error creating 'pmu' node\n")); > > + return EFI_INVALID_PARAMETER; > > + } > > + > > SetSocIdStatus (Fdt); > > SetXgbeStatus (Fdt); > > > > -- > > 2.17.1 > >