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From: Ard Biesheuvel <ard.biesheuvel@linaro.org>
To: Marcin Wojtas <mw@semihalf.com>
Cc: "edk2-devel@lists.01.org" <edk2-devel@lists.01.org>,
	"Leif Lindholm" <leif.lindholm@linaro.org>,
	"Nadav Haklai" <nadavh@marvell.com>,
	"Neta Zur Hershkovits" <neta@marvell.com>,
	"Kostya Porotchkin" <kostap@marvell.com>,
	jinghua@marvell.com, "Alexander Graf" <agraf@suse.de>,
	"Jan Dąbroś" <jsd@semihalf.com>
Subject: Re: [platforms: PATCH 6/7] Drivers/Net/Pp2Dxe: Move devices description to MvHwDescLib
Date: Fri, 1 Sep 2017 10:33:24 +0100	[thread overview]
Message-ID: <CAKv+Gu_wpR_dfyeUQd84jWQcS38fz34TrWNNhW0U8ipFAqnBYw@mail.gmail.com> (raw)
In-Reply-To: <1504233451-6455-7-git-send-email-mw@semihalf.com>

On 1 September 2017 at 03:37, Marcin Wojtas <mw@semihalf.com> wrote:
> This patch introduces Pp2Dxe description, using the new structures
> and template in MvHwDescLib. This change enables more flexible
> addition of multiple Pp2Dxe controllers. For that purpose, static global
> variables (BufferLocation and Mvpp2Shared) had to be replaced by
> dynamically allocated resources. PortingGuide is updated accordingly.
>
> Contributed-under: TianoCore Contribution Agreement 1.0
> Signed-off-by: Marcin Wojtas <mw@semihalf.com>

Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>

> ---
>  Platform/Marvell/Armada/Armada70x0.dsc             |   3 +-
>  .../Marvell/Documentation/PortingGuide/Pp2.txt     |   9 +-
>  Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.c       | 109 ++++++++++++++++-----
>  Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.h       |  19 ++--
>  Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.inf     |   3 +-
>  Platform/Marvell/Include/Library/MvHwDescLib.h     |  26 +++++
>  Platform/Marvell/Marvell.dec                       |   3 +-
>  7 files changed, 125 insertions(+), 47 deletions(-)
>
> diff --git a/Platform/Marvell/Armada/Armada70x0.dsc b/Platform/Marvell/Armada/Armada70x0.dsc
> index bbe6ba5..334bfaa 100644
> --- a/Platform/Marvell/Armada/Armada70x0.dsc
> +++ b/Platform/Marvell/Armada/Armada70x0.dsc
> @@ -121,13 +121,12 @@
>
>    #NET
>    gMarvellTokenSpaceGuid.PcdPhySmiAddresses|{ 0xff, 0x0, 0x1 }
> -  gMarvellTokenSpaceGuid.PcdPp2ClockFrequency|333333333
>    gMarvellTokenSpaceGuid.PcdPp2GopIndexes|{ 0x0, 0x2, 0x3 }
>    gMarvellTokenSpaceGuid.PcdPp2InterfaceAlwaysUp|{ 0x0, 0x0, 0x0 }
>    gMarvellTokenSpaceGuid.PcdPp2InterfaceSpeed|{ 0x5, 0x3, 0x3 }
>    gMarvellTokenSpaceGuid.PcdPp2NumPorts|3
>    gMarvellTokenSpaceGuid.PcdPp2PortIds|{ 0x0, 0x1, 0x2 }
> -  gMarvellTokenSpaceGuid.PcdPp2SharedAddress|0xf2000000
> +  gMarvellTokenSpaceGuid.PcdPp2Controllers|{ 0x1 }
>
>    #PciEmulation
>    gMarvellTokenSpaceGuid.PcdPciEXhci|{ 0x1, 0x1, 0x0, 0x0 }
> diff --git a/Platform/Marvell/Documentation/PortingGuide/Pp2.txt b/Platform/Marvell/Documentation/PortingGuide/Pp2.txt
> index 3c2f418..9b829c9 100644
> --- a/Platform/Marvell/Documentation/PortingGuide/Pp2.txt
> +++ b/Platform/Marvell/Documentation/PortingGuide/Pp2.txt
> @@ -3,6 +3,9 @@ Pp2Dxe porting guide
>  Pp2Dxe is driver supporting PP2 NIC on Marvell platforms. Following PCDs
>  are required to operate:
>
> +Array with used controllers - Set to 0x1 for enabled, 0x0 for disabled:
> +  gMarvellTokenSpaceGuid.PcdPp2Controllers
> +
>  Number of ports/network interfaces:
>    gMarvellTokenSpaceGuid.PcdPp2NumPorts
>
> @@ -30,9 +33,3 @@ PHY_SPEED (in Mbps) is defined as follows:
>    4  SPEED_2500,
>    5  SPEED_10000
>    } PHY_SPEED;
> -
> -Base address of shared register space of PP2:
> -  gMarvellTokenSpaceGuid.PcdPp2SharedAddress
> -
> -TCLK frequency in Hz:
> -  gMarvellTokenSpaceGuid.PcdPp2ClockFrequency
> diff --git a/Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.c b/Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.c
> index 42cf0f9..8e6bfbc 100644
> --- a/Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.c
> +++ b/Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.c
> @@ -42,6 +42,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
>  #include <Library/DebugLib.h>
>  #include <Library/IoLib.h>
>  #include <Library/MemoryAllocationLib.h>
> +#include <Library/MvHwDescLib.h>
>  #include <Library/NetLib.h>
>  #include <Library/PcdLib.h>
>  #include <Library/UefiBootServicesTableLib.h>
> @@ -53,8 +54,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
>
>  #define ReturnUnlock(tpl, status) do { gBS->RestoreTPL (tpl); return (status); } while(0)
>
> -STATIC MVPP2_SHARED *Mvpp2Shared;
> -STATIC BUFFER_LOCATION BufferLocation;
> +DECLARE_A7K8K_PP2_TEMPLATE;
> +
>  STATIC PP2_DEVICE_PATH Pp2DevicePathTemplate = {
>    {
>      {
> @@ -172,7 +173,7 @@ QueueRemove (
>  STATIC
>  EFI_STATUS
>  Pp2DxeBmPoolInit (
> -  VOID
> +  MVPP2_SHARED *Mvpp2Shared
>    )
>  {
>    INTN          Index;
> @@ -233,7 +234,7 @@ FreePools:
>  STATIC
>  EFI_STATUS
>  Pp2DxeBmStart (
> -  VOID
> +  MVPP2_SHARED *Mvpp2Shared
>    )
>  {
>    UINT8 *Buff, *BuffPhys;
> @@ -247,7 +248,7 @@ Pp2DxeBmStart (
>
>      /* Fill BM pool with Buffers */
>      for (Index = 0; Index < MVPP2_BM_SIZE; Index++) {
> -      Buff = (UINT8 *)(BufferLocation.RxBuffers[Pool] + (Index * RX_BUFFER_SIZE));
> +      Buff = (UINT8 *)(Mvpp2Shared->BufferLocation.RxBuffers[Pool] + (Index * RX_BUFFER_SIZE));
>        if (Buff == NULL) {
>          return EFI_OUT_OF_RESOURCES;
>        }
> @@ -342,6 +343,7 @@ Pp2DxeSetupAggrTxqs (
>    )
>  {
>    MVPP2_TX_QUEUE *AggrTxq;
> +  MVPP2_SHARED *Mvpp2Shared = Pp2Context->Port.Priv;
>
>    AggrTxq = Mvpp2Shared->AggrTxqs;
>    AggrTxq->DescsPhys = (DmaAddrT)AggrTxq->Descs;
> @@ -361,6 +363,7 @@ Pp2DxeOpen (
>    )
>  {
>    PP2DXE_PORT *Port = &Pp2Context->Port;
> +  MVPP2_SHARED *Mvpp2Shared = Pp2Context->Port.Priv;
>    UINT8 MacBcast[NET_ETHER_ADDR_LEN] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
>    UINT8 DevAddr[NET_ETHER_ADDR_LEN];
>    INTN Ret;
> @@ -412,6 +415,7 @@ Pp2DxeLatePortInitialize (
>    )
>  {
>    PP2DXE_PORT *Port = &Pp2Context->Port;
> +  MVPP2_SHARED *Mvpp2Shared = Pp2Context->Port.Priv;
>    INTN Queue;
>
>    Port->TxRingSize = MVPP2_MAX_TXD;
> @@ -428,7 +432,7 @@ Pp2DxeLatePortInitialize (
>    }
>
>    /* Use preallocated area */
> -  Port->Txqs[0].Descs = BufferLocation.TxDescs[Port->Id];
> +  Port->Txqs[0].Descs = Mvpp2Shared->BufferLocation.TxDescs[Port->Id];
>
>    for (Queue = 0; Queue < TxqNumber; Queue++) {
>      MVPP2_TX_QUEUE *Txq = &Port->Txqs[Queue];
> @@ -444,7 +448,7 @@ Pp2DxeLatePortInitialize (
>      return EFI_OUT_OF_RESOURCES;
>    }
>
> -  Port->Rxqs[0].Descs = BufferLocation.RxDescs[Port->Id];
> +  Port->Rxqs[0].Descs = Mvpp2Shared->BufferLocation.RxDescs[Port->Id];
>
>    for (Queue = 0; Queue < TxqNumber; Queue++) {
>      MVPP2_RX_QUEUE *Rxq = &Port->Rxqs[Queue];
> @@ -666,6 +670,7 @@ Pp2DxeHalt (
>  {
>    PP2DXE_CONTEXT *Pp2Context = Context;
>    PP2DXE_PORT *Port = &Pp2Context->Port;
> +  MVPP2_SHARED *Mvpp2Shared = Pp2Context->Port.Priv;
>    STATIC BOOLEAN CommonPartHalted = FALSE;
>    INTN Index;
>
> @@ -737,6 +742,7 @@ Pp2SnpStationAddress (
>    PP2DXE_CONTEXT *Pp2Context = INSTANCE_FROM_SNP(Snp);
>    PP2_DEVICE_PATH *Pp2DevicePath = Pp2Context->DevicePath;
>    PP2DXE_PORT *Port = &Pp2Context->Port;
> +  MVPP2_SHARED *Mvpp2Shared = Pp2Context->Port.Priv;
>    UINT32 State = Snp->Mode->State;
>    EFI_TPL SavedTpl;
>    INTN Ret;
> @@ -877,6 +883,7 @@ Pp2SnpTransmit (
>  {
>    PP2DXE_CONTEXT *Pp2Context = INSTANCE_FROM_SNP(This);
>    PP2DXE_PORT *Port = &Pp2Context->Port;
> +  MVPP2_SHARED *Mvpp2Shared = Pp2Context->Port.Priv;
>    MVPP2_TX_QUEUE *AggrTxq = Mvpp2Shared->AggrTxqs;
>    MVPP2_TX_DESC *TxDesc;
>    EFI_STATUS Status;
> @@ -1002,6 +1009,7 @@ Pp2SnpReceive (
>    INTN ReceivedPackets;
>    PP2DXE_CONTEXT *Pp2Context = INSTANCE_FROM_SNP(This);
>    PP2DXE_PORT *Port = &Pp2Context->Port;
> +  MVPP2_SHARED *Mvpp2Shared = Pp2Context->Port.Priv;
>    UINTN PhysAddr, VirtAddr;
>    EFI_STATUS Status = EFI_SUCCESS;
>    EFI_TPL SavedTpl;
> @@ -1160,11 +1168,12 @@ Pp2DxeParsePortPcd (
>    Pp2Context->Port.Speed = Speed[Pp2Context->Instance];
>  }
>
> +STATIC
>  EFI_STATUS
> -EFIAPI
> -Pp2DxeInitialise (
> -  IN EFI_HANDLE ImageHandle,
> -  IN EFI_SYSTEM_TABLE *SystemTable
> +Pp2DxeInitialiseController (
> +  IN MVPP2_SHARED *Mvpp2Shared,
> +  IN UINTN BaseAddress,
> +  IN UINTN ClockFrequency
>    )
>  {
>    PP2DXE_CONTEXT *Pp2Context = NULL;
> @@ -1179,19 +1188,12 @@ Pp2DxeInitialise (
>      return EFI_INVALID_PARAMETER;
>    }
>
> -  /* Initialize private data */
> -  Mvpp2Shared = AllocateZeroPool (sizeof (MVPP2_SHARED));
> -  if (Mvpp2Shared == NULL) {
> -    DEBUG((DEBUG_ERROR, "Allocation fail.\n"));
> -    return EFI_OUT_OF_RESOURCES;
> -  }
> -
> -  Mvpp2Shared->Base = PcdGet64 (PcdPp2SharedAddress);
> +  Mvpp2Shared->Base = BaseAddress;
>    Mvpp2Shared->Rfu1Base = Mvpp2Shared->Base + MVPP22_RFU1_OFFSET;
>    Mvpp2Shared->XpcsBase = Mvpp2Shared->Base + MVPP22_XPCS_OFFSET;
>    Mvpp2Shared->MpcsBase = Mvpp2Shared->Base + MVPP22_MPCS_OFFSET;
>    Mvpp2Shared->SmiBase = Mvpp2Shared->Base + MVPP22_SMI_OFFSET;
> -  Mvpp2Shared->Tclk = PcdGet32 (PcdPp2ClockFrequency);
> +  Mvpp2Shared->Tclk = ClockFrequency;
>
>    /* Prepare buffers */
>    Status = DmaAllocateAlignedBuffer (EfiBootServicesData,
> @@ -1206,21 +1208,21 @@ Pp2DxeInitialise (
>    ZeroMem (BufferSpace, BD_SPACE);
>
>    for (Index = 0; Index < MVPP2_MAX_PORT; Index++) {
> -    BufferLocation.TxDescs[Index] = (MVPP2_TX_DESC *)
> +    Mvpp2Shared->BufferLocation.TxDescs[Index] = (MVPP2_TX_DESC *)
>        (BufferSpace + Index * MVPP2_MAX_TXD * sizeof(MVPP2_TX_DESC));
>    }
>
> -  BufferLocation.AggrTxDescs = (MVPP2_TX_DESC *)
> +  Mvpp2Shared->BufferLocation.AggrTxDescs = (MVPP2_TX_DESC *)
>      ((UINTN)BufferSpace + MVPP2_MAX_TXD * MVPP2_MAX_PORT * sizeof(MVPP2_TX_DESC));
>
>    for (Index = 0; Index < MVPP2_MAX_PORT; Index++) {
> -    BufferLocation.RxDescs[Index] = (MVPP2_RX_DESC *)
> +    Mvpp2Shared->BufferLocation.RxDescs[Index] = (MVPP2_RX_DESC *)
>        ((UINTN)BufferSpace + (MVPP2_MAX_TXD * MVPP2_MAX_PORT + MVPP2_AGGR_TXQ_SIZE) *
>        sizeof(MVPP2_TX_DESC) + Index * MVPP2_MAX_RXD * sizeof(MVPP2_RX_DESC));
>    }
>
>    for (Index = 0; Index < MVPP2_MAX_PORT; Index++) {
> -    BufferLocation.RxBuffers[Index] = (DmaAddrT)
> +    Mvpp2Shared->BufferLocation.RxBuffers[Index] = (DmaAddrT)
>        (BufferSpace + (MVPP2_MAX_TXD * MVPP2_MAX_PORT + MVPP2_AGGR_TXQ_SIZE) *
>        sizeof(MVPP2_TX_DESC) + MVPP2_MAX_RXD * MVPP2_MAX_PORT * sizeof(MVPP2_RX_DESC) +
>        Index * MVPP2_BM_SIZE * RX_BUFFER_SIZE);
> @@ -1228,7 +1230,7 @@ Pp2DxeInitialise (
>
>    /* Initialize HW */
>    Mvpp2AxiConfig(Mvpp2Shared);
> -  Pp2DxeBmPoolInit();
> +  Pp2DxeBmPoolInit (Mvpp2Shared);
>    Mvpp2RxFifoInit(Mvpp2Shared);
>
>    Mvpp2Shared->PrsShadow = AllocateZeroPool (sizeof(MVPP2_PRS_SHADOW) * MVPP2_PRS_TCAM_SRAM_SIZE);
> @@ -1245,7 +1247,7 @@ Pp2DxeInitialise (
>
>    Mvpp2ClsInit(Mvpp2Shared);
>
> -  Status = Pp2DxeBmStart();
> +  Status = Pp2DxeBmStart (Mvpp2Shared);
>    if (EFI_ERROR(Status)) {
>      DEBUG((DEBUG_ERROR, "Pp2Dxe: BM start error\n"));
>      return Status;
> @@ -1258,7 +1260,7 @@ Pp2DxeInitialise (
>      return EFI_OUT_OF_RESOURCES;
>    }
>
> -  Mvpp2Shared->AggrTxqs->Descs = BufferLocation.AggrTxDescs;
> +  Mvpp2Shared->AggrTxqs->Descs = Mvpp2Shared->BufferLocation.AggrTxDescs;
>    Mvpp2Shared->AggrTxqs->Id = 0;
>    Mvpp2Shared->AggrTxqs->LogId = 0;
>    Mvpp2Shared->AggrTxqs->Size = MVPP2_AGGR_TXQ_SIZE;
> @@ -1316,3 +1318,56 @@ Pp2DxeInitialise (
>
>    return EFI_SUCCESS;
>  }
> +
> +EFI_STATUS
> +EFIAPI
> +Pp2DxeInitialise (
> +  IN EFI_HANDLE ImageHandle,
> +  IN EFI_SYSTEM_TABLE *SystemTable
> +  )
> +{
> +  MVHW_PP2_DESC *Desc = &mA7k8kPp2DescTemplate;
> +  UINT8 *Pp2DeviceTable, Index;
> +  MVPP2_SHARED *Mvpp2Shared;
> +  EFI_STATUS Status;
> +
> +  /* Obtain table with enabled Pp2 devices */
> +  Pp2DeviceTable = (UINT8 *)PcdGetPtr (PcdPp2Controllers);
> +  if (Pp2DeviceTable == NULL) {
> +    DEBUG ((DEBUG_ERROR, "Missing PcdPp2Controllers\n"));
> +    return EFI_INVALID_PARAMETER;
> +  }
> +
> +  if (PcdGetSize (PcdPp2Controllers) > MVHW_MAX_PP2_DEVS) {
> +    DEBUG ((DEBUG_ERROR, "Wrong PcdPp2Controllers format\n"));
> +    return EFI_INVALID_PARAMETER;
> +  }
> +
> +  /* Initialize enabled chips */
> +  for (Index = 0; Index < PcdGetSize (PcdPp2Controllers); Index++) {
> +    if (!MVHW_DEV_ENABLED (Pp2, Index)) {
> +      DEBUG ((DEBUG_ERROR, "Skip Pp2 controller %d\n", Index));
> +      continue;
> +    }
> +
> +    /* Initialize private data */
> +    Mvpp2Shared = AllocateZeroPool (sizeof (MVPP2_SHARED));
> +    if (Mvpp2Shared == NULL) {
> +      DEBUG ((DEBUG_ERROR, "Pp2Dxe #%d: Mvpp2Shared allocation fail\n", Index));
> +      return EFI_OUT_OF_RESOURCES;
> +    }
> +
> +    Status = Pp2DxeInitialiseController (
> +                    Mvpp2Shared,
> +                    Desc->Pp2BaseAddresses[Index],
> +                    Desc->Pp2ClockFrequency[Index]
> +                    );
> +    if (EFI_ERROR(Status)) {
> +      FreePool (Mvpp2Shared);
> +      DEBUG ((DEBUG_ERROR, "Pp2Dxe #%d: Controller initialisation fail\n", Index));
> +      return Status;
> +    }
> +  }
> +
> +  return EFI_SUCCESS;
> +}
> diff --git a/Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.h b/Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.h
> index 9e71ec9..7071cef 100644
> --- a/Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.h
> +++ b/Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.h
> @@ -262,6 +262,14 @@ typedef struct {
>
>  typedef struct Pp2DxePort PP2DXE_PORT;
>
> +/* Structure for preallocation for buffer */
> +typedef struct {
> +  MVPP2_TX_DESC *TxDescs[MVPP2_MAX_PORT];
> +  MVPP2_TX_DESC *AggrTxDescs;
> +  MVPP2_RX_DESC *RxDescs[MVPP2_MAX_PORT];
> +  DmaAddrT RxBuffers[MVPP2_MAX_PORT];
> +} BUFFER_LOCATION;
> +
>  /* Shared Packet Processor resources */
>  typedef struct {
>    /* Shared registers' base addresses */
> @@ -271,6 +279,9 @@ typedef struct {
>    UINT64 SmiBase;
>    UINT64 XpcsBase;
>
> +  /* Preallocated buffers */
> +  BUFFER_LOCATION BufferLocation;
> +
>    /* List of pointers to Port structures */
>    PP2DXE_PORT **PortList;
>
> @@ -330,14 +341,6 @@ struct Pp2DxePort {
>    UINT8 FirstRxq;
>  };
>
> -/* Structure for preallocation for buffer */
> -typedef struct {
> -  MVPP2_TX_DESC *TxDescs[MVPP2_MAX_PORT];
> -  MVPP2_TX_DESC *AggrTxDescs;
> -  MVPP2_RX_DESC *RxDescs[MVPP2_MAX_PORT];
> -  DmaAddrT RxBuffers[MVPP2_MAX_PORT];
> -} BUFFER_LOCATION;
> -
>  typedef struct {
>    MAC_ADDR_DEVICE_PATH      Pp2Mac;
>    EFI_DEVICE_PATH_PROTOCOL  End;
> diff --git a/Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.inf b/Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.inf
> index ecd82b6..b67162d 100644
> --- a/Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.inf
> +++ b/Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.inf
> @@ -73,13 +73,12 @@
>  [Pcd]
>    gMarvellTokenSpaceGuid.PcdPhyConnectionTypes
>    gMarvellTokenSpaceGuid.PcdPhySmiAddresses
> -  gMarvellTokenSpaceGuid.PcdPp2ClockFrequency
> +  gMarvellTokenSpaceGuid.PcdPp2Controllers
>    gMarvellTokenSpaceGuid.PcdPp2GopIndexes
>    gMarvellTokenSpaceGuid.PcdPp2InterfaceAlwaysUp
>    gMarvellTokenSpaceGuid.PcdPp2InterfaceSpeed
>    gMarvellTokenSpaceGuid.PcdPp2NumPorts
>    gMarvellTokenSpaceGuid.PcdPp2PortIds
> -  gMarvellTokenSpaceGuid.PcdPp2SharedAddress
>
>  [Depex]
>    TRUE
> diff --git a/Platform/Marvell/Include/Library/MvHwDescLib.h b/Platform/Marvell/Include/Library/MvHwDescLib.h
> index ac8dc37..6a86865 100644
> --- a/Platform/Marvell/Include/Library/MvHwDescLib.h
> +++ b/Platform/Marvell/Include/Library/MvHwDescLib.h
> @@ -85,6 +85,17 @@ typedef struct {
>  } MVHW_NONDISCOVERABLE_DESC;
>
>  //
> +// PP2 NIC devices description template definition
> +//
> +#define MVHW_MAX_PP2_DEVS         4
> +
> +typedef struct {
> +  UINT8 Pp2DevCount;
> +  UINTN Pp2BaseAddresses[MVHW_MAX_PP2_DEVS];
> +  UINTN Pp2ClockFrequency[MVHW_MAX_PP2_DEVS];
> +} MVHW_PP2_DESC;
> +
> +//
>  // RealTimeClock devices description template definition
>  //
>  #define MVHW_MAX_RTC_DEVS         2
> @@ -153,6 +164,21 @@ MVHW_NONDISCOVERABLE_DESC mA7k8kNonDiscoverableDescTemplate = {\
>  }
>
>  //
> +// Platform description of Pp2 NIC devices
> +//
> +#define MVHW_CP0_PP2_BASE       0xF2000000
> +#define MVHW_CP1_PP2_BASE       0xF4000000
> +#define MVHW_PP2_CLK_FREQ       333333333
> +
> +#define DECLARE_A7K8K_PP2_TEMPLATE \
> +STATIC \
> +MVHW_PP2_DESC mA7k8kPp2DescTemplate = {\
> +  2,\
> +  { MVHW_CP0_PP2_BASE, MVHW_CP1_PP2_BASE },\
> +  { MVHW_PP2_CLK_FREQ, MVHW_PP2_CLK_FREQ } \
> +}
> +
> +//
>  // Platform description of RealTimeClock devices
>  //
>  #define MVHW_CP0_RTC0_BASE       0xF2284000
> diff --git a/Platform/Marvell/Marvell.dec b/Platform/Marvell/Marvell.dec
> index 9e2f706..e6a3621 100644
> --- a/Platform/Marvell/Marvell.dec
> +++ b/Platform/Marvell/Marvell.dec
> @@ -169,13 +169,12 @@
>
>  #NET
>    gMarvellTokenSpaceGuid.PcdPhySmiAddresses|{ 0x0 }|VOID*|0x3000024
> -  gMarvellTokenSpaceGuid.PcdPp2ClockFrequency|0|UINT32|0x3000026
> +  gMarvellTokenSpaceGuid.PcdPp2Controllers|{ 0x0 }|VOID*|0x3000028
>    gMarvellTokenSpaceGuid.PcdPp2GopIndexes|{ 0x0 }|VOID*|0x3000029
>    gMarvellTokenSpaceGuid.PcdPp2InterfaceAlwaysUp|{ 0x0 }|VOID*|0x300002A
>    gMarvellTokenSpaceGuid.PcdPp2InterfaceSpeed|{ 0x0 }|VOID*|0x300002B
>    gMarvellTokenSpaceGuid.PcdPp2NumPorts|0|UINT32|0x300002D
>    gMarvellTokenSpaceGuid.PcdPp2PortIds|{ 0x0 }|VOID*|0x300002C
> -  gMarvellTokenSpaceGuid.PcdPp2SharedAddress|0|UINT64|0x300002F
>
>  #PciEmulation
>    gMarvellTokenSpaceGuid.PcdPciEXhci|{ 0x0 }|VOID*|0x3000033
> --
> 1.8.3.1
>


  reply	other threads:[~2017-09-01  9:30 UTC|newest]

Thread overview: 20+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-09-01  2:37 [platforms: PATCH 0/7] Armada 70x0/80x0 network improvements Marcin Wojtas
2017-09-01  2:37 ` [platforms: PATCH 1/7] Drivers/Net/Pp2Dxe: Move registers' description to macros Marcin Wojtas
2017-09-01  9:22   ` Ard Biesheuvel
2017-09-01  2:37 ` [platforms: PATCH 2/7] Drivers/Net/Pp2Dxe: Add SFI support Marcin Wojtas
2017-09-01  9:26   ` Ard Biesheuvel
2017-09-01  9:39     ` Marcin Wojtas
2017-09-01  9:40       ` Ard Biesheuvel
2017-09-01  9:49         ` Marcin Wojtas
2017-09-01  9:51           ` Ard Biesheuvel
2017-09-01  2:37 ` [platforms: PATCH 3/7] Drivers/Net/Pp2Dxe: Support multiple ethernet ports simultaneously Marcin Wojtas
2017-09-01  9:30   ` Ard Biesheuvel
2017-09-01  2:37 ` [platforms: PATCH 4/7] Drivers/Net/Pp2Dxe: Increase amount of ingress resources Marcin Wojtas
2017-09-01  9:30   ` Ard Biesheuvel
2017-09-01  2:37 ` [platforms: PATCH 5/7] Platforms/Marvell: Update ethernet ports types on A70x0 DB Marcin Wojtas
2017-09-01  9:31   ` Ard Biesheuvel
2017-09-01  2:37 ` [platforms: PATCH 6/7] Drivers/Net/Pp2Dxe: Move devices description to MvHwDescLib Marcin Wojtas
2017-09-01  9:33   ` Ard Biesheuvel [this message]
2017-09-01  2:37 ` [platforms: PATCH 7/7] Drivers/Net/Pp2Dxe: Enable using ports from different controllers Marcin Wojtas
2017-09-01  9:34   ` Ard Biesheuvel
2017-09-01  9:27 ` [platforms: PATCH 0/7] Armada 70x0/80x0 network improvements Ard Biesheuvel

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