From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:4001:c06::243; helo=mail-io0-x243.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-io0-x243.google.com (mail-io0-x243.google.com [IPv6:2607:f8b0:4001:c06::243]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 6C1B321E4904E for ; Wed, 14 Mar 2018 07:44:19 -0700 (PDT) Received: by mail-io0-x243.google.com with SMTP id m83so4676876ioi.8 for ; Wed, 14 Mar 2018 07:50:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc; bh=jf3gegOAW6YjXgc4dmgxGFJoA2BgYoCRMNquhwidw9s=; b=dWXekE3dnmTc/GLWnemNXSd1Qv4D1hHcYBLUtH9m19PYIm/ckDxjnhdSbNV38P1zYD Rs7cEiLPM6znYztSu2dihua+QZxxnCW7D8sIptAvXW8OZeMDuoLUDjL7WNHQh/RGlU9z YIANhPDsAZLjNW1lLMFQZQYfZy2zRzs54ouko= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=jf3gegOAW6YjXgc4dmgxGFJoA2BgYoCRMNquhwidw9s=; b=pvqR+Cn+shXf2tGgGEEhEEweyNpBWG+FnOUp7SF0HTqKYX2WqK7df5GmRT54avyJsX 6Mq56Jwqbhnx20dQU9Whi1eSvU+VPYwFn2vJObsF9h+fzL8chT1TK96sVWJse5BGxHzd aSeL0rga61vFi+pxyPLUIBazmXMaqzxxosyLojufR4zWuqTCPBmD52eBckpy51f3Fmg0 YFmOcLlqQ0x+1xbp9F/S26y4tL01RqI8wqCZ4ews6A4ceipmKsxtBtKGQR54CENnHIKR y8O4D7LcRyosPI7ZezMFJ+rbXrSsva0EoNQXmlu+at1RpAQigD5Irzj+jQvjjDRags5a nNUg== X-Gm-Message-State: AElRT7HkBSBYfarlTbTxomZ8jRdjIkiz6WsVLjQEYXNkMNQpblGaBuVf hUbYGFX380gc9SNMDwzAHNNg6Et50L0AFLW73UcSCA== X-Google-Smtp-Source: AG47ELvI+z3CD03Vdr2MnGI7vbBcfzhA+gNvDwEIscIqvzSaR58nQkuv1BnaaO2dkKejh9fXRNyjE6luKZrU0YhvUXQ= X-Received: by 10.107.213.72 with SMTP id x8mr1464800ioc.60.1521039041602; Wed, 14 Mar 2018 07:50:41 -0700 (PDT) MIME-Version: 1.0 Received: by 10.107.138.209 with HTTP; Wed, 14 Mar 2018 07:50:41 -0700 (PDT) In-Reply-To: <86a7vbaynt.wl-marc.zyngier@arm.com> References: <1520901090-96694-1-git-send-email-heyi.guo@linaro.org> <1520901090-96694-2-git-send-email-heyi.guo@linaro.org> <0403f2bf-d6a8-b101-73a2-949946f71e46@arm.com> <20180314002509.GE96299@SZX1000114654> <86a7vbaynt.wl-marc.zyngier@arm.com> From: Ard Biesheuvel Date: Wed, 14 Mar 2018 14:50:41 +0000 Message-ID: To: Marc Zyngier Cc: Guo Heyi , "edk2-devel@lists.01.org" , Yi Li , Leif Lindholm Subject: Re: [PATCH v2 1/1] ArmPkg/TimerDxe: Add ISB for timer compare value reload X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 14 Mar 2018 14:44:19 -0000 Content-Type: text/plain; charset="UTF-8" On 14 March 2018 at 07:45, Marc Zyngier wrote: > On Wed, 14 Mar 2018 00:25:09 +0000, > Guo Heyi wrote: >> >> On Tue, Mar 13, 2018 at 09:33:33AM +0000, Marc Zyngier wrote: >> > On 13/03/18 00:31, Heyi Guo wrote: >> > > If timer interrupt is level sensitive, reloading timer compare >> > > register has a side effect of clearing GIC pending status, so a "ISB" >> > > is needed to make sure this instruction is executed before enabling >> > > CPU IRQ, or else we may get spurious timer interrupts. >> > > >> > > Contributed-under: TianoCore Contribution Agreement 1.1 >> > > Signed-off-by: Heyi Guo >> > > Signed-off-by: Yi Li >> > > Cc: Leif Lindholm >> > > Cc: Ard Biesheuvel >> > > Cc: Marc Zyngier >> > > --- >> > > >> > > Notes: >> > > v2: >> > > - Use ISB instead of DSB [Marc] >> > > - Update commit message accordingly. >> > > >> > > ArmPkg/Drivers/TimerDxe/TimerDxe.c | 1 + >> > > 1 file changed, 1 insertion(+) >> > > >> > > diff --git a/ArmPkg/Drivers/TimerDxe/TimerDxe.c b/ArmPkg/Drivers/TimerDxe/TimerDxe.c >> > > index 33d7c922221f..32abee8726a0 100644 >> > > --- a/ArmPkg/Drivers/TimerDxe/TimerDxe.c >> > > +++ b/ArmPkg/Drivers/TimerDxe/TimerDxe.c >> > > @@ -337,6 +337,7 @@ TimerInterruptHandler ( >> > > >> > > // Set next compare value >> > > ArmGenericTimerSetCompareVal (CompareValue); >> > > + ArmInstructionSynchronizationBarrier (); >> > > ArmGenericTimerEnableTimer (); >> > > } >> > >> > Sorry for being pedantic here, but it would make more sense if ISB was >> > placed after the enabling of the timer. Otherwise, you only force the >> > update of the comparator. But on the other hand, the timer was never >> > disabled the first place, in which case you'd wonder why you're trying >> > to enable it again. >> Yes, I also had such question and hesitated at this place :) >> > >> > So either you leave the ISB here and remove the enable call, or move the >> > ISB after the enable. >> >> If we are going to remove the enable call, is it better to be changed in a >> separate patch? It seems not related with adding ISB, though it is only a >> one-line change. > > I guess a separate patch doesn't hurt, but that's for Ard and Leif to > decide. > Yes, please.