From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by mx.groups.io with SMTP id smtpd.web08.49.1615565095155364911 for ; Fri, 12 Mar 2021 08:04:55 -0800 Authentication-Results: mx.groups.io; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=Mu+iAeqZ; spf=pass (domain: kernel.org, ip: 198.145.29.99, mailfrom: ardb@kernel.org) Received: by mail.kernel.org (Postfix) with ESMTPSA id 7EA1465019 for ; Fri, 12 Mar 2021 16:04:54 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1615565094; bh=xTl2Qm9HqhP3Zb1oD9iLi0xRKnWhj7uHeBIXg5/SgcI=; h=References:In-Reply-To:From:Date:Subject:To:Cc:From; b=Mu+iAeqZXY889gClxCkoP/VBeatrxYI97XOX4/8oRzKIToav1QRlwd7ItIJ78nf2Z EXTHasU824C5HaRTN0OiXv3knmZAGAViIRnq/ecv1ubk6InlRWaat2cUOAfvPgm10R rxnRT9s+clKUNiuoYY12afu6SKGK5I/bVzu8S7F9ifX4BtRZcihfAF62d1bT/EA3Iz 2z0YG2sNIrKl7i9+FWtlkB2iYZvU8f9sWZH/a3qQZFhnCukICWuztgmFjljf0NzgId nUJ8kKjvBKgimX/aKNBhOY6kB82lQQus7Q2FboOnFKMKdDbyQtuJZXlfmQNErYkkrL zjKR/xK5Xz+xg== Received: by mail-ot1-f53.google.com with SMTP id h6-20020a0568300346b02901b71a850ab4so1632339ote.6 for ; Fri, 12 Mar 2021 08:04:54 -0800 (PST) X-Gm-Message-State: AOAM531//utdQxxo+jjDGXjfe4xw3LWJMEU6fBpFgPsdV6Mj71CluBrz Bq/qXiFoLlJpoqhIKvgePFEH4HoYRscalPR0HfQ= X-Google-Smtp-Source: ABdhPJyVInsgM4J/jwHD0qaEFlJyEFtzY2HzFO1X7F+lidRpKWIXxYok3dr2CntrCAeIgvgD9tr0QinzKdypbNkAzJc= X-Received: by 2002:a9d:7512:: with SMTP id r18mr3989435otk.90.1615565093665; Fri, 12 Mar 2021 08:04:53 -0800 (PST) MIME-Version: 1.0 References: In-Reply-To: From: "Ard Biesheuvel" Date: Fri, 12 Mar 2021 17:04:41 +0100 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [edk2-platforms][PATCH 1/1] Silicon/Broadcom/Bcm27xx: Allow more than one device on pcie busses >1 To: =?UTF-8?Q?Ren=C3=A9_Treffer?= Cc: devel@edk2.groups.io, Pete Batard , Leif Lindholm , Ard Biesheuvel , "Andrei Warkentin (awarkentin@vmware.com)" , Jeremy Linton , Samer El-Haj-Mahmoud Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Thu, 11 Mar 2021 at 23:56, Ren=C3=A9 Treffer wrote: > > There is only a single pcie port on the bcm2711 so limiting the number of > devices to 1 worked as long as there is no way to add a pcie switch. > > On the compute module 4 it is possible to add a pcie switch (tested with > asm1184e) which adds 5 new pcie busses. > > In the current state the pci enumeration fails for the pcie switch > internal bus (usually bus 2, device 1,3,5,7). The root port gets > configured with > subordniate=3D0x2 after enumeration. That blocks e.g. linux from discover= ing > devices behind the switch. > > Devices behind the switch work after lifting the device limit on busses > other than 0 and 1. Please include a signed-off-by line > --- > .../Library/Bcm2711PciSegmentLib/PciSegmentLib.c | 14 +++++++------- > 1 file changed, 7 insertions(+), 7 deletions(-) > > diff --git > a/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciSegmentLib/PciSegmentLib.c > b/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciSegmentLib/PciSegmentLib.c > index 44ce3b4b99..4af9374d23 100644 > --- a/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciSegmentLib/PciSegmentLib= .c > +++ b/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciSegmentLib/PciSegmentLib= .c > @@ -78,6 +78,7 @@ PciSegmentLibGetConfigBase ( > UINT64 Base; > UINT64 Offset; > UINT32 Dev; > + UINT32 Bus; > > Base =3D PCIE_REG_BASE; > Offset =3D Address & 0xFFF; /* Pick off the 4k register offset= */ > @@ -89,17 +90,16 @@ PciSegmentLibGetConfigBase ( > Base +=3D PCIE_EXT_CFG_DATA; > if (mPciSegmentLastAccess !=3D Address) { > Dev =3D EFI_PCI_ADDR_DEV (Address); > + Bus =3D EFI_PCI_ADDR_BUS (Address); > /* > - * Scan things out directly rather than translating the "bus" to > a device, etc.. > - * only we need to limit each bus to a single device. > + * There can only be a single device on bus 1 (downstream of root)= . > + * Subsequent busses (behind a PCIe switch) could have more. > */ > - if (Dev < 1) { > - MmioWrite32 (PCIE_REG_BASE + PCIE_EXT_CFG_INDEX, Address); > - mPciSegmentLastAccess =3D Address; > - } else { > - mPciSegmentLastAccess =3D 0; > + if (Dev > 0 && (Bus =3D=3D 1 || Bus =3D=3D 0)) { > return 0xFFFFFFFF; > } > + MmioWrite32 (PCIE_REG_BASE + PCIE_EXT_CFG_INDEX, Address); > + mPciSegmentLastAccess =3D Address; This looks ok to me, but I'd like Jeremy to confirm, please. > } > } > return Base + Offset; > -- > 2.27.0 > >