[edk2-platforms PATCH 0/6] Marvell multiple PCIE support

[edk2-platforms PATCH 0/6] Marvell multiple PCIE support

[Marcin Wojtas]

This patchset is a preparation for adding a new platform
(CN913x CEx7 Evaluation Board). It modifies a common
Marvell code in order to enable multiple PCIE controllers.
Moreover a default interrupt map is reworked, so that to
support all CP11x south bridge units.  
Last but not least, a custom initialization sequence
can be executed thanks to a new board description library
extension.

More details can be found in the commit logs.
The patchest is publicly available in the github:
https://github.com/semihalf-wojtas-marcin/edk2-platforms/commits/pcie-r20210802

Best regards,
Marcin

Kamil Koczurek (1):
  Marvell: Armada7k8k/OcteonTx: Add multiple PCIE ports support

Marcin Wojtas (5):
  Marvell: Armada7k8k/OcteonTx: Allow memory mapping for more config
    spaces
  Marvell: Armada7k8k/OcteonTx: Allow tuning PCIE config space size
  Marvell: Armada7k8kPciHostBridgeLib: Remove ECAM base limitation
  Marvell: Armada7k8k/OcteonTX: Enable additional board configuration
  Marvell: IcuLib: Rework default interrupt map

 Platform/Marvell/Cn913xDb/Cn9130DbA.dsc.inc                                                 |   7 --
 Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc                                               |   7 --
 Silicon/Marvell/Armada7k8k/Drivers/PlatInitDxe/PlatInitDxe.inf                              |   1 +
 Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLib.inf                          |   1 +
 Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciSegmentLib/PciSegmentLib.inf                |  11 +-
 Silicon/Marvell/Armada7k8k/AcpiTables/IcuInterrupts.h                                       |  48 ++++----
 Silicon/Marvell/Include/Library/ArmadaBoardDescLib.h                                        |  10 ++
 Silicon/Marvell/Library/IcuLib/IcuLib.h                                                     |   6 +-
 Silicon/Marvell/OcteonTx/AcpiTables/T91/IcuInterrupts.h                                     |  61 +++++++----
 Platform/Marvell/Armada70x0Db/Armada70x0DbBoardDescLib/Armada70x0DbBoardDescLib.c           |  11 ++
 Platform/Marvell/Armada80x0Db/Armada80x0DbBoardDescLib/Armada80x0DbBoardDescLib.c           |  11 ++
 Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9130DbABoardDescLib.c                       |  11 ++
 Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9132DbABoardDescLib.c                       |  11 ++
 Platform/SolidRun/Armada80x0McBin/Armada80x0McBinBoardDescLib/Armada80x0McBinBoardDescLib.c |  11 ++
 Silicon/Marvell/Armada7k8k/Drivers/PlatInitDxe/PlatInitDxe.c                                |   2 +
 Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLibMem.c                         |  18 ++-
 Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciHostBridgeLib/PciHostBridgeLib.c            |  15 ++-
 Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciHostBridgeLib/PciHostBridgeLibConstructor.c |   1 -
 Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciSegmentLib/PciSegmentLib.c                  |  69 +++++++++++-
 Silicon/Marvell/Library/IcuLib/IcuLib.c                                                     | 115 ++++++--------------
 20 files changed, 267 insertions(+), 160 deletions(-)

-- 
2.29.0

[edk2-platforms PATCH 1/6] Marvell: Armada7k8k/OcteonTx: Allow memory mapping for more config spaces

[Marcin Wojtas]

Until now the virtual memory map for the single PCIE configuration space
was hardcoded via PCDs and assumed adjacency to the SoC MMIO region
(0xf0000000 - 4GB). Remove this limitation by splitting the regions
and allowing to obtain the PCIE configuration space settings
from ArmadaBoardDescLib. It is a preparation patch for adding
support for multiple PCIE controllers.

Signed-off-by: Marcin Wojtas <mw@semihalf.com>
---
 Platform/Marvell/Cn913xDb/Cn9130DbA.dsc.inc                         |  3 ---
 Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc                       |  3 ---
 Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLib.inf  |  1 +
 Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLibMem.c | 16 +++++++++++++++-
 4 files changed, 16 insertions(+), 7 deletions(-)

diff --git a/Platform/Marvell/Cn913xDb/Cn9130DbA.dsc.inc b/Platform/Marvell/Cn913xDb/Cn9130DbA.dsc.inc
index 756d875f6c..41d9cb9247 100644
--- a/Platform/Marvell/Cn913xDb/Cn9130DbA.dsc.inc
+++ b/Platform/Marvell/Cn913xDb/Cn9130DbA.dsc.inc
@@ -100,8 +100,5 @@
   # RTC
   gMarvellTokenSpaceGuid.PcdRtcBaseAddress|0xF2284000
 
-  # SoC Configuration Space
-  gMarvellTokenSpaceGuid.PcdConfigSpaceBaseAddress|0xD0000000
-
   # Variable store
   gMarvellTokenSpaceGuid.PcdSpiMemoryMapped|FALSE
diff --git a/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc b/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc
index d398d9432f..b1aa0ae4d0 100644
--- a/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc
+++ b/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc
@@ -400,9 +400,6 @@
   gArmTokenSpaceGuid.PcdPciIoTranslation|0xEFF00000
   gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xE0000000
 
-  # SoC Configuration Space
-  gMarvellTokenSpaceGuid.PcdConfigSpaceBaseAddress|0xE0000000
-
 !if $(CAPSULE_ENABLE)
 [PcdsDynamicExDefault.common.DEFAULT]
   gEfiSignedCapsulePkgTokenSpaceGuid.PcdEdkiiSystemFirmwareImageDescriptor|{0x0}|VOID*|0x100
diff --git a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLib.inf b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLib.inf
index 94427177ef..8b77a07ab3 100644
--- a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLib.inf
+++ b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLib.inf
@@ -20,6 +20,7 @@
   Silicon/Marvell/Marvell.dec
 
 [LibraryClasses]
+  ArmadaBoardDescLib
   ArmadaSoCDescLib
   ArmLib
   ArmSmcLib
diff --git a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLibMem.c b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLibMem.c
index cc19694d37..853c1b4e56 100644
--- a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLibMem.c
+++ b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLibMem.c
@@ -10,6 +10,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
 #include <IndustryStandard/ArmStdSmc.h>
 #include <IndustryStandard/MvSmc.h>
 
+#include <Library/ArmadaBoardDescLib.h>
 #include <Library/ArmadaSoCDescLib.h>
 #include <Library/ArmPlatformLib.h>
 #include <Library/ArmSmcLib.h>
@@ -81,6 +82,9 @@ ArmPlatformGetVirtualMemoryMap (
   UINT64                        MemHighStart;
   UINT64                        MemHighSize;
   UINT64                        ConfigSpaceBaseAddr;
+  UINTN                         PcieControllerCount;
+  UINTN                         PcieIndex;
+  MV_PCIE_CONTROLLER CONST      *PcieControllers;
   EFI_RESOURCE_ATTRIBUTE_TYPE   ResourceAttributes;
   EFI_STATUS                    Status;
 
@@ -125,12 +129,22 @@ ArmPlatformGetVirtualMemoryMap (
   mVirtualMemoryTable[Index].Length          = MemLowSize;
   mVirtualMemoryTable[Index].Attributes      = DDR_ATTRIBUTES_CACHED;
 
-  // Configuration space
+  // SoC MMIO configuration space
   mVirtualMemoryTable[++Index].PhysicalBase  = ConfigSpaceBaseAddr;
   mVirtualMemoryTable[Index].VirtualBase     = ConfigSpaceBaseAddr;
   mVirtualMemoryTable[Index].Length          = SIZE_4GB - ConfigSpaceBaseAddr;
   mVirtualMemoryTable[Index].Attributes      = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
 
+  // PCIE ECAM
+  Status = ArmadaBoardPcieControllerGet (&PcieControllers, &PcieControllerCount);
+  ASSERT_EFI_ERROR (Status);
+  for (PcieIndex = 0; PcieIndex < PcieControllerCount; PcieIndex++) {
+    mVirtualMemoryTable[++Index].PhysicalBase  = PcieControllers[PcieIndex].ConfigSpaceAddress;
+    mVirtualMemoryTable[Index].VirtualBase     = PcieControllers[PcieIndex].ConfigSpaceAddress;
+    mVirtualMemoryTable[Index].Length = SIZE_256MB;
+    mVirtualMemoryTable[Index].Attributes      = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+  }
+
   if (MemSize > MemLowSize) {
     //
     // If we have more than MemLowSize worth of DRAM, the remainder will be
-- 
2.29.0

[edk2-platforms PATCH 2/6] Marvell: Armada7k8k/OcteonTx: Allow tuning PCIE config space size

[Marcin Wojtas]

Until now it was assumed that the configuration space size is 256MB.
Allow setting different values in the board description library
instance for each platform.

Signed-off-by: Marcin Wojtas <mw@semihalf.com>
---
 Silicon/Marvell/Include/Library/ArmadaBoardDescLib.h                | 1 +
 Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLibMem.c | 4 +++-
 2 files changed, 4 insertions(+), 1 deletion(-)

diff --git a/Silicon/Marvell/Include/Library/ArmadaBoardDescLib.h b/Silicon/Marvell/Include/Library/ArmadaBoardDescLib.h
index 2ad19aae7a..80c55eb3a7 100644
--- a/Silicon/Marvell/Include/Library/ArmadaBoardDescLib.h
+++ b/Silicon/Marvell/Include/Library/ArmadaBoardDescLib.h
@@ -111,6 +111,7 @@ typedef struct {
 typedef struct {
   EFI_PHYSICAL_ADDRESS PcieDbiAddress;
   EFI_PHYSICAL_ADDRESS ConfigSpaceAddress;
+  UINT64 ConfigSpaceSize;
   BOOLEAN HaveResetGpio;
   MV_GPIO_PIN PcieResetGpio;
   UINT64 PcieBusMin;
diff --git a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLibMem.c b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLibMem.c
index 853c1b4e56..43aacb7a11 100644
--- a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLibMem.c
+++ b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLibMem.c
@@ -141,7 +141,9 @@ ArmPlatformGetVirtualMemoryMap (
   for (PcieIndex = 0; PcieIndex < PcieControllerCount; PcieIndex++) {
     mVirtualMemoryTable[++Index].PhysicalBase  = PcieControllers[PcieIndex].ConfigSpaceAddress;
     mVirtualMemoryTable[Index].VirtualBase     = PcieControllers[PcieIndex].ConfigSpaceAddress;
-    mVirtualMemoryTable[Index].Length = SIZE_256MB;
+    mVirtualMemoryTable[Index].Length          = (PcieControllers[PcieIndex].ConfigSpaceSize == 0) ?
+                                                 SIZE_256MB :
+                                                 PcieControllers[PcieIndex].ConfigSpaceSize;
     mVirtualMemoryTable[Index].Attributes      = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
   }
 
-- 
2.29.0

[edk2-platforms PATCH 3/6] Marvell: Armada7k8kPciHostBridgeLib: Remove ECAM base limitation

[Marcin Wojtas]

On CN913x-based platforms it is possible to have up to 9 PCIE
root complexes. In such case it may be necessary to configure
more configuration spaces with smaller bus count, so that
to fit the memory layout constraints. For that purpose remove
forcing ECAM base to be divisible by SIZE_256MB.

Signed-off-by: Marcin Wojtas <mw@semihalf.com>
---
 Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciHostBridgeLib/PciHostBridgeLibConstructor.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciHostBridgeLib/PciHostBridgeLibConstructor.c b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciHostBridgeLib/PciHostBridgeLibConstructor.c
index 067e57a2dc..87e57aeae3 100644
--- a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciHostBridgeLib/PciHostBridgeLibConstructor.c
+++ b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciHostBridgeLib/PciHostBridgeLibConstructor.c
@@ -219,7 +219,6 @@ Armada7k8kPciHostBridgeLibConstructor (
     PcieController = &(BoardPcieDescription->PcieControllers[Index]);
 
     ASSERT (PcieController->PcieBusMin == 0);
-    ASSERT (PcieController->ConfigSpaceAddress % SIZE_256MB == 0);
 
     if (PcieController->HaveResetGpio == TRUE) {
       /* Reset PCIE slot */
-- 
2.29.0

Re: [edk2-platforms PATCH 3/6] Marvell: Armada7k8kPciHostBridgeLib: Remove ECAM base limitation

[Ard Biesheuvel]

On Mon, 2 Aug 2021 at 07:01, Marcin Wojtas <mw@semihalf.com> wrote:
>
> On CN913x-based platforms it is possible to have up to 9 PCIE
> root complexes. In such case it may be necessary to configure
> more configuration spaces with smaller bus count, so that
> to fit the memory layout constraints. For that purpose remove
> forcing ECAM base to be divisible by SIZE_256MB.
>

There is one subtlety here that we need to take into account: IIUC,
PCIe requires that the ECAM start address of bus N equals N MB modulo
256 MB. In other words, if your ECAM range lives at 1 GB + 128 MB, the
bus range has to start at bus 128.

I think OSes are usually quite lax about this, but it is something to
double check regardless, even for existing platforms


> Signed-off-by: Marcin Wojtas <mw@semihalf.com>
> ---
>  Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciHostBridgeLib/PciHostBridgeLibConstructor.c | 1 -
>  1 file changed, 1 deletion(-)
>
> diff --git a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciHostBridgeLib/PciHostBridgeLibConstructor.c b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciHostBridgeLib/PciHostBridgeLibConstructor.c
> index 067e57a2dc..87e57aeae3 100644
> --- a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciHostBridgeLib/PciHostBridgeLibConstructor.c
> +++ b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciHostBridgeLib/PciHostBridgeLibConstructor.c
> @@ -219,7 +219,6 @@ Armada7k8kPciHostBridgeLibConstructor (
>      PcieController = &(BoardPcieDescription->PcieControllers[Index]);
>
>      ASSERT (PcieController->PcieBusMin == 0);
> -    ASSERT (PcieController->ConfigSpaceAddress % SIZE_256MB == 0);
>
>      if (PcieController->HaveResetGpio == TRUE) {
>        /* Reset PCIE slot */
> --
> 2.29.0
>

Re: [edk2-platforms PATCH 3/6] Marvell: Armada7k8kPciHostBridgeLib: Remove ECAM base limitation

[Marcin Wojtas]

Hi Ard,

pon., 2 sie 2021 o 10:43 Ard Biesheuvel <ardb@kernel.org> napisał(a):
>
> On Mon, 2 Aug 2021 at 07:01, Marcin Wojtas <mw@semihalf.com> wrote:
> >
> > On CN913x-based platforms it is possible to have up to 9 PCIE
> > root complexes. In such case it may be necessary to configure
> > more configuration spaces with smaller bus count, so that
> > to fit the memory layout constraints. For that purpose remove
> > forcing ECAM base to be divisible by SIZE_256MB.
> >
>
> There is one subtlety here that we need to take into account: IIUC,
> PCIe requires that the ECAM start address of bus N equals N MB modulo
> 256 MB. In other words, if your ECAM range lives at 1 GB + 128 MB, the
> bus range has to start at bus 128.
>
> I think OSes are usually quite lax about this, but it is something to
> double check regardless, even for existing platforms
>

I tested a wide range of OSs (various Linux distributions, Win10 PE,
FreeBSD, OpenBSD and of course EDK2) and with 7 ECAMs, of which 6 are
squeezed within 256MB memory chunk together with their mmio32 and no
issue was observed. Moreover, if you recall, contrary to the EDK2,
where the full bus number is used, in ACPI we expose a single 1MB
space with the ECAM base address aligned to 0x8000.

Do you wish to change the assertion in EDK2 instead of removing?

Thanks,
Marcin

>
> > Signed-off-by: Marcin Wojtas <mw@semihalf.com>
> > ---
> >  Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciHostBridgeLib/PciHostBridgeLibConstructor.c | 1 -
> >  1 file changed, 1 deletion(-)
> >
> > diff --git a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciHostBridgeLib/PciHostBridgeLibConstructor.c b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciHostBridgeLib/PciHostBridgeLibConstructor.c
> > index 067e57a2dc..87e57aeae3 100644
> > --- a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciHostBridgeLib/PciHostBridgeLibConstructor.c
> > +++ b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciHostBridgeLib/PciHostBridgeLibConstructor.c
> > @@ -219,7 +219,6 @@ Armada7k8kPciHostBridgeLibConstructor (
> >      PcieController = &(BoardPcieDescription->PcieControllers[Index]);
> >
> >      ASSERT (PcieController->PcieBusMin == 0);
> > -    ASSERT (PcieController->ConfigSpaceAddress % SIZE_256MB == 0);
> >
> >      if (PcieController->HaveResetGpio == TRUE) {
> >        /* Reset PCIE slot */
> > --
> > 2.29.0
> >

Re: [edk2-platforms PATCH 3/6] Marvell: Armada7k8kPciHostBridgeLib: Remove ECAM base limitation

[Ard Biesheuvel]

On Mon, 2 Aug 2021 at 19:00, Marcin Wojtas <mw@semihalf.com> wrote:
>
> Hi Ard,
>
> pon., 2 sie 2021 o 10:43 Ard Biesheuvel <ardb@kernel.org> napisał(a):
> >
> > On Mon, 2 Aug 2021 at 07:01, Marcin Wojtas <mw@semihalf.com> wrote:
> > >
> > > On CN913x-based platforms it is possible to have up to 9 PCIE
> > > root complexes. In such case it may be necessary to configure
> > > more configuration spaces with smaller bus count, so that
> > > to fit the memory layout constraints. For that purpose remove
> > > forcing ECAM base to be divisible by SIZE_256MB.
> > >
> >
> > There is one subtlety here that we need to take into account: IIUC,
> > PCIe requires that the ECAM start address of bus N equals N MB modulo
> > 256 MB. In other words, if your ECAM range lives at 1 GB + 128 MB, the
> > bus range has to start at bus 128.
> >
> > I think OSes are usually quite lax about this, but it is something to
> > double check regardless, even for existing platforms
> >
>
> I tested a wide range of OSs (various Linux distributions, Win10 PE,
> FreeBSD, OpenBSD and of course EDK2) and with 7 ECAMs, of which 6 are
> squeezed within 256MB memory chunk together with their mmio32 and no
> issue was observed. Moreover, if you recall, contrary to the EDK2,
> where the full bus number is used, in ACPI we expose a single 1MB
> space with the ECAM base address aligned to 0x8000.
>

Ah yes, I had forgotten about that hack :-)

> Do you wish to change the assertion in EDK2 instead of removing?
>

No worries - if all those OSes are fine with this, I don't see a point
in being pedantic. I will note, however, that you can still comply
with this requirement by changing the bus ranges: each RC only uses a
single bus, but that bus number could be (ECAM base address / 1M) %
256


> >
> > > Signed-off-by: Marcin Wojtas <mw@semihalf.com>
> > > ---
> > >  Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciHostBridgeLib/PciHostBridgeLibConstructor.c | 1 -
> > >  1 file changed, 1 deletion(-)
> > >
> > > diff --git a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciHostBridgeLib/PciHostBridgeLibConstructor.c b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciHostBridgeLib/PciHostBridgeLibConstructor.c
> > > index 067e57a2dc..87e57aeae3 100644
> > > --- a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciHostBridgeLib/PciHostBridgeLibConstructor.c
> > > +++ b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciHostBridgeLib/PciHostBridgeLibConstructor.c
> > > @@ -219,7 +219,6 @@ Armada7k8kPciHostBridgeLibConstructor (
> > >      PcieController = &(BoardPcieDescription->PcieControllers[Index]);
> > >
> > >      ASSERT (PcieController->PcieBusMin == 0);
> > > -    ASSERT (PcieController->ConfigSpaceAddress % SIZE_256MB == 0);
> > >
> > >      if (PcieController->HaveResetGpio == TRUE) {
> > >        /* Reset PCIE slot */
> > > --
> > > 2.29.0
> > >

Re: [edk2-platforms PATCH 3/6] Marvell: Armada7k8kPciHostBridgeLib: Remove ECAM base limitation

[Marcin Wojtas]

wt., 3 sie 2021 o 08:53 Ard Biesheuvel <ardb@kernel.org> napisał(a):
>
> On Mon, 2 Aug 2021 at 19:00, Marcin Wojtas <mw@semihalf.com> wrote:
> >
> > Hi Ard,
> >
> > pon., 2 sie 2021 o 10:43 Ard Biesheuvel <ardb@kernel.org> napisał(a):
> > >
> > > On Mon, 2 Aug 2021 at 07:01, Marcin Wojtas <mw@semihalf.com> wrote:
> > > >
> > > > On CN913x-based platforms it is possible to have up to 9 PCIE
> > > > root complexes. In such case it may be necessary to configure
> > > > more configuration spaces with smaller bus count, so that
> > > > to fit the memory layout constraints. For that purpose remove
> > > > forcing ECAM base to be divisible by SIZE_256MB.
> > > >
> > >
> > > There is one subtlety here that we need to take into account: IIUC,
> > > PCIe requires that the ECAM start address of bus N equals N MB modulo
> > > 256 MB. In other words, if your ECAM range lives at 1 GB + 128 MB, the
> > > bus range has to start at bus 128.
> > >
> > > I think OSes are usually quite lax about this, but it is something to
> > > double check regardless, even for existing platforms
> > >
> >
> > I tested a wide range of OSs (various Linux distributions, Win10 PE,
> > FreeBSD, OpenBSD and of course EDK2) and with 7 ECAMs, of which 6 are
> > squeezed within 256MB memory chunk together with their mmio32 and no
> > issue was observed. Moreover, if you recall, contrary to the EDK2,
> > where the full bus number is used, in ACPI we expose a single 1MB
> > space with the ECAM base address aligned to 0x8000.
> >
>
> Ah yes, I had forgotten about that hack :-)

A great one though.

>
> > Do you wish to change the assertion in EDK2 instead of removing?
> >
>
> No worries - if all those OSes are fine with this, I don't see a point
> in being pedantic. I will note, however, that you can still comply
> with this requirement by changing the bus ranges: each RC only uses a
> single bus, but that bus number could be (ECAM base address / 1M) %
> 256
>

For OS's there is indeed only bus0 exposed, but I plan to make it
tunable, so that to use entire range (e.g. for FreeBSD). In EDK2 there
is full coverage. FYI, in the platform I plan to submit after this
patchset there 7 RC's: 1 with 255 and 6 with 15 busses (the last 1 MB
in each case is used for IO space).

Best regards,
Marcin

>
> > >
> > > > Signed-off-by: Marcin Wojtas <mw@semihalf.com>
> > > > ---
> > > >  Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciHostBridgeLib/PciHostBridgeLibConstructor.c | 1 -
> > > >  1 file changed, 1 deletion(-)
> > > >
> > > > diff --git a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciHostBridgeLib/PciHostBridgeLibConstructor.c b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciHostBridgeLib/PciHostBridgeLibConstructor.c
> > > > index 067e57a2dc..87e57aeae3 100644
> > > > --- a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciHostBridgeLib/PciHostBridgeLibConstructor.c
> > > > +++ b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciHostBridgeLib/PciHostBridgeLibConstructor.c
> > > > @@ -219,7 +219,6 @@ Armada7k8kPciHostBridgeLibConstructor (
> > > >      PcieController = &(BoardPcieDescription->PcieControllers[Index]);
> > > >
> > > >      ASSERT (PcieController->PcieBusMin == 0);
> > > > -    ASSERT (PcieController->ConfigSpaceAddress % SIZE_256MB == 0);
> > > >
> > > >      if (PcieController->HaveResetGpio == TRUE) {
> > > >        /* Reset PCIE slot */
> > > > --
> > > > 2.29.0
> > > >

[edk2-platforms PATCH 4/6] Marvell: Armada7k8k/OcteonTx: Add multiple PCIE ports support

[Marcin Wojtas]

From: Kamil Koczurek <kek@semihalf.com>

In order to support more than one PCIE port, PciHostBridgeLib must
generate appropriate device paths according to the board description
and assign correct segment numbers instead of a hard-coded 0.

Additionally, PciSegmentLib has to operate on a proper
config spaces base address (depending on the segment number).
Add the library constructor routine and obtain the necessary
data from the Marvell board description protocol.

Remove unused PCIE-related PCD's.

Signed-off-by: Marcin Wojtas <mw@semihalf.com>
---
 Platform/Marvell/Cn913xDb/Cn9130DbA.dsc.inc                                      |  4 --
 Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc                                    |  4 --
 Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciSegmentLib/PciSegmentLib.inf     | 11 ++--
 Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciHostBridgeLib/PciHostBridgeLib.c | 15 +++--
 Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciSegmentLib/PciSegmentLib.c       | 69 +++++++++++++++++++-
 5 files changed, 86 insertions(+), 17 deletions(-)

diff --git a/Platform/Marvell/Cn913xDb/Cn9130DbA.dsc.inc b/Platform/Marvell/Cn913xDb/Cn9130DbA.dsc.inc
index 41d9cb9247..e4d4c8e073 100644
--- a/Platform/Marvell/Cn913xDb/Cn9130DbA.dsc.inc
+++ b/Platform/Marvell/Cn913xDb/Cn9130DbA.dsc.inc
@@ -93,10 +93,6 @@
   gMarvellTokenSpaceGuid.PcdPciEAhci|{ 0x1 }
   gMarvellTokenSpaceGuid.PcdPciESdhci|{ 0x1, 0x1 }
 
-  # PCIE
-  gArmTokenSpaceGuid.PcdPciIoTranslation|0xDFF00000
-  gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xD0000000
-
   # RTC
   gMarvellTokenSpaceGuid.PcdRtcBaseAddress|0xF2284000
 
diff --git a/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc b/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc
index b1aa0ae4d0..25f3fc8dd8 100644
--- a/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc
+++ b/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc
@@ -396,10 +396,6 @@
   gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize|0x00010000
   gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize|0x00010000
 
-  # PCIE
-  gArmTokenSpaceGuid.PcdPciIoTranslation|0xEFF00000
-  gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xE0000000
-
 !if $(CAPSULE_ENABLE)
 [PcdsDynamicExDefault.common.DEFAULT]
   gEfiSignedCapsulePkgTokenSpaceGuid.PcdEdkiiSystemFirmwareImageDescriptor|{0x0}|VOID*|0x100
diff --git a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciSegmentLib/PciSegmentLib.inf b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciSegmentLib/PciSegmentLib.inf
index f5f1b8409b..d3876791e9 100644
--- a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciSegmentLib/PciSegmentLib.inf
+++ b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciSegmentLib/PciSegmentLib.inf
@@ -16,18 +16,21 @@
   MODULE_TYPE                    = BASE
   VERSION_STRING                 = 1.0
   LIBRARY_CLASS                  = PciSegmentLib
+  CONSTRUCTOR                    = Armada7k8kPciSegmentLibConstructor
 
 [Sources]
   PciSegmentLib.c
 
 [Packages]
+  EmbeddedPkg/EmbeddedPkg.dec
+  MdeModulePkg/MdeModulePkg.dec
   MdePkg/MdePkg.dec
   Silicon/Marvell/Marvell.dec
 
 [LibraryClasses]
+  ArmadaBoardDescLib
+  ArmadaSoCDescLib
   BaseLib
-  DebugLib
-  IoLib
 
-[Pcd]
-  gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress
+[Protocols]
+  gMarvellBoardDescProtocolGuid
diff --git a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciHostBridgeLib/PciHostBridgeLib.c b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciHostBridgeLib/PciHostBridgeLib.c
index 52fa5a4c1a..ad52062d73 100644
--- a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciHostBridgeLib/PciHostBridgeLib.c
+++ b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciHostBridgeLib/PciHostBridgeLib.c
@@ -9,6 +9,7 @@
 **/
 #include <PiDxe.h>
 
+#include <Library/BaseMemoryLib.h>
 #include <Library/DebugLib.h>
 #include <Library/DevicePathLib.h>
 #include <Library/MemoryAllocationLib.h>
@@ -27,7 +28,7 @@ typedef struct {
 } EFI_PCI_ROOT_BRIDGE_DEVICE_PATH;
 #pragma pack ()
 
-STATIC EFI_PCI_ROOT_BRIDGE_DEVICE_PATH mEfiPciRootBridgeDevicePath = {
+STATIC CONST EFI_PCI_ROOT_BRIDGE_DEVICE_PATH mEfiPciRootBridgeDevicePathTemplate = {
   {
     {
       ACPI_DEVICE_PATH,
@@ -38,7 +39,7 @@ STATIC EFI_PCI_ROOT_BRIDGE_DEVICE_PATH mEfiPciRootBridgeDevicePath = {
       }
     },
     EISA_PNP_ID (0x0A08), // PCI Express
-    0
+    0 // AcpiDevicePath.UID
   },
 
   {
@@ -74,6 +75,7 @@ PciHostBridgeGetRootBridges (
 {
   MV_BOARD_PCIE_DESCRIPTION CONST *BoardPcieDescription;
   MARVELL_BOARD_DESC_PROTOCOL     *BoardDescriptionProtocol;
+  EFI_PCI_ROOT_BRIDGE_DEVICE_PATH *EfiPciRootBridgeDevicePath;
   MV_PCIE_CONTROLLER CONST        *PcieController;
   PCI_ROOT_BRIDGE                 *PciRootBridges;
   PCI_ROOT_BRIDGE                 *RootBridge;
@@ -119,10 +121,15 @@ PciHostBridgeGetRootBridges (
 
   /* Fill information of all root bridge instances */
   for (Index = 0; Index < *Count; Index++, RootBridge++) {
+    EfiPciRootBridgeDevicePath = AllocateCopyPool (
+                                   sizeof (EFI_PCI_ROOT_BRIDGE_DEVICE_PATH),
+                                   &mEfiPciRootBridgeDevicePathTemplate
+                                   );
+    EfiPciRootBridgeDevicePath->AcpiDevicePath.UID = Index;
 
     PcieController = &(BoardPcieDescription->PcieControllers[Index]);
 
-    RootBridge->Segment   = 0;
+    RootBridge->Segment   = Index;
     RootBridge->Supports  = 0;
     RootBridge->Attributes  = RootBridge->Supports;
 
@@ -168,7 +175,7 @@ PciHostBridgeGetRootBridges (
 
     RootBridge->NoExtendedConfigSpace = FALSE;
 
-    RootBridge->DevicePath = (EFI_DEVICE_PATH_PROTOCOL *)&mEfiPciRootBridgeDevicePath;
+    RootBridge->DevicePath = (EFI_DEVICE_PATH_PROTOCOL *)EfiPciRootBridgeDevicePath;
   }
 
   return PciRootBridges;
diff --git a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciSegmentLib/PciSegmentLib.c b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciSegmentLib/PciSegmentLib.c
index 283190959e..02ceb17825 100644
--- a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciSegmentLib/PciSegmentLib.c
+++ b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciSegmentLib/PciSegmentLib.c
@@ -9,12 +9,20 @@
 
 **/
 
+#include <Uefi.h>
 #include <Base.h>
 
 #include <Library/BaseLib.h>
 #include <Library/DebugLib.h>
 #include <Library/IoLib.h>
+#include <Library/MemoryAllocationLib.h>
 #include <Library/PciSegmentLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+
+#include <Protocol/BoardDesc.h>
+
+UINT64 *mConfigSpaceAddresses;
+UINTN mPcieControllerCount;
 
 typedef enum {
   PciCfgWidthUint8      = 0,
@@ -34,6 +42,15 @@ typedef enum {
 #define ASSERT_INVALID_PCI_SEGMENT_ADDRESS(A,M) \
   ASSERT (((A) & (0xffff0000f0000000ULL | (M))) == 0)
 
+/**
+  Extract segment number from PCI Segment address
+
+  @param  A The address to process.
+
+**/
+#define SEGMENT_INDEX(A) \
+  (((A) & 0x0000ffff00000000) >> 32)
+
 /**
   Internal worker function to obtain config space base address.
 
@@ -49,7 +66,9 @@ PciSegmentLibGetConfigBase (
   IN  UINT64      Address
   )
 {
-  return PcdGet64 (PcdPciExpressBaseAddress);
+  ASSERT (SEGMENT_INDEX (Address) < mPcieControllerCount);
+
+  return mConfigSpaceAddresses[SEGMENT_INDEX (Address)];
 }
 
 /**
@@ -1388,3 +1407,51 @@ PciSegmentWriteBuffer (
 
   return ReturnValue;
 }
+
+/**
+  Obtain base addresses of PCIe configuration spaces.
+
+  @retval EFI_SUCEESS       Routine executed properly.
+  @retval Other             Return error status.
+
+**/
+EFI_STATUS
+EFIAPI
+Armada7k8kPciSegmentLibConstructor (
+  VOID
+  )
+{
+  CONST MV_BOARD_PCIE_DESCRIPTION *PcieDesc;
+  MARVELL_BOARD_DESC_PROTOCOL *Proto;
+  EFI_STATUS Status;
+  UINTN Index;
+
+  Status = gBS->LocateProtocol (
+                  &gMarvellBoardDescProtocolGuid,
+                  NULL,
+                  (VOID **)&Proto
+                  );
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+
+  Status = Proto->PcieDescriptionGet (Proto, &PcieDesc);
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+
+  mConfigSpaceAddresses = AllocateZeroPool (
+                            PcieDesc->PcieControllerCount * sizeof (UINT64)
+                          );
+  if (mConfigSpaceAddresses == NULL) {
+    return EFI_OUT_OF_RESOURCES;
+  }
+
+  for (Index = 0; Index < PcieDesc->PcieControllerCount; Index++) {
+    mConfigSpaceAddresses[Index] = PcieDesc->PcieControllers[Index].ConfigSpaceAddress;
+  }
+
+  mPcieControllerCount = PcieDesc->PcieControllerCount;
+
+  return EFI_SUCCESS;
+}
-- 
2.29.0

[edk2-platforms PATCH 5/6] Marvell: Armada7k8k/OcteonTX: Enable additional board configuration

[Marcin Wojtas]

Introduce new board description library extension that allows
to execute custom initialization sequence. Add stubs for all
existing platforms.

Signed-off-by: Marcin Wojtas <mw@semihalf.com>
---
 Silicon/Marvell/Armada7k8k/Drivers/PlatInitDxe/PlatInitDxe.inf                              |  1 +
 Silicon/Marvell/Include/Library/ArmadaBoardDescLib.h                                        |  9 +++++++++
 Platform/Marvell/Armada70x0Db/Armada70x0DbBoardDescLib/Armada70x0DbBoardDescLib.c           | 11 +++++++++++
 Platform/Marvell/Armada80x0Db/Armada80x0DbBoardDescLib/Armada80x0DbBoardDescLib.c           | 11 +++++++++++
 Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9130DbABoardDescLib.c                       | 11 +++++++++++
 Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9132DbABoardDescLib.c                       | 11 +++++++++++
 Platform/SolidRun/Armada80x0McBin/Armada80x0McBinBoardDescLib/Armada80x0McBinBoardDescLib.c | 11 +++++++++++
 Silicon/Marvell/Armada7k8k/Drivers/PlatInitDxe/PlatInitDxe.c                                |  2 ++
 8 files changed, 67 insertions(+)

diff --git a/Silicon/Marvell/Armada7k8k/Drivers/PlatInitDxe/PlatInitDxe.inf b/Silicon/Marvell/Armada7k8k/Drivers/PlatInitDxe/PlatInitDxe.inf
index b63e9b6325..398baebcf5 100644
--- a/Silicon/Marvell/Armada7k8k/Drivers/PlatInitDxe/PlatInitDxe.inf
+++ b/Silicon/Marvell/Armada7k8k/Drivers/PlatInitDxe/PlatInitDxe.inf
@@ -26,6 +26,7 @@
   Silicon/Marvell/Marvell.dec
 
 [LibraryClasses]
+  ArmadaBoardDescLib
   ArmadaIcuLib
   ArmSmcLib
   ComPhyLib
diff --git a/Silicon/Marvell/Include/Library/ArmadaBoardDescLib.h b/Silicon/Marvell/Include/Library/ArmadaBoardDescLib.h
index 80c55eb3a7..6dc296371d 100644
--- a/Silicon/Marvell/Include/Library/ArmadaBoardDescLib.h
+++ b/Silicon/Marvell/Include/Library/ArmadaBoardDescLib.h
@@ -11,6 +11,15 @@
 #include <Library/ArmadaSoCDescLib.h>
 #include <Library/MvGpioLib.h>
 
+//
+// General purpose routine for per-board initalization
+//
+EFI_STATUS
+EFIAPI
+ArmadaBoardInit (
+  VOID
+  );
+
 //
 // COMPHY controllers per-board description
 //
diff --git a/Platform/Marvell/Armada70x0Db/Armada70x0DbBoardDescLib/Armada70x0DbBoardDescLib.c b/Platform/Marvell/Armada70x0Db/Armada70x0DbBoardDescLib/Armada70x0DbBoardDescLib.c
index b0b6855bbb..33e40d0bd9 100644
--- a/Platform/Marvell/Armada70x0Db/Armada70x0DbBoardDescLib/Armada70x0DbBoardDescLib.c
+++ b/Platform/Marvell/Armada70x0Db/Armada70x0DbBoardDescLib/Armada70x0DbBoardDescLib.c
@@ -16,6 +16,17 @@
 #include <Library/MvGpioLib.h>
 #include <Library/UefiBootServicesTableLib.h>
 
+//
+// General purpose routine for per-board initalization
+//
+EFI_STATUS
+ArmadaBoardInit (
+  VOID
+  )
+{
+  return EFI_SUCCESS;
+}
+
 //
 // GPIO Expander
 //
diff --git a/Platform/Marvell/Armada80x0Db/Armada80x0DbBoardDescLib/Armada80x0DbBoardDescLib.c b/Platform/Marvell/Armada80x0Db/Armada80x0DbBoardDescLib/Armada80x0DbBoardDescLib.c
index 2b119fa2a7..e4ee2e04ae 100644
--- a/Platform/Marvell/Armada80x0Db/Armada80x0DbBoardDescLib/Armada80x0DbBoardDescLib.c
+++ b/Platform/Marvell/Armada80x0Db/Armada80x0DbBoardDescLib/Armada80x0DbBoardDescLib.c
@@ -16,6 +16,17 @@
 #include <Library/MvGpioLib.h>
 #include <Library/UefiBootServicesTableLib.h>
 
+//
+// General purpose routine for per-board initalization
+//
+EFI_STATUS
+ArmadaBoardInit (
+  VOID
+  )
+{
+  return EFI_SUCCESS;
+}
+
 //
 // GPIO Expanders
 //
diff --git a/Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9130DbABoardDescLib.c b/Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9130DbABoardDescLib.c
index 2755600f53..d53c7086a1 100644
--- a/Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9130DbABoardDescLib.c
+++ b/Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9130DbABoardDescLib.c
@@ -16,6 +16,17 @@
 #include <Library/MvGpioLib.h>
 #include <Library/UefiBootServicesTableLib.h>
 
+//
+// General purpose routine for per-board initalization
+//
+EFI_STATUS
+ArmadaBoardInit (
+  VOID
+  )
+{
+  return EFI_SUCCESS;
+}
+
 //
 // GPIO Expander
 //
diff --git a/Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9132DbABoardDescLib.c b/Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9132DbABoardDescLib.c
index d2846dde30..920c7436c2 100644
--- a/Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9132DbABoardDescLib.c
+++ b/Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9132DbABoardDescLib.c
@@ -16,6 +16,17 @@
 #include <Library/MvGpioLib.h>
 #include <Library/UefiBootServicesTableLib.h>
 
+//
+// General purpose routine for per-board initalization
+//
+EFI_STATUS
+ArmadaBoardInit (
+  VOID
+  )
+{
+  return EFI_SUCCESS;
+}
+
 //
 // GPIO Expander
 //
diff --git a/Platform/SolidRun/Armada80x0McBin/Armada80x0McBinBoardDescLib/Armada80x0McBinBoardDescLib.c b/Platform/SolidRun/Armada80x0McBin/Armada80x0McBinBoardDescLib/Armada80x0McBinBoardDescLib.c
index ebe7386df1..b11195c5a1 100644
--- a/Platform/SolidRun/Armada80x0McBin/Armada80x0McBinBoardDescLib/Armada80x0McBinBoardDescLib.c
+++ b/Platform/SolidRun/Armada80x0McBin/Armada80x0McBinBoardDescLib/Armada80x0McBinBoardDescLib.c
@@ -15,6 +15,17 @@
 #include <Library/MemoryAllocationLib.h>
 #include <Library/UefiBootServicesTableLib.h>
 
+//
+// General purpose routine for per-board initalization
+//
+EFI_STATUS
+ArmadaBoardInit (
+  VOID
+  )
+{
+  return EFI_SUCCESS;
+}
+
 //
 // GPIO Expander
 //
diff --git a/Silicon/Marvell/Armada7k8k/Drivers/PlatInitDxe/PlatInitDxe.c b/Silicon/Marvell/Armada7k8k/Drivers/PlatInitDxe/PlatInitDxe.c
index 927abb9400..78ad1c8a7a 100644
--- a/Silicon/Marvell/Armada7k8k/Drivers/PlatInitDxe/PlatInitDxe.c
+++ b/Silicon/Marvell/Armada7k8k/Drivers/PlatInitDxe/PlatInitDxe.c
@@ -110,6 +110,8 @@ ArmadaPlatInitDxeEntryPoint (
   UtmiPhyInit ();
   MppInitialize ();
   ArmadaIcuInitialize ();
+  Status = ArmadaBoardInit ();
+  ASSERT_EFI_ERROR (Status);
 
   /*
    * Enable EL3 PMU interrupt handler and
-- 
2.29.0

[edk2-platforms PATCH 6/6] Marvell: IcuLib: Rework default interrupt map

[Marcin Wojtas]

The ICU to GIC interrupt mapping was fixed to support
the maximum of two CP11x south bridge units. Rework
the default map to use only the interrupts wired
to controllers supported in the ACPI tables.
Thanks to above all necessary IRQs from the CN913x
SoCs (maximum 3 CP11x) can be mapped and passed to the OS.

Signed-off-by: Marcin Wojtas <mw@semihalf.com>
---
 Silicon/Marvell/Armada7k8k/AcpiTables/IcuInterrupts.h   |  48 ++++----
 Silicon/Marvell/Library/IcuLib/IcuLib.h                 |   6 +-
 Silicon/Marvell/OcteonTx/AcpiTables/T91/IcuInterrupts.h |  61 +++++++----
 Silicon/Marvell/Library/IcuLib/IcuLib.c                 | 115 ++++++--------------
 4 files changed, 95 insertions(+), 135 deletions(-)

diff --git a/Silicon/Marvell/Armada7k8k/AcpiTables/IcuInterrupts.h b/Silicon/Marvell/Armada7k8k/AcpiTables/IcuInterrupts.h
index b106790913..a2b7b00b0d 100644
--- a/Silicon/Marvell/Armada7k8k/AcpiTables/IcuInterrupts.h
+++ b/Silicon/Marvell/Armada7k8k/AcpiTables/IcuInterrupts.h
@@ -11,28 +11,28 @@
 
 **/
 
-#define CP_GIC_SPI_CP0_PCI0            64
-#define CP_GIC_SPI_CP0_PCI1            65
-#define CP_GIC_SPI_CP0_PCI2            66
-#define CP_GIC_SPI_CP0_SDMMC           67
-#define CP_GIC_SPI_PP2_CP0_PORT0       69, 72, 75, 78, 81, 127
-#define CP_GIC_SPI_PP2_CP0_PORT1       70, 73, 76, 79, 82, 126
-#define CP_GIC_SPI_PP2_CP0_PORT2       71, 74, 77, 80, 83, 125
-#define CP_GIC_SPI_CP0_EIP_RNG0        105
-#define CP_GIC_SPI_CP0_USB_H1          112
-#define CP_GIC_SPI_CP0_USB_H0          113
-#define CP_GIC_SPI_CP0_SATA_H0         114
-#define CP_GIC_SPI_CP0_UART0           121
-#define CP_GIC_SPI_CP0_UART1           122
+#define CP_GIC_SPI_CP0_SDMMC           64
+#define CP_GIC_SPI_PP2_CP0_PORT0       65, 68, 71, 74, 77, 90
+#define CP_GIC_SPI_PP2_CP0_PORT1       66, 69, 72, 75, 78, 89
+#define CP_GIC_SPI_PP2_CP0_PORT2       67, 70, 73, 76, 79, 88
+#define CP_GIC_SPI_CP0_EIP_RNG0        80
+#define CP_GIC_SPI_CP0_USB_H1          81
+#define CP_GIC_SPI_CP0_USB_H0          82
+#define CP_GIC_SPI_CP0_SATA_H0         83
+#define CP_GIC_SPI_CP0_UART0           84
+#define CP_GIC_SPI_CP0_UART1           85
+#define CP_GIC_SPI_CP0_UART2           86
+#define CP_GIC_SPI_CP0_UART3           87
 
-#define CP_GIC_SPI_CP1_PCI0            288
-#define CP_GIC_SPI_CP1_PCI1            289
-#define CP_GIC_SPI_CP1_PCI2            290
-#define CP_GIC_SPI_CP1_SDMMC           291
-#define CP_GIC_SPI_PP2_CP1_PORT0       293, 296, 299, 302, 305, 351
-#define CP_GIC_SPI_PP2_CP1_PORT1       294, 297, 300, 303, 306, 350
-#define CP_GIC_SPI_PP2_CP1_PORT2       295, 298, 301, 304, 307, 349
-#define CP_GIC_SPI_CP1_EIP_RNG0        329
-#define CP_GIC_SPI_CP1_USB_H1          336
-#define CP_GIC_SPI_CP1_USB_H0          337
-#define CP_GIC_SPI_CP1_SATA_H0         338
+#define CP_GIC_SPI_CP1_SDMMC           96
+#define CP_GIC_SPI_PP2_CP1_PORT0       97, 100, 103, 106, 109, 122
+#define CP_GIC_SPI_PP2_CP1_PORT1       98, 101, 104, 107, 110, 121
+#define CP_GIC_SPI_PP2_CP1_PORT2       99, 102, 105, 108, 111, 120
+#define CP_GIC_SPI_CP1_EIP_RNG0        112
+#define CP_GIC_SPI_CP1_USB_H1          113
+#define CP_GIC_SPI_CP1_USB_H0          114
+#define CP_GIC_SPI_CP1_SATA_H0         115
+#define CP_GIC_SPI_CP1_UART0           116
+#define CP_GIC_SPI_CP1_UART1           117
+#define CP_GIC_SPI_CP1_UART2           118
+#define CP_GIC_SPI_CP1_UART3           119
diff --git a/Silicon/Marvell/Library/IcuLib/IcuLib.h b/Silicon/Marvell/Library/IcuLib/IcuLib.h
index 22027f6bc0..cc1fc5754b 100644
--- a/Silicon/Marvell/Library/IcuLib/IcuLib.h
+++ b/Silicon/Marvell/Library/IcuLib/IcuLib.h
@@ -22,7 +22,7 @@
 #include <Library/PcdLib.h>
 #include <Library/UefiBootServicesTableLib.h>
 
-#define ICU_REG_BASE(Cp)        (ArmadaSoCDescCpBaseGet (CpIndex) + 0x1E0000)
+#define ICU_REG_BASE(CpIndex)   (ArmadaSoCDescCpBaseGet (CpIndex) + 0x1E0000)
 
 #define ICU_GROUP_REGISTER_BASE_OFFSET    0x10
 #define ICU_SET_SPI_AL(x)       (0x10 + (ICU_GROUP_REGISTER_BASE_OFFSET * x))
@@ -35,7 +35,7 @@
 #define ICU_IS_EDGE_OFFSET       28
 #define ICU_GROUP_OFFSET         29
 
-#define ICU_MAX_SUPPORTED_UNITS  2
-#define ICU_MAX_IRQS_PER_CP      64
+#define ICU_MAX_SUPPORTED_UNITS  3
+#define ICU_SPI_OFFSET(CpIndex)  ((CpIndex) * 32)
 
 #define MAX_ICU_IRQS             207
diff --git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/IcuInterrupts.h b/Silicon/Marvell/OcteonTx/AcpiTables/T91/IcuInterrupts.h
index 83006ebd8a..fea820f9ed 100644
--- a/Silicon/Marvell/OcteonTx/AcpiTables/T91/IcuInterrupts.h
+++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/IcuInterrupts.h
@@ -11,28 +11,41 @@
 
 **/
 
-#define CP_GIC_SPI_CP0_PCI0            64
-#define CP_GIC_SPI_CP0_PCI1            65
-#define CP_GIC_SPI_CP0_PCI2            66
-#define CP_GIC_SPI_CP0_SDMMC           67
-#define CP_GIC_SPI_PP2_CP0_PORT0       69, 72, 75, 78, 81, 127
-#define CP_GIC_SPI_PP2_CP0_PORT1       70, 73, 76, 79, 82, 126
-#define CP_GIC_SPI_PP2_CP0_PORT2       71, 74, 77, 80, 83, 125
-#define CP_GIC_SPI_CP0_EIP_RNG0        105
-#define CP_GIC_SPI_CP0_USB_H1          112
-#define CP_GIC_SPI_CP0_USB_H0          113
-#define CP_GIC_SPI_CP0_SATA_H0         114
-#define CP_GIC_SPI_CP0_UART0           121
-#define CP_GIC_SPI_CP0_UART1           122
+#define CP_GIC_SPI_CP0_SDMMC           64
+#define CP_GIC_SPI_PP2_CP0_PORT0       65, 68, 71, 74, 77, 90
+#define CP_GIC_SPI_PP2_CP0_PORT1       66, 69, 72, 75, 78, 89
+#define CP_GIC_SPI_PP2_CP0_PORT2       67, 70, 73, 76, 79, 88
+#define CP_GIC_SPI_CP0_EIP_RNG0        80
+#define CP_GIC_SPI_CP0_USB_H1          81
+#define CP_GIC_SPI_CP0_USB_H0          82
+#define CP_GIC_SPI_CP0_SATA_H0         83
+#define CP_GIC_SPI_CP0_UART0           84
+#define CP_GIC_SPI_CP0_UART1           85
+#define CP_GIC_SPI_CP0_UART2           86
+#define CP_GIC_SPI_CP0_UART3           87
 
-#define CP_GIC_SPI_CP1_PCI0            288
-#define CP_GIC_SPI_CP1_PCI1            289
-#define CP_GIC_SPI_CP1_PCI2            290
-#define CP_GIC_SPI_CP1_SDMMC           291
-#define CP_GIC_SPI_PP2_CP1_PORT0       293, 296, 299, 302, 305, 351
-#define CP_GIC_SPI_PP2_CP1_PORT1       294, 297, 300, 303, 306, 350
-#define CP_GIC_SPI_PP2_CP1_PORT2       295, 298, 301, 304, 307, 349
-#define CP_GIC_SPI_CP1_EIP_RNG0        329
-#define CP_GIC_SPI_CP1_USB_H1          336
-#define CP_GIC_SPI_CP1_USB_H0          337
-#define CP_GIC_SPI_CP1_SATA_H0         338
+#define CP_GIC_SPI_CP1_SDMMC           96
+#define CP_GIC_SPI_PP2_CP1_PORT0       97, 100, 103, 106, 109, 122
+#define CP_GIC_SPI_PP2_CP1_PORT1       98, 101, 104, 107, 110, 121
+#define CP_GIC_SPI_PP2_CP1_PORT2       99, 102, 105, 108, 111, 120
+#define CP_GIC_SPI_CP1_EIP_RNG0        112
+#define CP_GIC_SPI_CP1_USB_H1          113
+#define CP_GIC_SPI_CP1_USB_H0          114
+#define CP_GIC_SPI_CP1_SATA_H0         115
+#define CP_GIC_SPI_CP1_UART0           116
+#define CP_GIC_SPI_CP1_UART1           117
+#define CP_GIC_SPI_CP1_UART2           118
+#define CP_GIC_SPI_CP1_UART3           119
+
+#define CP_GIC_SPI_CP2_SDMMC           288
+#define CP_GIC_SPI_PP2_CP2_PORT0       289, 292, 295, 298, 301, 314
+#define CP_GIC_SPI_PP2_CP2_PORT1       290, 293, 296, 299, 302, 313
+#define CP_GIC_SPI_PP2_CP2_PORT2       291, 294, 297, 300, 303, 312
+#define CP_GIC_SPI_CP2_EIP_RNG0        304
+#define CP_GIC_SPI_CP2_USB_H1          305
+#define CP_GIC_SPI_CP2_USB_H0          306
+#define CP_GIC_SPI_CP2_SATA_H0         307
+#define CP_GIC_SPI_CP2_UART0           308
+#define CP_GIC_SPI_CP2_UART1           309
+#define CP_GIC_SPI_CP2_UART2           310
+#define CP_GIC_SPI_CP2_UART3           311
diff --git a/Silicon/Marvell/Library/IcuLib/IcuLib.c b/Silicon/Marvell/Library/IcuLib/IcuLib.c
index 4d9f17445e..e4cb993c7e 100644
--- a/Silicon/Marvell/Library/IcuLib/IcuLib.c
+++ b/Silicon/Marvell/Library/IcuLib/IcuLib.c
@@ -16,73 +16,34 @@
 STATIC EFI_EVENT mEfiExitBootServicesEvent;
 
 STATIC CONST ICU_IRQ IrqMapNonSecure[] = {
-  {22,   0, IcuIrqTypeLevel}, /* PCIx4 INT A interrupt */
-  {23,   1, IcuIrqTypeLevel}, /* PCIx1 INT A interrupt */
-  {24,   2, IcuIrqTypeLevel}, /* PCIx1 INT A interrupt */
-  {27,   3, IcuIrqTypeLevel}, /* SD/MMC */
-  {33,   4, IcuIrqTypeLevel}, /* PPv2 DBG AXI monitor */
-  {34,   4, IcuIrqTypeLevel}, /* HB1      AXI monitor */
-  {35,   4, IcuIrqTypeLevel}, /* AP       AXI monitor */
-  {36,   4, IcuIrqTypeLevel}, /* PPv2     AXI monitor */
-  {39,   5, IcuIrqTypeLevel}, /* PPv2 Irq */
-  {40,   6, IcuIrqTypeLevel}, /* PPv2 Irq */
-  {41,   7, IcuIrqTypeLevel}, /* PPv2 Irq */
-  {43,   8, IcuIrqTypeLevel}, /* PPv2 Irq */
-  {44,   9, IcuIrqTypeLevel}, /* PPv2 Irq */
-  {45,  10, IcuIrqTypeLevel}, /* PPv2 Irq */
-  {47,  11, IcuIrqTypeLevel}, /* PPv2 Irq */
-  {48,  12, IcuIrqTypeLevel}, /* PPv2 Irq */
-  {49,  13, IcuIrqTypeLevel}, /* PPv2 Irq */
-  {51,  14, IcuIrqTypeLevel}, /* PPv2 Irq */
-  {52,  15, IcuIrqTypeLevel}, /* PPv2 Irq */
-  {53,  16, IcuIrqTypeLevel}, /* PPv2 Irq */
-  {55,  17, IcuIrqTypeLevel}, /* PPv2 Irq */
-  {56,  18, IcuIrqTypeLevel}, /* PPv2 Irq */
-  {57,  19, IcuIrqTypeLevel}, /* PPv2 Irq */
-  {59,  20, IcuIrqTypeLevel}, /* PPv2 Irq */
-  {60,  21, IcuIrqTypeLevel}, /* PPv2 Irq */
-  {61,  22, IcuIrqTypeLevel}, /* PPv2 Irq */
-  {63,  23, IcuIrqTypeLevel}, /* PPv2 Irq */
-  {64,  24, IcuIrqTypeLevel}, /* PPv2 Irq */
-  {65,  25, IcuIrqTypeLevel}, /* PPv2 Irq */
-  {67,  26, IcuIrqTypeLevel}, /* PPv2 Irq */
-  {68,  27, IcuIrqTypeLevel}, /* PPv2 Irq */
-  {69,  28, IcuIrqTypeLevel}, /* PPv2 Irq */
-  {71,  29, IcuIrqTypeLevel}, /* PPv2 Irq */
-  {72,  30, IcuIrqTypeLevel}, /* PPv2 Irq */
-  {73,  31, IcuIrqTypeLevel}, /* PPv2 Irq */
-  {78,  32, IcuIrqTypeLevel}, /* MG Irq */
-  {79,  33, IcuIrqTypeLevel}, /* GPIO 56-63 */
-  {80,  34, IcuIrqTypeLevel}, /* GPIO 48-55 */
-  {81,  35, IcuIrqTypeLevel}, /* GPIO 40-47 */
-  {82,  36, IcuIrqTypeLevel}, /* GPIO 32-39 */
-  {83,  37, IcuIrqTypeLevel}, /* GPIO 24-31 */
-  {84,  38, IcuIrqTypeLevel}, /* GPIO 16-23 */
-  {85,  39, IcuIrqTypeLevel}, /* GPIO  8-15 */
-  {86,  40, IcuIrqTypeLevel}, /* GPIO  0-7  */
-  {88,  41, IcuIrqTypeLevel}, /* EIP-197 ring-0 */
-  {89,  42, IcuIrqTypeLevel}, /* EIP-197 ring-1 */
-  {90,  43, IcuIrqTypeLevel}, /* EIP-197 ring-2 */
-  {91,  44, IcuIrqTypeLevel}, /* EIP-197 ring-3 */
-  {92,  45, IcuIrqTypeLevel}, /* EIP-197 int */
-  {95,  46, IcuIrqTypeLevel}, /* EIP-150 Irq */
-  {102, 47, IcuIrqTypeLevel}, /* USB3 Device Irq */
-  {105, 48, IcuIrqTypeLevel}, /* USB3 Host-1 Irq */
-  {106, 49, IcuIrqTypeLevel}, /* USB3 Host-0 Irq */
-  {107, 50, IcuIrqTypeLevel}, /* SATA Host-1 Irq */
-  {109, 50, IcuIrqTypeLevel}, /* SATA Host-0 Irq */
-  {115, 52, IcuIrqTypeLevel}, /* NAND Irq */
-  {117, 53, IcuIrqTypeLevel}, /* SPI-1 Irq */
-  {118, 54, IcuIrqTypeLevel}, /* SPI-0 Irq */
-  {120, 55, IcuIrqTypeLevel}, /* I2C 0 Irq */
-  {121, 56, IcuIrqTypeLevel}, /* I2C 1 Irq */
-  {122, 57, IcuIrqTypeLevel}, /* UART 0 Irq */
-  {123, 58, IcuIrqTypeLevel}, /* UART 1 Irq */
-  {124, 59, IcuIrqTypeLevel}, /* UART 2 Irq */
-  {125, 60, IcuIrqTypeLevel}, /* UART 3 Irq */
-  {127, 61, IcuIrqTypeLevel}, /* GOP-3 Irq */
-  {128, 62, IcuIrqTypeLevel}, /* GOP-2 Irq */
-  {129, 63, IcuIrqTypeLevel}, /* GOP-0 Irq */
+  {27,   0, IcuIrqTypeLevel}, /* SD/MMC */
+  {39,   1, IcuIrqTypeLevel}, /* PPv2 Irq */
+  {40,   2, IcuIrqTypeLevel}, /* PPv2 Irq */
+  {41,   3, IcuIrqTypeLevel}, /* PPv2 Irq */
+  {43,   4, IcuIrqTypeLevel}, /* PPv2 Irq */
+  {44,   5, IcuIrqTypeLevel}, /* PPv2 Irq */
+  {45,   6, IcuIrqTypeLevel}, /* PPv2 Irq */
+  {47,   7, IcuIrqTypeLevel}, /* PPv2 Irq */
+  {48,   8, IcuIrqTypeLevel}, /* PPv2 Irq */
+  {49,   9, IcuIrqTypeLevel}, /* PPv2 Irq */
+  {51,  10, IcuIrqTypeLevel}, /* PPv2 Irq */
+  {52,  11, IcuIrqTypeLevel}, /* PPv2 Irq */
+  {53,  12, IcuIrqTypeLevel}, /* PPv2 Irq */
+  {55,  13, IcuIrqTypeLevel}, /* PPv2 Irq */
+  {56,  14, IcuIrqTypeLevel}, /* PPv2 Irq */
+  {57,  15, IcuIrqTypeLevel}, /* PPv2 Irq */
+  {88,  16, IcuIrqTypeLevel}, /* EIP-197 ring-0 */
+  {105, 17, IcuIrqTypeLevel}, /* USB3 Host-1 Irq */
+  {106, 18, IcuIrqTypeLevel}, /* USB3 Host-0 Irq */
+  {107, 19, IcuIrqTypeLevel}, /* SATA Host-1 Irq */
+  {109, 19, IcuIrqTypeLevel}, /* SATA Host-0 Irq */
+  {122, 20, IcuIrqTypeLevel}, /* UART 0 Irq */
+  {123, 21, IcuIrqTypeLevel}, /* UART 1 Irq */
+  {124, 22, IcuIrqTypeLevel}, /* UART 2 Irq */
+  {125, 23, IcuIrqTypeLevel}, /* UART 3 Irq */
+  {127, 24, IcuIrqTypeLevel}, /* GOP-3 Irq */
+  {128, 25, IcuIrqTypeLevel}, /* GOP-2 Irq */
+  {129, 26, IcuIrqTypeLevel}, /* GOP-0 Irq */
 };
 
 /*
@@ -177,7 +138,7 @@ IcuConfigure (
   /* Get the base of the GIC SPI ID in the MSI message */
   SpiBase = IcuDesc->IcuSpiBase;
   /* Get multiple CP110 instances SPI ID shift */
-  SpiOffset = CpIndex * ICU_MAX_IRQS_PER_CP;
+  SpiOffset = ICU_SPI_OFFSET (CpIndex);
   /* Get MSI addresses per interrupt group */
   Msi = IcuDesc->IcuMsi;
 
@@ -230,7 +191,7 @@ IcuClearGicSpi (
   /* Get the base of the GIC SPI ID in the MSI message */
   SpiBase = IcuDesc->IcuSpiBase;
   /* Get multiple CP110 instances SPI ID shift */
-  SpiOffset = CpIndex * ICU_MAX_IRQS_PER_CP;
+  SpiOffset = ICU_SPI_OFFSET (CpIndex);
   /* Get MSI addresses per interrupt group */
   Msi = IcuDesc->IcuMsi;
 
@@ -254,10 +215,6 @@ IcuCleanUp (
   IcuDesc = Context;
 
   CpCount = FixedPcdGet8 (PcdMaxCpCount);
-  if (CpCount > ICU_MAX_SUPPORTED_UNITS) {
-    CpCount = ICU_MAX_SUPPORTED_UNITS;
-  }
-
   for (CpIndex = 0; CpIndex < CpCount; CpIndex++) {
     IcuClearGicSpi (CpIndex, IcuDesc);
   }
@@ -272,18 +229,8 @@ ArmadaIcuInitialize (
   UINTN CpCount, CpIndex;
   EFI_STATUS Status;
 
-  /*
-   * Due to limited amount of interrupt lanes, only 2 units can be
-   * wired to the GIC.
-   */
   CpCount = FixedPcdGet8 (PcdMaxCpCount);
-  if (CpCount > ICU_MAX_SUPPORTED_UNITS) {
-    DEBUG ((DEBUG_ERROR,
-      "%a: Default ICU to GIC mapping is available for maximum %d CP110 units",
-      __FUNCTION__,
-      ICU_MAX_SUPPORTED_UNITS));
-    CpCount = ICU_MAX_SUPPORTED_UNITS;
-  }
+  ASSERT (CpCount <= ICU_MAX_SUPPORTED_UNITS);
 
   /* Obtain SoC description of the ICU */
   Status = ArmadaSoCDescIcuGet (&IcuDesc);
-- 
2.29.0

Re: [edk2-platforms PATCH 0/6] Marvell multiple PCIE support

[Ard Biesheuvel]

On Mon, 2 Aug 2021 at 07:01, Marcin Wojtas <mw@semihalf.com> wrote:
>
> This patchset is a preparation for adding a new platform
> (CN913x CEx7 Evaluation Board). It modifies a common
> Marvell code in order to enable multiple PCIE controllers.
> Moreover a default interrupt map is reworked, so that to
> support all CP11x south bridge units.
> Last but not least, a custom initialization sequence
> can be executed thanks to a new board description library
> extension.
>
> More details can be found in the commit logs.
> The patchest is publicly available in the github:
> https://github.com/semihalf-wojtas-marcin/edk2-platforms/commits/pcie-r20210802
>
> Best regards,
> Marcin
>
> Kamil Koczurek (1):
>   Marvell: Armada7k8k/OcteonTx: Add multiple PCIE ports support
>
> Marcin Wojtas (5):
>   Marvell: Armada7k8k/OcteonTx: Allow memory mapping for more config
>     spaces
>   Marvell: Armada7k8k/OcteonTx: Allow tuning PCIE config space size
>   Marvell: Armada7k8kPciHostBridgeLib: Remove ECAM base limitation
>   Marvell: Armada7k8k/OcteonTX: Enable additional board configuration
>   Marvell: IcuLib: Rework default interrupt map
>

Pushed as d84c0545f4b4..73ccc21d918c

Thanks,


>  Platform/Marvell/Cn913xDb/Cn9130DbA.dsc.inc                                                 |   7 --
>  Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc                                               |   7 --
>  Silicon/Marvell/Armada7k8k/Drivers/PlatInitDxe/PlatInitDxe.inf                              |   1 +
>  Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLib.inf                          |   1 +
>  Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciSegmentLib/PciSegmentLib.inf                |  11 +-
>  Silicon/Marvell/Armada7k8k/AcpiTables/IcuInterrupts.h                                       |  48 ++++----
>  Silicon/Marvell/Include/Library/ArmadaBoardDescLib.h                                        |  10 ++
>  Silicon/Marvell/Library/IcuLib/IcuLib.h                                                     |   6 +-
>  Silicon/Marvell/OcteonTx/AcpiTables/T91/IcuInterrupts.h                                     |  61 +++++++----
>  Platform/Marvell/Armada70x0Db/Armada70x0DbBoardDescLib/Armada70x0DbBoardDescLib.c           |  11 ++
>  Platform/Marvell/Armada80x0Db/Armada80x0DbBoardDescLib/Armada80x0DbBoardDescLib.c           |  11 ++
>  Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9130DbABoardDescLib.c                       |  11 ++
>  Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9132DbABoardDescLib.c                       |  11 ++
>  Platform/SolidRun/Armada80x0McBin/Armada80x0McBinBoardDescLib/Armada80x0McBinBoardDescLib.c |  11 ++
>  Silicon/Marvell/Armada7k8k/Drivers/PlatInitDxe/PlatInitDxe.c                                |   2 +
>  Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLibMem.c                         |  18 ++-
>  Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciHostBridgeLib/PciHostBridgeLib.c            |  15 ++-
>  Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciHostBridgeLib/PciHostBridgeLibConstructor.c |   1 -
>  Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciSegmentLib/PciSegmentLib.c                  |  69 +++++++++++-
>  Silicon/Marvell/Library/IcuLib/IcuLib.c                                                     | 115 ++++++--------------
>  20 files changed, 267 insertions(+), 160 deletions(-)
>
> --
> 2.29.0
>