From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by mx.groups.io with SMTP id smtpd.web11.6716.1685969612963123395 for ; Mon, 05 Jun 2023 05:53:33 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=WxEi1YnC; spf=pass (domain: kernel.org, ip: 139.178.84.217, mailfrom: ardb@kernel.org) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 5203862155 for ; Mon, 5 Jun 2023 12:53:32 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id B849DC433D2 for ; Mon, 5 Jun 2023 12:53:31 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1685969611; bh=vrdsnSp8rcxItvklYPcie6Hr+KyJjGaKdSeqWseabUU=; h=References:In-Reply-To:From:Date:Subject:To:Cc:From; b=WxEi1YnCvW0OuoA80mOWDbazFt+kKahIXEt9gs51jUjzGJxBBaQ1w2xr9Gi9wbvwZ PmAGbrfBGSVenXEcqyp2OuurO9SWIaTpWoDudu3eAhcn1lWRhgGanAvXtgV2NyX1De P5YnWUWk8koIuUveQBjcaeD4J1/FDwWAbP/Y5NYgtrwlQc/RQOU7SYFOmNXuj/FzZg ZU2QkCz/6YVMVbfbebYqYhb1Qq646UfryqucTHVuuQn79WjREikIgnpxxv89NaidQd zlQ8HKY6/1eQDwAMUvV37zlU5cQU1RFd/Cj+NNpkl1Z/0VkcFGcnWBbioBxCItAkeK 03QqE3GSBficQ== Received: by mail-lj1-f181.google.com with SMTP id 38308e7fff4ca-2b1acd41ad2so40752751fa.3 for ; Mon, 05 Jun 2023 05:53:31 -0700 (PDT) X-Gm-Message-State: AC+VfDyy5tJvTlffJ/njPOyyKWWT/OtzqdcVkPww3Xbg5vptal+vP3h+ uKSkn0EOFzqHPAvDytIVM11nJel5R+7hDrjabG8= X-Google-Smtp-Source: ACHHUZ5xjNGBeLlZW7K9lta0w8/dI8s5EcmFbO+D0SnC8RDSfpfSAlR5SMHdiNK54fuSJZRKc0JFIsg+Q/sIXDwm1mQ= X-Received: by 2002:a2e:98da:0:b0:2ac:8e5a:1054 with SMTP id s26-20020a2e98da000000b002ac8e5a1054mr3958427ljj.0.1685969609764; Mon, 05 Jun 2023 05:53:29 -0700 (PDT) MIME-Version: 1.0 References: <20230605124726.124268-1-wangyuquan1236@phytium.com.cn> In-Reply-To: <20230605124726.124268-1-wangyuquan1236@phytium.com.cn> From: "Ard Biesheuvel" Date: Mon, 5 Jun 2023 14:53:18 +0200 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH v1 0/3] use XHCI to replace EHCI To: Yuquan Wang Cc: ardb+tianocore@kernel.org, quic_llindhol@quicinc.com, quic_ggregory@quicinc.com, rad@semihalf.com, devel@edk2.groups.io, chenbaozi@phytium.com.cn, marcin.juszkiewicz@linaro.org, peter.maydell@linaro.org Content-Type: text/plain; charset="UTF-8" On Mon, 5 Jun 2023 at 14:48, Yuquan Wang wrote: > > This patchset implements XHCI on sbsa-ref board to replace EHCI. > As sbsa-ref does not have DRAM below 4G, it cannot utilize EHCI > that only has 32-bit DMA capablity. Now this board has XHCI as > an available usb controller with 64-bit DMA capablity. > > This version(v1) has removed Change-Id from patch files and > fixed formatting issues. > > Yuquan Wang (3): > Platform/Qemu/SbsaQemu/SbsaQemu.dsc: define XHCI Pcd settings > SbsaQemu: Drivers: Add initial support for XHCI > SbsaQemu: AcpiTables: Add XHCI info into DSDT > Do all sbsa-ref implementation expose this device? If not, shouldn't this be discovered dynamically? > Platform/Qemu/SbsaQemu/SbsaQemu.dsc | 6 +- > .../Qemu/SbsaQemu/AcpiTables/AcpiTables.inf | 4 +- > Silicon/Qemu/SbsaQemu/AcpiTables/Dsdt.asl | 125 ++---------------- > .../SbsaQemuPlatformDxe/SbsaQemuPlatformDxe.c | 40 ++++-- > .../SbsaQemuPlatformDxe.inf | 2 + > Silicon/Qemu/SbsaQemu/SbsaQemu.dec | 4 +- > 6 files changed, 53 insertions(+), 128 deletions(-) > > -- > 2.34.1 > >