From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by mx.groups.io with SMTP id smtpd.web11.33701.1620662092448168717 for ; Mon, 10 May 2021 08:54:52 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=TVDCzfHn; spf=pass (domain: kernel.org, ip: 198.145.29.99, mailfrom: ardb@kernel.org) Received: by mail.kernel.org (Postfix) with ESMTPSA id 8DCA361624 for ; Mon, 10 May 2021 15:54:51 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1620662091; bh=91opBCn/Nn8KzdBPnfBQkdDAueQbZhKYvnqsGmknEQo=; h=References:In-Reply-To:From:Date:Subject:To:Cc:From; b=TVDCzfHn0hVVJRGvRHjBiIgZoYN5m6/VJwINEXTVrH3KhjIHm4S6JPemdEFooyaxp Ts1xNIVTkz8gPdnf78Dc+ZZxPI7D6Czbyzzj7AS0V3r/zStoaZFl3ZRFEayxEmi7XE /8i4uNcaFAGTTPD2/b4RJFxpomW/+/S/k/WdjcNWIBR+myH95NYiLmXW6Jp8D3+anu ZeY19JfT4hJHf4oRhpMIequA20K4qmHjW8TvEqLWMKCwTe2JlT8OyF3qv82GIYdeOl q4RMyqEm+GfqYrvStlts+XhP/Udzfs99Q6q37+Oq6AKuNddOD0rS1b19UZeTULZ7y7 Eh1hrvHohJREw== Received: by mail-oo1-f51.google.com with SMTP id c12-20020a4ae24c0000b02901bad05f40e4so3568457oot.4 for ; Mon, 10 May 2021 08:54:51 -0700 (PDT) X-Gm-Message-State: AOAM531vrkcQvpaQkqNdAVThSeCq3FVVrNFbnkRoik/aDckg0I6LM19N bG85CSmwp1RyC/wpdt94nUdUrHHEIcoWgNYpeI8= X-Google-Smtp-Source: ABdhPJxMNFMu7xthuQI+69nYTpuZkTNwzRKQs+AxNFt9y7wzIN5/vPXbwRzcEiZfVFvU0bnrO245s64+lp5ngI2n600= X-Received: by 2002:a4a:b997:: with SMTP id e23mr19381299oop.13.1620662090900; Mon, 10 May 2021 08:54:50 -0700 (PDT) MIME-Version: 1.0 References: <20210504152048.8739-1-etienne.carriere@linaro.org> <20210504152048.8739-4-etienne.carriere@linaro.org> In-Reply-To: <20210504152048.8739-4-etienne.carriere@linaro.org> From: "Ard Biesheuvel" Date: Mon, 10 May 2021 17:54:40 +0200 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH 3/5] GenGv: Arm: support images entered in Thumb mode To: Etienne Carriere , "Feng, Bob C" , "Liming Gao (Byosoft address)" Cc: edk2-devel-groups-io , Achin Gupta , Ard Biesheuvel , Jiewen Yao , Leif Lindholm , Sami Mujawar , Sughosh Ganu Content-Type: text/plain; charset="UTF-8" On Tue, 4 May 2021 at 17:20, Etienne Carriere wrote: > > Change GenFv for Arm architecture to generate a specific jump > instruction as image entry instruction, when the target entry label > is assembled with Thumb instruction set. This is possible since > SecCoreEntryAddress value fetched from the PE32 as its LSBit set when > the entry instruction executes in Thumb mode. > > Cc: Bob Feng > Cc: Liming Gao > Cc: Achin Gupta > Cc: Ard Biesheuvel > Cc: Leif Lindholm > Cc: Sughosh Ganu > Signed-off-by: Etienne Carriere This looks fine to me (modulo a couple of typos: GenGv, enry) but this needs an ack from the BaseTools maintainers. Bob, Liming? > --- > BaseTools/Source/C/GenFv/GenFvInternalLib.c | 38 +++++++++++++++----- > 1 file changed, 29 insertions(+), 9 deletions(-) > > diff --git a/BaseTools/Source/C/GenFv/GenFvInternalLib.c b/BaseTools/Source/C/GenFv/GenFvInternalLib.c > index 6e296b8ad6..3af65146f6 100644 > --- a/BaseTools/Source/C/GenFv/GenFvInternalLib.c > +++ b/BaseTools/Source/C/GenFv/GenFvInternalLib.c > @@ -34,9 +34,27 @@ SPDX-License-Identifier: BSD-2-Clause-Patent > #include "FvLib.h" > #include "PeCoffLib.h" > > -#define ARMT_UNCONDITIONAL_JUMP_INSTRUCTION 0xEB000000 > #define ARM64_UNCONDITIONAL_JUMP_INSTRUCTION 0x14000000 > > +/* > + * Arm instruction to jump to Fv enry instruction in Arm or Thumb mode. > + * From ARM Arch Ref Manual versions b/c/d, section A8.8.25 BL, BLX (immediate) > + * BLX (encoding A2) branches to offset in Thumb instruction set mode. > + * BL (encoding A1) branches to offset in Arm instruction set mode. > + */ > +#define ARM_JUMP_OFFSET_MAX 0xffffff > +#define ARM_JUMP_TO_ARM(Offset) (0xeb000000 | ((Offset - 8) >> 2)) > + > +#define _ARM_JUMP_TO_THUMB(Imm32) (0xfa000000 | \ > + (((Imm32) & (1 << 1)) << (24 - 1)) | \ > + (((Imm32) >> 2) & 0x7fffff)) > +#define ARM_JUMP_TO_THUMB(Offset) _ARM_JUMP_TO_THUMB((Offset) - 8) > + > +/* > + * Arm instruction to retrun from exception (MOVS PC, LR) > + */ > +#define ARM_RETURN_FROM_EXCEPTION 0xE1B0F07E > + > BOOLEAN mArm = FALSE; > BOOLEAN mRiscV = FALSE; > STATIC UINT32 MaxFfsAlignment = 0; > @@ -2203,23 +2221,25 @@ Returns: > // if we found an SEC core entry point then generate a branch instruction > // to it and populate a debugger SWI entry as well > if (UpdateVectorSec) { > + UINT32 EntryOffset; > > VerboseMsg("UpdateArmResetVectorIfNeeded updating ARM SEC vector"); > > - // B SecEntryPoint - signed_immed_24 part +/-32MB offset > - // on ARM, the PC is always 8 ahead, so we're not really jumping from the base address, but from base address + 8 > - ResetVector[0] = (INT32)(SecCoreEntryAddress - FvInfo->BaseAddress - 8) >> 2; > + EntryOffset = (INT32)(SecCoreEntryAddress - FvInfo->BaseAddress); > > - if (ResetVector[0] > 0x00FFFFFF) { > - Error(NULL, 0, 3000, "Invalid", "SEC Entry point must be within 32MB of the start of the FV"); > + if (EntryOffset > ARM_JUMP_OFFSET_MAX) { > + Error(NULL, 0, 3000, "Invalid", "SEC Entry point offset above 1MB of the start of the FV"); > return EFI_ABORTED; > } > > - // Add opcode for an unconditional branch with no link. i.e.: " B SecEntryPoint" > - ResetVector[0] |= ARMT_UNCONDITIONAL_JUMP_INSTRUCTION; > + if (SecCoreEntryAddress & 1) { > + ResetVector[0] = ARM_JUMP_TO_THUMB(EntryOffset); > + } else { > + ResetVector[0] = ARM_JUMP_TO_ARM(EntryOffset); > + } > > // SWI handler movs pc,lr. Just in case a debugger uses SWI > - ResetVector[2] = 0xE1B0F07E; > + ResetVector[2] = ARM_RETURN_FROM_EXCEPTION; > > // Place holder to support a common interrupt handler from ROM. > // Currently not supported. For this to be used the reset vector would not be in this FV > -- > 2.17.1 >