From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from ams.source.kernel.org (ams.source.kernel.org [145.40.68.75]) by mx.groups.io with SMTP id smtpd.web11.10042.1645708403861517101 for ; Thu, 24 Feb 2022 05:13:24 -0800 Authentication-Results: mx.groups.io; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=uw0T/7l7; spf=pass (domain: kernel.org, ip: 145.40.68.75, mailfrom: ardb@kernel.org) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id 13A4EB825C6 for ; Thu, 24 Feb 2022 13:13:21 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id B1C09C340F5 for ; Thu, 24 Feb 2022 13:13:19 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1645708399; bh=hxTG1yRzy1IBYNKeUAfAkCTWZeawOx7zwYtW+otkYrw=; h=References:In-Reply-To:From:Date:Subject:To:Cc:From; b=uw0T/7l7fxTUfZxu8T03UdbjkKzxsZ7chh0Z36iR6AzK7vLVxP3iHO6Rr2K4G4nnA MF34naQCn+23bzH1n4j4QkH9ttTFv26i1hStbyVKi1E5EYAlKJ0haAWz7htl62Q5PF dE4K/tPA4HxJ3iUptFAvHNy+90PMqaYmDzklzOzJwxoLp62mOvc8ZYJhWBliR38gyq bmOTBvNevFnBzg2BgIukiqjzFvYWU2Dzx88aBSyGlyDZriEiyhdfCsE+V9xPEBPBfb VZMa6alwMG4BUPT1zOCgTT9TRXYGugdNGS5qF4jwVcyYjwxCKIvulkAEn0wOOXzTFf UKCyHr1M7FZ8g== Received: by mail-yw1-f174.google.com with SMTP id 00721157ae682-2d641c31776so24166227b3.12 for ; Thu, 24 Feb 2022 05:13:19 -0800 (PST) X-Gm-Message-State: AOAM531ccrA2YRkBLKfbGT+P+BZPaL7XdRxvESPjRq+J+7yX7cbFs9hP +Cf+Zk/gNqGjQKHGMr2iBuHw/IzkxFc7W240DVg= X-Google-Smtp-Source: ABdhPJyzgkWRRiMPNWth9xI6FWW97NzQvaj1dwjW/6EO4HLaH+PxdrIulaNB/6ylNKgqilPvh0OqqwKsXWLSecFGbHw= X-Received: by 2002:a0d:dfd5:0:b0:2cf:924b:105d with SMTP id i204-20020a0ddfd5000000b002cf924b105dmr2342421ywe.342.1645708398601; Thu, 24 Feb 2022 05:13:18 -0800 (PST) MIME-Version: 1.0 References: <20220224125753.2021633-1-quic_tpilar@quicinc.com> In-Reply-To: <20220224125753.2021633-1-quic_tpilar@quicinc.com> From: "Ard Biesheuvel" Date: Thu, 24 Feb 2022 14:13:07 +0100 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [edk2-devel] [PATCH v2] MdeModulePkg: Correct high-memory use in NvmExpressDxe To: edk2-devel-groups-io , Tomas Pilar Cc: Ray Ni , Ard Biesheuvel , Leif Lindholm Content-Type: text/plain; charset="UTF-8" On Thu, 24 Feb 2022 at 13:58, Tomas Pilar (tpilar) wrote: > > Move the logic that sets EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE Pci > > attribute to DriverBindingStart() before the memory that backs the > > DMA engine is allocated. > > > > This ensures that the DMA-backing memory is not forcibly allocated > > below 4G in system address map. Otherwise the allocation fails on > > platforms that do not have any memory below the 4G mark and the drive > > initialisation fails. > > > > Cc: Ray Ni > > Cc: Ard Biesheuvel > > Cc: Leif Lindholm > > Signed-off-by: Tomas Pilar Ehm, nope, that is not exactly what I meant. The existing code stores the original PCI attributes in the controller private data, enables MMIO/IO decoding and bus mastering, and only then sets the dual address cycle attribute. All of that needs to move, so that the captured attributes are accurate. > > --- > > MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpress.c | 13 +++++++++++++ > > MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressHci.c | 13 ------------- > > 2 files changed, 13 insertions(+), 13 deletions(-) > > > > diff --git a/MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpress.c b/MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpress.c > > index 9d40f67e8e..1f0fc5bb68 100644 > > --- a/MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpress.c > > +++ b/MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpress.c > > @@ -959,6 +959,19 @@ NvmExpressDriverBindingStart ( > > goto Exit; > > } > > > > + // > > + // Enable 64-bit DMA support in the PCI layer. > > + // > > + Status = PciIo->Attributes ( > > + PciIo, > > + EfiPciIoAttributeOperationEnable, > > + EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE, > > + NULL > > + ); > > + if (EFI_ERROR (Status)) { > > + DEBUG ((DEBUG_WARN, "NvmeControllerInit: failed to enable 64-bit DMA (%r)\n", Status)); > > + } > > + > > // > > // 6 x 4kB aligned buffers will be carved out of this buffer. > > // 1st 4kB boundary is the start of the admin submission queue. > > diff --git a/MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressHci.c b/MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressHci.c > > index ac77afe113..748cb0ba24 100644 > > --- a/MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressHci.c > > +++ b/MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressHci.c > > @@ -764,19 +764,6 @@ NvmeControllerInit ( > > return Status; > > } > > > > - // > > - // Enable 64-bit DMA support in the PCI layer. > > - // > > - Status = PciIo->Attributes ( > > - PciIo, > > - EfiPciIoAttributeOperationEnable, > > - EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE, > > - NULL > > - ); > > - if (EFI_ERROR (Status)) { > > - DEBUG ((DEBUG_WARN, "NvmeControllerInit: failed to enable 64-bit DMA (%r)\n", Status)); > > - } > > - > > // > > // Read the Controller Capabilities register and verify that the NVM command set is supported > > // > > -- > > 2.30.2 > > > > > >