From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from ams.source.kernel.org (ams.source.kernel.org [145.40.68.75]) by mx.groups.io with SMTP id smtpd.web10.2971.1645656881109170503 for ; Wed, 23 Feb 2022 14:54:41 -0800 Authentication-Results: mx.groups.io; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=tDqXbjz1; spf=pass (domain: kernel.org, ip: 145.40.68.75, mailfrom: ardb@kernel.org) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id 8279CB821FA for ; Wed, 23 Feb 2022 22:54:38 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 07B0FC340F4 for ; Wed, 23 Feb 2022 22:54:37 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1645656877; bh=wwUT7VM83qxfY1/fL/2wSiEsM6Jo4I/D70TNVqLPpDc=; h=References:In-Reply-To:From:Date:Subject:To:Cc:From; b=tDqXbjz1OX9UEOTNms1lMi8depPU3dJvCuGbMSg5LHWjxcnJfT/KffVAvRkBhEK4b ZKDr7a78hnGKGdJIMH8Sdb4jU4rL1itqb6/fZCReiWTL+MviA42CT/tBMBR5mI8Mx2 lAPNXaV1S1BM6jliw/AWfNTteSz2LOxe83wxQ74X2CfP1/vJQgbUqVdP5YdOr3q059 w6wgen8moNDFdf/7nFsRca5OeBWLxwrlwsDlhx2bFMA+N737UC0UZMGqRXNVwIdEAn zrDxRl7bYooGqMeChIvoj7OxqXS7q1Ao0YUlXa8Gsw+XjBtZh+iIS/jhXgle5ie5r4 31B0EJK1Yr9OQ== Received: by mail-yw1-f176.google.com with SMTP id 00721157ae682-2d07c4a0d06so5690377b3.13 for ; Wed, 23 Feb 2022 14:54:36 -0800 (PST) X-Gm-Message-State: AOAM531quMnryQmxsy96zB0aQrb077ahUN8GLN7nnuqyfM+h2QSBwfbc r7I6WrWE2w4C/a4LEV26OFLnE9Xi3EFIRf7GE98= X-Google-Smtp-Source: ABdhPJxVbHYkjt0wbvLq2ALyWmWiccnTQ55fQc1+bKWbFGGGNC1p8W+7S6Ih4goWA2pszYqipjEcMM8AtiroIlYozB0= X-Received: by 2002:a81:4a45:0:b0:2d6:b212:6a76 with SMTP id x66-20020a814a45000000b002d6b2126a76mr1778784ywa.60.1645656876080; Wed, 23 Feb 2022 14:54:36 -0800 (PST) MIME-Version: 1.0 References: <122c32bb19ed0730ef166b9f46d3b112bc9ed937.1645497637.git.ashishsingha@nvidia.com> <877d9m3qny.wl-maz@kernel.org> In-Reply-To: From: "Ard Biesheuvel" Date: Wed, 23 Feb 2022 23:54:24 +0100 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [edk2-devel] [PATCH] ArmPkg: Invalidate Instruction Cache On MMU Enable To: Ashish Singhal Cc: edk2-devel-groups-io , Marc Zyngier , Sami Mujawar , Ard Biesheuvel , Leif Lindholm Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Wed, 23 Feb 2022 at 19:14, Ashish Singhal wrot= e: > > Ard, > > During PrePi, I setup the initial memory map by calling into ArmConfigure= Mmu function with my memory table where device memory regions have attribut= e of ARM_MEMORY_REGION_ATTRIBUTE_DEVICE and DRAM regions have attribute of = ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK. > > For device memory, XN bit is set by ArmMemoryAttributeToPageAttribute fun= ction. After PrePi, when I add a region of memory to device memory from a D= XE driver, I call gDS->AddMemorySpace with EfiGcdMemoryTypeMemoryMappedIo a= nd EFI_MEMORY_UC | EFI_MEMORY_RUNTIME followed by gDS->SetMemorySpaceAttrib= utes with EFI_MEMORY_UC. > > Please let me know in case I have still not understood your question. > This all looks ok. But the real question is whether the address that the speculative access targets is mapped using the XN attribute or not, so you will need to find a way to check that. So there are a couple of options: - The XN attribute is set correctly, but the CPU is speculatively fetching instructions anyway. This would imply a severe hardware bug, and flushing the I-cache is unlikely to make a difference. - The speculative access is not the result of an instruction fetch, in which case I-cache maintenance is unlikely to help either. - The XN bit is not being set correctly, and so the MMU code needs to be fi= xed. Papering over this by adding I-cache maintenance doesn't seem the best course of action tbh. --=20 Ard.