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* [edk2-devel][PATCH v1 1/1] ArmPkg: CpuDxe: Sync GCD Capabilities With Page Table Attributes
@ 2023-04-26  0:09 Oliver Smith-Denny
  2023-05-01 13:02 ` Ard Biesheuvel
  0 siblings, 1 reply; 26+ messages in thread
From: Oliver Smith-Denny @ 2023-04-26  0:09 UTC (permalink / raw)
  To: devel
  Cc: Leif Lindholm, Ard Biesheuvel, Sami Mujawar, Michael Kubacki,
	Sean Brogan

When ArmPkg's CpuDxe driver initializes, it attempts to sync the
GCD with the page table. However, unlike when the UefiCpuPkg's
CpuDxe initializes, the Arm version does not update the GCD
capabilities with EFI_MEMORY_[RO|RP|XP] (this could also set
the capabilities to be the existing page table attributes for
this range, but the UefiCpuPkg CpuDxe sets the above attributes
as they are software constructs, possible to set for any memory
hardware).

As a result, when the GCD attributes are attempted to be set
against the old GCD capabilities, attributes that are set in the
page table can get lost because the new attributes are not in the
old GCD capabilities (and yet they are already set in the page
table) meaning that the attempted sync between the GCD and the
page table was a failure and drivers querying one vs the other
will see different state. This can lead to RWX memory regions
even with the no-execute policy set, because core drivers (such
as NonDiscoverablePciDeviceIo, to be fixed up in a later patchset)
allocate pages, query the GCD attributes, attempt to set a new
cache attribute and end up clearing the XP bit in the page table
because the GCD attributes do not have XP set.

This patch follows the UefiCpuPkg pattern and adds
EFI_MEMORY_[RO|RP|XP] to the GCD capabilities during CpuDxe
initialization. This ensures that memory regions which already have
these attributes set get them set in the GCD attributes, properly
syncing between the GCD and the page table.

This mitigates the issue seen, however, additional investigations
into setting the GCD attributes earlier and maintaining a better
sync between the GCD and the page table are being done.

Feedback on this proposal is greatly appreciated, particularly
any pitfalls or more architectural solutions to issues seen
with syncing the GCD and the page table.

PR: https://github.com/tianocore/edk2/pull/4311
Personal branch: https://github.com/os-d/edk2/tree/osde/sync_aarch64_gcd_capabilities_v1

Cc: Leif Lindholm <quic_llindhol@quicinc.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Sami Mujawar <sami.mujawar@arm.com>
Cc: Michael Kubacki <mikuback@linux.microsoft.com>
Cc: Sean Brogan <sean.brogan@microsoft.com>

Signed-off-by: Oliver Smith-Denny <osde@linux.microsoft.com>
---
 ArmPkg/Drivers/CpuDxe/CpuMmuCommon.c | 55 +++++++++++++++++---
 1 file changed, 49 insertions(+), 6 deletions(-)

diff --git a/ArmPkg/Drivers/CpuDxe/CpuMmuCommon.c b/ArmPkg/Drivers/CpuDxe/CpuMmuCommon.c
index 2e73719dce04..3ef0380e084f 100644
--- a/ArmPkg/Drivers/CpuDxe/CpuMmuCommon.c
+++ b/ArmPkg/Drivers/CpuDxe/CpuMmuCommon.c
@@ -90,6 +90,7 @@ SetGcdMemorySpaceAttributes (
   UINTN                 EndIndex;
   EFI_PHYSICAL_ADDRESS  RegionStart;
   UINT64                RegionLength;
+  UINT64                Capabilities;
 
   DEBUG ((
     DEBUG_GCD,
@@ -146,14 +147,56 @@ SetGcdMemorySpaceAttributes (
       RegionLength = MemorySpaceMap[Index].BaseAddress + MemorySpaceMap[Index].Length - RegionStart;
     }
 
+    // Always add RO, RP, and XP as all memory is capable of supporting these types (they are software
+    // constructs, not hardware features) and they are critical to maintaining a security boundary
+    Capabilities = MemorySpaceMap[Index].Capabilities | EFI_MEMORY_RO | EFI_MEMORY_RP | EFI_MEMORY_XP;
+
     //
-    // Set memory attributes according to MTRR attribute and the original attribute of descriptor
+    // Update GCD capabilities as these may have changed in the page table since the GCD was created
+    // this follows the same pattern as x86 GCD and Page Table syncing
     //
-    gDS->SetMemorySpaceAttributes (
-           RegionStart,
-           RegionLength,
-           (MemorySpaceMap[Index].Attributes & ~EFI_MEMORY_CACHETYPE_MASK) | (MemorySpaceMap[Index].Capabilities & Attributes)
-           );
+    Status = gDS->SetMemorySpaceCapabilities (
+                    RegionStart,
+                    RegionLength,
+                    Capabilities
+                    );
+
+    if (EFI_ERROR (Status)) {
+      DEBUG ((
+        DEBUG_ERROR,
+        "%a - failed to update GCD capabilities: 0x%llx on memory region: 0x%llx length: 0x%llx Status: %r\n",
+        __func__,
+        Capabilities,
+        RegionStart,
+        RegionLength,
+        Status
+        ));
+      ASSERT_EFI_ERROR (Status);
+      continue;
+    }
+
+    //
+    // Set memory attributes according to the page table attribute and the original attribute of descriptor
+    //
+    Status = gDS->SetMemorySpaceAttributes (
+                    RegionStart,
+                    RegionLength,
+                    (MemorySpaceMap[Index].Attributes & ~EFI_MEMORY_CACHETYPE_MASK) | (Attributes & Capabilities)
+                    );
+
+    if (EFI_ERROR (Status)) {
+      DEBUG ((
+        DEBUG_ERROR,
+        "%a - failed to update GCD attributes: 0x%llx on memory region: 0x%llx length: 0x%llx Status: %r\n",
+        __func__,
+        Attributes,
+        RegionStart,
+        RegionLength,
+        Status
+        ));
+      ASSERT_EFI_ERROR (Status);
+      continue;
+    }
   }
 
   return EFI_SUCCESS;
-- 
2.40.0


^ permalink raw reply related	[flat|nested] 26+ messages in thread

* Re: [edk2-devel][PATCH v1 1/1] ArmPkg: CpuDxe: Sync GCD Capabilities With Page Table Attributes
  2023-04-26  0:09 Oliver Smith-Denny
@ 2023-05-01 13:02 ` Ard Biesheuvel
  2023-05-01 17:03   ` Oliver Smith-Denny
  0 siblings, 1 reply; 26+ messages in thread
From: Ard Biesheuvel @ 2023-05-01 13:02 UTC (permalink / raw)
  To: Oliver Smith-Denny
  Cc: devel, Leif Lindholm, Ard Biesheuvel, Sami Mujawar,
	Michael Kubacki, Sean Brogan

On Wed, 26 Apr 2023 at 02:09, Oliver Smith-Denny
<osde@linux.microsoft.com> wrote:
>
> When ArmPkg's CpuDxe driver initializes, it attempts to sync the
> GCD with the page table. However, unlike when the UefiCpuPkg's
> CpuDxe initializes, the Arm version does not update the GCD
> capabilities with EFI_MEMORY_[RO|RP|XP] (this could also set
> the capabilities to be the existing page table attributes for
> this range, but the UefiCpuPkg CpuDxe sets the above attributes
> as they are software constructs, possible to set for any memory
> hardware).
>
> As a result, when the GCD attributes are attempted to be set
> against the old GCD capabilities, attributes that are set in the
> page table can get lost because the new attributes are not in the
> old GCD capabilities (and yet they are already set in the page
> table) meaning that the attempted sync between the GCD and the
> page table was a failure and drivers querying one vs the other
> will see different state. This can lead to RWX memory regions
> even with the no-execute policy set, because core drivers (such
> as NonDiscoverablePciDeviceIo, to be fixed up in a later patchset)
> allocate pages, query the GCD attributes, attempt to set a new
> cache attribute and end up clearing the XP bit in the page table
> because the GCD attributes do not have XP set.
>
> This patch follows the UefiCpuPkg pattern and adds
> EFI_MEMORY_[RO|RP|XP] to the GCD capabilities during CpuDxe
> initialization. This ensures that memory regions which already have
> these attributes set get them set in the GCD attributes, properly
> syncing between the GCD and the page table.
>
> This mitigates the issue seen, however, additional investigations
> into setting the GCD attributes earlier and maintaining a better
> sync between the GCD and the page table are being done.
>
> Feedback on this proposal is greatly appreciated, particularly
> any pitfalls or more architectural solutions to issues seen
> with syncing the GCD and the page table.
>

I think this is conceptually correct. However, I've played with this
in the past, and IIRC, these attributes are inherited by the EFI
memory map too, and not updated when allocations are made. This means
that all code and data regions will be listed as RP, RO and XP in the
EFI memory map, which is going to confuse Linux at the very least, and
potentially other OSes as well.

Generally, the EFI and PI specs are very vague when it comes to
defining whether memory region attributes apply to the memory region
itself ("this memory can be mapped as read-only or non-exec") or its
contents ("these pages can be mapped read-only because the code does
not expect to be able to write to it").

Before we have some clarification and some rigid wording in the spec
as to what these attributes actually mean for non-allocated regions vs
allocated ones, I don't think we can use them like this.
Alternatively, we could update the GCD core so these attributes are
not inherited by the EFI memory map.

Another potential concern is fragmentation: the GCD memory map has
very few entries usually under the current usage model, but keeping
track of all memory permission attributes is going to inflate its size
substantially.

Also, including EFI_MEMORY_RP only makes sense if we implement a way
to apply it, which ArmCpuDxe currently does not provide.


> PR: https://github.com/tianocore/edk2/pull/4311
> Personal branch: https://github.com/os-d/edk2/tree/osde/sync_aarch64_gcd_capabilities_v1
>
> Cc: Leif Lindholm <quic_llindhol@quicinc.com>
> Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
> Cc: Sami Mujawar <sami.mujawar@arm.com>
> Cc: Michael Kubacki <mikuback@linux.microsoft.com>
> Cc: Sean Brogan <sean.brogan@microsoft.com>
>
> Signed-off-by: Oliver Smith-Denny <osde@linux.microsoft.com>
> ---
>  ArmPkg/Drivers/CpuDxe/CpuMmuCommon.c | 55 +++++++++++++++++---
>  1 file changed, 49 insertions(+), 6 deletions(-)
>
> diff --git a/ArmPkg/Drivers/CpuDxe/CpuMmuCommon.c b/ArmPkg/Drivers/CpuDxe/CpuMmuCommon.c
> index 2e73719dce04..3ef0380e084f 100644
> --- a/ArmPkg/Drivers/CpuDxe/CpuMmuCommon.c
> +++ b/ArmPkg/Drivers/CpuDxe/CpuMmuCommon.c
> @@ -90,6 +90,7 @@ SetGcdMemorySpaceAttributes (
>    UINTN                 EndIndex;
>    EFI_PHYSICAL_ADDRESS  RegionStart;
>    UINT64                RegionLength;
> +  UINT64                Capabilities;
>
>    DEBUG ((
>      DEBUG_GCD,
> @@ -146,14 +147,56 @@ SetGcdMemorySpaceAttributes (
>        RegionLength = MemorySpaceMap[Index].BaseAddress + MemorySpaceMap[Index].Length - RegionStart;
>      }
>
> +    // Always add RO, RP, and XP as all memory is capable of supporting these types (they are software
> +    // constructs, not hardware features) and they are critical to maintaining a security boundary
> +    Capabilities = MemorySpaceMap[Index].Capabilities | EFI_MEMORY_RO | EFI_MEMORY_RP | EFI_MEMORY_XP;
> +
>      //
> -    // Set memory attributes according to MTRR attribute and the original attribute of descriptor
> +    // Update GCD capabilities as these may have changed in the page table since the GCD was created
> +    // this follows the same pattern as x86 GCD and Page Table syncing
>      //
> -    gDS->SetMemorySpaceAttributes (
> -           RegionStart,
> -           RegionLength,
> -           (MemorySpaceMap[Index].Attributes & ~EFI_MEMORY_CACHETYPE_MASK) | (MemorySpaceMap[Index].Capabilities & Attributes)
> -           );
> +    Status = gDS->SetMemorySpaceCapabilities (
> +                    RegionStart,
> +                    RegionLength,
> +                    Capabilities
> +                    );
> +
> +    if (EFI_ERROR (Status)) {
> +      DEBUG ((
> +        DEBUG_ERROR,
> +        "%a - failed to update GCD capabilities: 0x%llx on memory region: 0x%llx length: 0x%llx Status: %r\n",
> +        __func__,
> +        Capabilities,
> +        RegionStart,
> +        RegionLength,
> +        Status
> +        ));
> +      ASSERT_EFI_ERROR (Status);
> +      continue;
> +    }
> +
> +    //
> +    // Set memory attributes according to the page table attribute and the original attribute of descriptor
> +    //
> +    Status = gDS->SetMemorySpaceAttributes (
> +                    RegionStart,
> +                    RegionLength,
> +                    (MemorySpaceMap[Index].Attributes & ~EFI_MEMORY_CACHETYPE_MASK) | (Attributes & Capabilities)
> +                    );
> +
> +    if (EFI_ERROR (Status)) {
> +      DEBUG ((
> +        DEBUG_ERROR,
> +        "%a - failed to update GCD attributes: 0x%llx on memory region: 0x%llx length: 0x%llx Status: %r\n",
> +        __func__,
> +        Attributes,
> +        RegionStart,
> +        RegionLength,
> +        Status
> +        ));
> +      ASSERT_EFI_ERROR (Status);
> +      continue;
> +    }
>    }
>
>    return EFI_SUCCESS;
> --
> 2.40.0
>

^ permalink raw reply	[flat|nested] 26+ messages in thread

* Re: [edk2-devel][PATCH v1 1/1] ArmPkg: CpuDxe: Sync GCD Capabilities With Page Table Attributes
  2023-05-01 13:02 ` Ard Biesheuvel
@ 2023-05-01 17:03   ` Oliver Smith-Denny
  2023-05-01 17:49     ` [edk2-devel] [PATCH " Michael D Kinney
  0 siblings, 1 reply; 26+ messages in thread
From: Oliver Smith-Denny @ 2023-05-01 17:03 UTC (permalink / raw)
  To: Ard Biesheuvel
  Cc: devel, Leif Lindholm, Ard Biesheuvel, Sami Mujawar,
	Michael Kubacki, Sean Brogan

On 5/1/2023 6:02 AM, Ard Biesheuvel wrote:
> On Wed, 26 Apr 2023 at 02:09, Oliver Smith-Denny
> <osde@linux.microsoft.com> wrote:
>>
>> When ArmPkg's CpuDxe driver initializes, it attempts to sync the
>> GCD with the page table. However, unlike when the UefiCpuPkg's
>> CpuDxe initializes, the Arm version does not update the GCD
>> capabilities with EFI_MEMORY_[RO|RP|XP] (this could also set
>> the capabilities to be the existing page table attributes for
>> this range, but the UefiCpuPkg CpuDxe sets the above attributes
>> as they are software constructs, possible to set for any memory
>> hardware).
>>
>> As a result, when the GCD attributes are attempted to be set
>> against the old GCD capabilities, attributes that are set in the
>> page table can get lost because the new attributes are not in the
>> old GCD capabilities (and yet they are already set in the page
>> table) meaning that the attempted sync between the GCD and the
>> page table was a failure and drivers querying one vs the other
>> will see different state. This can lead to RWX memory regions
>> even with the no-execute policy set, because core drivers (such
>> as NonDiscoverablePciDeviceIo, to be fixed up in a later patchset)
>> allocate pages, query the GCD attributes, attempt to set a new
>> cache attribute and end up clearing the XP bit in the page table
>> because the GCD attributes do not have XP set.
>>
>> This patch follows the UefiCpuPkg pattern and adds
>> EFI_MEMORY_[RO|RP|XP] to the GCD capabilities during CpuDxe
>> initialization. This ensures that memory regions which already have
>> these attributes set get them set in the GCD attributes, properly
>> syncing between the GCD and the page table.
>>
>> This mitigates the issue seen, however, additional investigations
>> into setting the GCD attributes earlier and maintaining a better
>> sync between the GCD and the page table are being done.
>>
>> Feedback on this proposal is greatly appreciated, particularly
>> any pitfalls or more architectural solutions to issues seen
>> with syncing the GCD and the page table.
>>
> 
> I think this is conceptually correct. However, I've played with this
> in the past, and IIRC, these attributes are inherited by the EFI
> memory map too, and not updated when allocations are made. This means
> that all code and data regions will be listed as RP, RO and XP in the
> EFI memory map, which is going to confuse Linux at the very least, and
> potentially other OSes as well.

Thanks for the detailed response, I appreciate it!
A clarification here: my patch follows what the x86 code does (see
https://github.com/tianocore/edk2/blob/56e9828380b7425678a080bd3a08e7c741af67ba/UefiCpuPkg/CpuDxe/CpuPageTable.c#LL994C1-L1077C27),
where the capabilities of each region are updated to include RP, RO, and
XP. However, the attributes of each region are only updated to include
these flags if the page table has the attributes set for this region.
I.e. we are only allowing for the possibility of these bits to be
set, but not actually setting them in the attributes unless the page
table already has them set. So, at the very least, we should be
matching what x86 does (so OS's should not be broken), unless
the other discrepancies in the x86 and Arm memory attribute handling
cause issue.

The main thing my change is intended to address is the case where
code that uses the GCD instead of the page table (such as the
NonDiscoverablePciDeviceIo driver I mentioned) attempts to set
a CPU memory attribute (such as UC) and ends up clearing the XP bit
that was set in the page table, but wasn't in the GCD (because it was
never properly synced with the page table). This could also be solved
by going to each caller and updating it to set the GCD capabilities
before it sets the GCD attributes (and perhaps they should be, already).
However, this puts the burden of maintaining memory protections such
as XP on each caller, instead of handling it at a core level (now,
there are of course complete design changes that could make this more
effective, but this was an attempt at a simple first step).

My understanding is that the EFI memory map is built on demand by calls
to GetMemoryMap from the page descriptor list, which is updated
thoughout bootservices, i.e. that it isn't pulling from the GCD. I will
go back and trace through this logic again.

> 
> Generally, the EFI and PI specs are very vague when it comes to
> defining whether memory region attributes apply to the memory region
> itself ("this memory can be mapped as read-only or non-exec") or its
> contents ("these pages can be mapped read-only because the code does
> not expect to be able to write to it").
> 
> Before we have some clarification and some rigid wording in the spec
> as to what these attributes actually mean for non-allocated regions vs
> allocated ones, I don't think we can use them like this.
> Alternatively, we could update the GCD core so these attributes are
> not inherited by the EFI memory map.
> 
> Another potential concern is fragmentation: the GCD memory map has
> very few entries usually under the current usage model, but keeping
> track of all memory permission attributes is going to inflate its size
> substantially.

I think this should not change the size of the GCD, right? It is not
tracking any more regions than it already was. It simply is updating
the capabilities of each region it was already tracking (and possibly
the attributes if the page table had RO, RP, or XP set). I agree that
not tracking each range of memory is critical, we have seen issues when
non-existent memory was getting tracked.

> 
> Also, including EFI_MEMORY_RP only makes sense if we implement a way
> to apply it, which ArmCpuDxe currently does not provide.

Thanks for pointing this out, I hadn't traced and seen that RP is not
implemented. If this moves forward, I can drop it (and with a comment
why it is different).

> 
> 
>> PR: https://github.com/tianocore/edk2/pull/4311
>> Personal branch: https://github.com/os-d/edk2/tree/osde/sync_aarch64_gcd_capabilities_v1
>>
>> Cc: Leif Lindholm <quic_llindhol@quicinc.com>
>> Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
>> Cc: Sami Mujawar <sami.mujawar@arm.com>
>> Cc: Michael Kubacki <mikuback@linux.microsoft.com>
>> Cc: Sean Brogan <sean.brogan@microsoft.com>
>>
>> Signed-off-by: Oliver Smith-Denny <osde@linux.microsoft.com>
>> ---
>>   ArmPkg/Drivers/CpuDxe/CpuMmuCommon.c | 55 +++++++++++++++++---
>>   1 file changed, 49 insertions(+), 6 deletions(-)
>>
>> diff --git a/ArmPkg/Drivers/CpuDxe/CpuMmuCommon.c b/ArmPkg/Drivers/CpuDxe/CpuMmuCommon.c
>> index 2e73719dce04..3ef0380e084f 100644
>> --- a/ArmPkg/Drivers/CpuDxe/CpuMmuCommon.c
>> +++ b/ArmPkg/Drivers/CpuDxe/CpuMmuCommon.c
>> @@ -90,6 +90,7 @@ SetGcdMemorySpaceAttributes (
>>     UINTN                 EndIndex;
>>     EFI_PHYSICAL_ADDRESS  RegionStart;
>>     UINT64                RegionLength;
>> +  UINT64                Capabilities;
>>
>>     DEBUG ((
>>       DEBUG_GCD,
>> @@ -146,14 +147,56 @@ SetGcdMemorySpaceAttributes (
>>         RegionLength = MemorySpaceMap[Index].BaseAddress + MemorySpaceMap[Index].Length - RegionStart;
>>       }
>>
>> +    // Always add RO, RP, and XP as all memory is capable of supporting these types (they are software
>> +    // constructs, not hardware features) and they are critical to maintaining a security boundary
>> +    Capabilities = MemorySpaceMap[Index].Capabilities | EFI_MEMORY_RO | EFI_MEMORY_RP | EFI_MEMORY_XP;
>> +
>>       //
>> -    // Set memory attributes according to MTRR attribute and the original attribute of descriptor
>> +    // Update GCD capabilities as these may have changed in the page table since the GCD was created
>> +    // this follows the same pattern as x86 GCD and Page Table syncing
>>       //
>> -    gDS->SetMemorySpaceAttributes (
>> -           RegionStart,
>> -           RegionLength,
>> -           (MemorySpaceMap[Index].Attributes & ~EFI_MEMORY_CACHETYPE_MASK) | (MemorySpaceMap[Index].Capabilities & Attributes)
>> -           );
>> +    Status = gDS->SetMemorySpaceCapabilities (
>> +                    RegionStart,
>> +                    RegionLength,
>> +                    Capabilities
>> +                    );
>> +
>> +    if (EFI_ERROR (Status)) {
>> +      DEBUG ((
>> +        DEBUG_ERROR,
>> +        "%a - failed to update GCD capabilities: 0x%llx on memory region: 0x%llx length: 0x%llx Status: %r\n",
>> +        __func__,
>> +        Capabilities,
>> +        RegionStart,
>> +        RegionLength,
>> +        Status
>> +        ));
>> +      ASSERT_EFI_ERROR (Status);
>> +      continue;
>> +    }
>> +
>> +    //
>> +    // Set memory attributes according to the page table attribute and the original attribute of descriptor
>> +    //
>> +    Status = gDS->SetMemorySpaceAttributes (
>> +                    RegionStart,
>> +                    RegionLength,
>> +                    (MemorySpaceMap[Index].Attributes & ~EFI_MEMORY_CACHETYPE_MASK) | (Attributes & Capabilities)
>> +                    );
>> +
>> +    if (EFI_ERROR (Status)) {
>> +      DEBUG ((
>> +        DEBUG_ERROR,
>> +        "%a - failed to update GCD attributes: 0x%llx on memory region: 0x%llx length: 0x%llx Status: %r\n",
>> +        __func__,
>> +        Attributes,
>> +        RegionStart,
>> +        RegionLength,
>> +        Status
>> +        ));
>> +      ASSERT_EFI_ERROR (Status);
>> +      continue;
>> +    }
>>     }
>>
>>     return EFI_SUCCESS;
>> --
>> 2.40.0
>>

^ permalink raw reply	[flat|nested] 26+ messages in thread

* Re: [edk2-devel] [PATCH v1 1/1] ArmPkg: CpuDxe: Sync GCD Capabilities With Page Table Attributes
  2023-05-01 17:03   ` Oliver Smith-Denny
@ 2023-05-01 17:49     ` Michael D Kinney
  2023-05-01 17:50       ` Ard Biesheuvel
  0 siblings, 1 reply; 26+ messages in thread
From: Michael D Kinney @ 2023-05-01 17:49 UTC (permalink / raw)
  To: devel@edk2.groups.io, osde@linux.microsoft.com, Ard Biesheuvel,
	Ni, Ray
  Cc: Leif Lindholm, Ard Biesheuvel, Sami Mujawar, Michael Kubacki,
	Sean Brogan, Kinney, Michael D

Hi,

These UEFI Memory Map, GCD, and Page Table interactions can be complex and I
agree there are some UEFI/PI spec clarifications that may help.

Ray hosts a TianoCore design meeting when needed.  Do you think a meeting with
an open discussion on these topics would help, or do we prefer to continue with
email discussions?

Thanks,

Mike

> -----Original Message-----
> From: devel@edk2.groups.io <devel@edk2.groups.io> On Behalf Of Oliver
> Smith-Denny
> Sent: Monday, May 1, 2023 10:04 AM
> To: Ard Biesheuvel <ardb@kernel.org>
> Cc: devel@edk2.groups.io; Leif Lindholm <quic_llindhol@quicinc.com>; Ard
> Biesheuvel <ardb+tianocore@kernel.org>; Sami Mujawar
> <sami.mujawar@arm.com>; Michael Kubacki
> <mikuback@linux.microsoft.com>; Sean Brogan
> <sean.brogan@microsoft.com>
> Subject: Re: [edk2-devel] [PATCH v1 1/1] ArmPkg: CpuDxe: Sync GCD
> Capabilities With Page Table Attributes
> 
> On 5/1/2023 6:02 AM, Ard Biesheuvel wrote:
> > On Wed, 26 Apr 2023 at 02:09, Oliver Smith-Denny
> > <osde@linux.microsoft.com> wrote:
> >>
> >> When ArmPkg's CpuDxe driver initializes, it attempts to sync the
> >> GCD with the page table. However, unlike when the UefiCpuPkg's
> >> CpuDxe initializes, the Arm version does not update the GCD
> >> capabilities with EFI_MEMORY_[RO|RP|XP] (this could also set
> >> the capabilities to be the existing page table attributes for
> >> this range, but the UefiCpuPkg CpuDxe sets the above attributes
> >> as they are software constructs, possible to set for any memory
> >> hardware).
> >>
> >> As a result, when the GCD attributes are attempted to be set
> >> against the old GCD capabilities, attributes that are set in the
> >> page table can get lost because the new attributes are not in the
> >> old GCD capabilities (and yet they are already set in the page
> >> table) meaning that the attempted sync between the GCD and the
> >> page table was a failure and drivers querying one vs the other
> >> will see different state. This can lead to RWX memory regions
> >> even with the no-execute policy set, because core drivers (such
> >> as NonDiscoverablePciDeviceIo, to be fixed up in a later patchset)
> >> allocate pages, query the GCD attributes, attempt to set a new
> >> cache attribute and end up clearing the XP bit in the page table
> >> because the GCD attributes do not have XP set.
> >>
> >> This patch follows the UefiCpuPkg pattern and adds
> >> EFI_MEMORY_[RO|RP|XP] to the GCD capabilities during CpuDxe
> >> initialization. This ensures that memory regions which already have
> >> these attributes set get them set in the GCD attributes, properly
> >> syncing between the GCD and the page table.
> >>
> >> This mitigates the issue seen, however, additional investigations
> >> into setting the GCD attributes earlier and maintaining a better
> >> sync between the GCD and the page table are being done.
> >>
> >> Feedback on this proposal is greatly appreciated, particularly
> >> any pitfalls or more architectural solutions to issues seen
> >> with syncing the GCD and the page table.
> >>
> >
> > I think this is conceptually correct. However, I've played with this
> > in the past, and IIRC, these attributes are inherited by the EFI
> > memory map too, and not updated when allocations are made. This means
> > that all code and data regions will be listed as RP, RO and XP in the
> > EFI memory map, which is going to confuse Linux at the very least, and
> > potentially other OSes as well.
> 
> Thanks for the detailed response, I appreciate it!
> A clarification here: my patch follows what the x86 code does (see
> https://github.com/tianocore/edk2/blob/56e9828380b7425678a080bd3a08e
> 7c741af67ba/UefiCpuPkg/CpuDxe/CpuPageTable.c#LL994C1-L1077C27),
> where the capabilities of each region are updated to include RP, RO, and
> XP. However, the attributes of each region are only updated to include
> these flags if the page table has the attributes set for this region.
> I.e. we are only allowing for the possibility of these bits to be
> set, but not actually setting them in the attributes unless the page
> table already has them set. So, at the very least, we should be
> matching what x86 does (so OS's should not be broken), unless
> the other discrepancies in the x86 and Arm memory attribute handling
> cause issue.
> 
> The main thing my change is intended to address is the case where
> code that uses the GCD instead of the page table (such as the
> NonDiscoverablePciDeviceIo driver I mentioned) attempts to set
> a CPU memory attribute (such as UC) and ends up clearing the XP bit
> that was set in the page table, but wasn't in the GCD (because it was
> never properly synced with the page table). This could also be solved
> by going to each caller and updating it to set the GCD capabilities
> before it sets the GCD attributes (and perhaps they should be, already).
> However, this puts the burden of maintaining memory protections such
> as XP on each caller, instead of handling it at a core level (now,
> there are of course complete design changes that could make this more
> effective, but this was an attempt at a simple first step).
> 
> My understanding is that the EFI memory map is built on demand by calls
> to GetMemoryMap from the page descriptor list, which is updated
> thoughout bootservices, i.e. that it isn't pulling from the GCD. I will
> go back and trace through this logic again.
> 
> >
> > Generally, the EFI and PI specs are very vague when it comes to
> > defining whether memory region attributes apply to the memory region
> > itself ("this memory can be mapped as read-only or non-exec") or its
> > contents ("these pages can be mapped read-only because the code does
> > not expect to be able to write to it").
> >
> > Before we have some clarification and some rigid wording in the spec
> > as to what these attributes actually mean for non-allocated regions vs
> > allocated ones, I don't think we can use them like this.
> > Alternatively, we could update the GCD core so these attributes are
> > not inherited by the EFI memory map.
> >
> > Another potential concern is fragmentation: the GCD memory map has
> > very few entries usually under the current usage model, but keeping
> > track of all memory permission attributes is going to inflate its size
> > substantially.
> 
> I think this should not change the size of the GCD, right? It is not
> tracking any more regions than it already was. It simply is updating
> the capabilities of each region it was already tracking (and possibly
> the attributes if the page table had RO, RP, or XP set). I agree that
> not tracking each range of memory is critical, we have seen issues when
> non-existent memory was getting tracked.
> 
> >
> > Also, including EFI_MEMORY_RP only makes sense if we implement a way
> > to apply it, which ArmCpuDxe currently does not provide.
> 
> Thanks for pointing this out, I hadn't traced and seen that RP is not
> implemented. If this moves forward, I can drop it (and with a comment
> why it is different).
> 
> >
> >
> >> PR: https://github.com/tianocore/edk2/pull/4311
> >> Personal branch: https://github.com/os-
> d/edk2/tree/osde/sync_aarch64_gcd_capabilities_v1
> >>
> >> Cc: Leif Lindholm <quic_llindhol@quicinc.com>
> >> Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
> >> Cc: Sami Mujawar <sami.mujawar@arm.com>
> >> Cc: Michael Kubacki <mikuback@linux.microsoft.com>
> >> Cc: Sean Brogan <sean.brogan@microsoft.com>
> >>
> >> Signed-off-by: Oliver Smith-Denny <osde@linux.microsoft.com>
> >> ---
> >>   ArmPkg/Drivers/CpuDxe/CpuMmuCommon.c | 55
> +++++++++++++++++---
> >>   1 file changed, 49 insertions(+), 6 deletions(-)
> >>
> >> diff --git a/ArmPkg/Drivers/CpuDxe/CpuMmuCommon.c
> b/ArmPkg/Drivers/CpuDxe/CpuMmuCommon.c
> >> index 2e73719dce04..3ef0380e084f 100644
> >> --- a/ArmPkg/Drivers/CpuDxe/CpuMmuCommon.c
> >> +++ b/ArmPkg/Drivers/CpuDxe/CpuMmuCommon.c
> >> @@ -90,6 +90,7 @@ SetGcdMemorySpaceAttributes (
> >>     UINTN                 EndIndex;
> >>     EFI_PHYSICAL_ADDRESS  RegionStart;
> >>     UINT64                RegionLength;
> >> +  UINT64                Capabilities;
> >>
> >>     DEBUG ((
> >>       DEBUG_GCD,
> >> @@ -146,14 +147,56 @@ SetGcdMemorySpaceAttributes (
> >>         RegionLength = MemorySpaceMap[Index].BaseAddress +
> MemorySpaceMap[Index].Length - RegionStart;
> >>       }
> >>
> >> +    // Always add RO, RP, and XP as all memory is capable of supporting
> these types (they are software
> >> +    // constructs, not hardware features) and they are critical to
> maintaining a security boundary
> >> +    Capabilities = MemorySpaceMap[Index].Capabilities |
> EFI_MEMORY_RO | EFI_MEMORY_RP | EFI_MEMORY_XP;
> >> +
> >>       //
> >> -    // Set memory attributes according to MTRR attribute and the original
> attribute of descriptor
> >> +    // Update GCD capabilities as these may have changed in the page
> table since the GCD was created
> >> +    // this follows the same pattern as x86 GCD and Page Table syncing
> >>       //
> >> -    gDS->SetMemorySpaceAttributes (
> >> -           RegionStart,
> >> -           RegionLength,
> >> -           (MemorySpaceMap[Index].Attributes &
> ~EFI_MEMORY_CACHETYPE_MASK) |
> (MemorySpaceMap[Index].Capabilities & Attributes)
> >> -           );
> >> +    Status = gDS->SetMemorySpaceCapabilities (
> >> +                    RegionStart,
> >> +                    RegionLength,
> >> +                    Capabilities
> >> +                    );
> >> +
> >> +    if (EFI_ERROR (Status)) {
> >> +      DEBUG ((
> >> +        DEBUG_ERROR,
> >> +        "%a - failed to update GCD capabilities: 0x%llx on memory region:
> 0x%llx length: 0x%llx Status: %r\n",
> >> +        __func__,
> >> +        Capabilities,
> >> +        RegionStart,
> >> +        RegionLength,
> >> +        Status
> >> +        ));
> >> +      ASSERT_EFI_ERROR (Status);
> >> +      continue;
> >> +    }
> >> +
> >> +    //
> >> +    // Set memory attributes according to the page table attribute and the
> original attribute of descriptor
> >> +    //
> >> +    Status = gDS->SetMemorySpaceAttributes (
> >> +                    RegionStart,
> >> +                    RegionLength,
> >> +                    (MemorySpaceMap[Index].Attributes &
> ~EFI_MEMORY_CACHETYPE_MASK) | (Attributes & Capabilities)
> >> +                    );
> >> +
> >> +    if (EFI_ERROR (Status)) {
> >> +      DEBUG ((
> >> +        DEBUG_ERROR,
> >> +        "%a - failed to update GCD attributes: 0x%llx on memory region:
> 0x%llx length: 0x%llx Status: %r\n",
> >> +        __func__,
> >> +        Attributes,
> >> +        RegionStart,
> >> +        RegionLength,
> >> +        Status
> >> +        ));
> >> +      ASSERT_EFI_ERROR (Status);
> >> +      continue;
> >> +    }
> >>     }
> >>
> >>     return EFI_SUCCESS;
> >> --
> >> 2.40.0
> >>
> 
> 
> 
> 


^ permalink raw reply	[flat|nested] 26+ messages in thread

* Re: [edk2-devel] [PATCH v1 1/1] ArmPkg: CpuDxe: Sync GCD Capabilities With Page Table Attributes
  2023-05-01 17:49     ` [edk2-devel] [PATCH " Michael D Kinney
@ 2023-05-01 17:50       ` Ard Biesheuvel
  2023-05-01 17:53         ` Oliver Smith-Denny
  0 siblings, 1 reply; 26+ messages in thread
From: Ard Biesheuvel @ 2023-05-01 17:50 UTC (permalink / raw)
  To: devel, michael.d.kinney
  Cc: osde@linux.microsoft.com, Ni, Ray, Leif Lindholm, Ard Biesheuvel,
	Sami Mujawar, Michael Kubacki, Sean Brogan

On Mon, 1 May 2023 at 19:49, Michael D Kinney
<michael.d.kinney@intel.com> wrote:
>
> Hi,
>
> These UEFI Memory Map, GCD, and Page Table interactions can be complex and I
> agree there are some UEFI/PI spec clarifications that may help.
>
> Ray hosts a TianoCore design meeting when needed.  Do you think a meeting with
> an open discussion on these topics would help, or do we prefer to continue with
> email discussions?
>

I'll gladly join a call to discuss this if we can find a timeslot that
works for everyone in terms of time zone. (I'm on Paris time)

^ permalink raw reply	[flat|nested] 26+ messages in thread

* Re: [edk2-devel] [PATCH v1 1/1] ArmPkg: CpuDxe: Sync GCD Capabilities With Page Table Attributes
  2023-05-01 17:50       ` Ard Biesheuvel
@ 2023-05-01 17:53         ` Oliver Smith-Denny
  2023-05-01 17:59           ` Michael D Kinney
  0 siblings, 1 reply; 26+ messages in thread
From: Oliver Smith-Denny @ 2023-05-01 17:53 UTC (permalink / raw)
  To: Ard Biesheuvel, devel, michael.d.kinney
  Cc: Ni, Ray, Leif Lindholm, Ard Biesheuvel, Sami Mujawar,
	Michael Kubacki, Sean Brogan

On 5/1/2023 10:50 AM, Ard Biesheuvel wrote:
> On Mon, 1 May 2023 at 19:49, Michael D Kinney
> <michael.d.kinney@intel.com> wrote:
>>
>> Hi,
>>
>> These UEFI Memory Map, GCD, and Page Table interactions can be complex and I
>> agree there are some UEFI/PI spec clarifications that may help.
>>
>> Ray hosts a TianoCore design meeting when needed.  Do you think a meeting with
>> an open discussion on these topics would help, or do we prefer to continue with
>> email discussions?
>>
> 
> I'll gladly join a call to discuss this if we can find a timeslot that
> works for everyone in terms of time zone. (I'm on Paris time)

I also think a call would be great, I certainly would benefit from
learning more here :). I'm sure various members of my team would
be interested in joining, happy to be flexible on timeslot (we are
generally in PST).

Thanks,
Oliver

^ permalink raw reply	[flat|nested] 26+ messages in thread

* Re: [edk2-devel] [PATCH v1 1/1] ArmPkg: CpuDxe: Sync GCD Capabilities With Page Table Attributes
  2023-05-01 17:53         ` Oliver Smith-Denny
@ 2023-05-01 17:59           ` Michael D Kinney
  2023-05-09  1:35             ` Ni, Ray
  0 siblings, 1 reply; 26+ messages in thread
From: Michael D Kinney @ 2023-05-01 17:59 UTC (permalink / raw)
  To: Oliver Smith-Denny, Ard Biesheuvel, devel@edk2.groups.io
  Cc: Ni, Ray, Leif Lindholm, Ard Biesheuvel, Sami Mujawar,
	Michael Kubacki, Sean Brogan, Kinney, Michael D

Thanks for the quick feedback.  Ray is out this week.  I will work with Ray to arrange a time slot, hopefully next week that works for everyone.

Mike

> -----Original Message-----
> From: Oliver Smith-Denny <osde@linux.microsoft.com>
> Sent: Monday, May 1, 2023 10:53 AM
> To: Ard Biesheuvel <ardb@kernel.org>; devel@edk2.groups.io; Kinney,
> Michael D <michael.d.kinney@intel.com>
> Cc: Ni, Ray <ray.ni@intel.com>; Leif Lindholm <quic_llindhol@quicinc.com>;
> Ard Biesheuvel <ardb+tianocore@kernel.org>; Sami Mujawar
> <sami.mujawar@arm.com>; Michael Kubacki
> <mikuback@linux.microsoft.com>; Sean Brogan
> <sean.brogan@microsoft.com>
> Subject: Re: [edk2-devel] [PATCH v1 1/1] ArmPkg: CpuDxe: Sync GCD
> Capabilities With Page Table Attributes
> 
> On 5/1/2023 10:50 AM, Ard Biesheuvel wrote:
> > On Mon, 1 May 2023 at 19:49, Michael D Kinney
> > <michael.d.kinney@intel.com> wrote:
> >>
> >> Hi,
> >>
> >> These UEFI Memory Map, GCD, and Page Table interactions can be
> complex and I
> >> agree there are some UEFI/PI spec clarifications that may help.
> >>
> >> Ray hosts a TianoCore design meeting when needed.  Do you think a
> meeting with
> >> an open discussion on these topics would help, or do we prefer to
> continue with
> >> email discussions?
> >>
> >
> > I'll gladly join a call to discuss this if we can find a timeslot that
> > works for everyone in terms of time zone. (I'm on Paris time)
> 
> I also think a call would be great, I certainly would benefit from
> learning more here :). I'm sure various members of my team would
> be interested in joining, happy to be flexible on timeslot (we are
> generally in PST).
> 
> Thanks,
> Oliver

^ permalink raw reply	[flat|nested] 26+ messages in thread

* Re: [edk2-devel] [PATCH v1 1/1] ArmPkg: CpuDxe: Sync GCD Capabilities With Page Table Attributes
  2023-05-01 17:59           ` Michael D Kinney
@ 2023-05-09  1:35             ` Ni, Ray
  2023-05-09  2:03               ` Oliver Smith-Denny
  0 siblings, 1 reply; 26+ messages in thread
From: Ni, Ray @ 2023-05-09  1:35 UTC (permalink / raw)
  To: Kinney, Michael D, Oliver Smith-Denny, Ard Biesheuvel,
	devel@edk2.groups.io
  Cc: Leif Lindholm, Ard Biesheuvel, Sami Mujawar, Michael Kubacki,
	Sean Brogan

[-- Attachment #1: Type: text/plain, Size: 2632 bytes --]

All,
Can you check if the meeting time is ok for you?

It will be in this week:
* PDT Thursday 07:00
* Paris Thursday 16:00
* Shanghai Thursday 22:00

Thanks,
Ray


> -----Original Message-----
> From: Kinney, Michael D <michael.d.kinney@intel.com>
> Sent: Tuesday, May 2, 2023 1:59 AM
> To: Oliver Smith-Denny <osde@linux.microsoft.com>; Ard Biesheuvel
> <ardb@kernel.org>; devel@edk2.groups.io
> Cc: Ni, Ray <ray.ni@intel.com>; Leif Lindholm <quic_llindhol@quicinc.com>;
> Ard Biesheuvel <ardb+tianocore@kernel.org>; Sami Mujawar
> <sami.mujawar@arm.com>; Michael Kubacki
> <mikuback@linux.microsoft.com>; Sean Brogan
> <sean.brogan@microsoft.com>; Kinney, Michael D
> <michael.d.kinney@intel.com>
> Subject: RE: [edk2-devel] [PATCH v1 1/1] ArmPkg: CpuDxe: Sync GCD
> Capabilities With Page Table Attributes
> 
> Thanks for the quick feedback.  Ray is out this week.  I will work with Ray to
> arrange a time slot, hopefully next week that works for everyone.
> 
> Mike
> 
> > -----Original Message-----
> > From: Oliver Smith-Denny <osde@linux.microsoft.com>
> > Sent: Monday, May 1, 2023 10:53 AM
> > To: Ard Biesheuvel <ardb@kernel.org>; devel@edk2.groups.io; Kinney,
> > Michael D <michael.d.kinney@intel.com>
> > Cc: Ni, Ray <ray.ni@intel.com>; Leif Lindholm <quic_llindhol@quicinc.com>;
> > Ard Biesheuvel <ardb+tianocore@kernel.org>; Sami Mujawar
> > <sami.mujawar@arm.com>; Michael Kubacki
> > <mikuback@linux.microsoft.com>; Sean Brogan
> > <sean.brogan@microsoft.com>
> > Subject: Re: [edk2-devel] [PATCH v1 1/1] ArmPkg: CpuDxe: Sync GCD
> > Capabilities With Page Table Attributes
> >
> > On 5/1/2023 10:50 AM, Ard Biesheuvel wrote:
> > > On Mon, 1 May 2023 at 19:49, Michael D Kinney
> > > <michael.d.kinney@intel.com> wrote:
> > >>
> > >> Hi,
> > >>
> > >> These UEFI Memory Map, GCD, and Page Table interactions can be
> > complex and I
> > >> agree there are some UEFI/PI spec clarifications that may help.
> > >>
> > >> Ray hosts a TianoCore design meeting when needed.  Do you think a
> > meeting with
> > >> an open discussion on these topics would help, or do we prefer to
> > continue with
> > >> email discussions?
> > >>
> > >
> > > I'll gladly join a call to discuss this if we can find a timeslot that
> > > works for everyone in terms of time zone. (I'm on Paris time)
> >
> > I also think a call would be great, I certainly would benefit from
> > learning more here :). I'm sure various members of my team would
> > be interested in joining, happy to be flexible on timeslot (we are
> > generally in PST).
> >
> > Thanks,
> > Oliver

[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #2: UEFI Memory Map GCD Page Table discussion - ARMX86.ics --]
[-- Type: text/calendar; name="UEFI Memory Map GCD Page Table discussion - ARMX86.ics", Size: 51528 bytes --]

BEGIN:VCALENDAR
PRODID:-//Microsoft Corporation//Outlook 16.0 MIMEDIR//EN
VERSION:2.0
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X-MS-OLK-FORCEINSPECTOROPEN:TRUE
BEGIN:VTIMEZONE
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DTSTART:16010101T000000
TZOFFSETFROM:+0800
TZOFFSETTO:+0800
END:STANDARD
END:VTIMEZONE
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	icrosoft.com/l/meetup-join/19%3ameeting_YTk4ZDU3YjItODkxZC00MTdmLTlkZmUtYT
	hkNGQ0ZWYyMDZh%40thread.v2/0?context=%7b%22Tid%22%3a%2246c98d88-e344-4ed4-
	8496-4ed7712e255d%22%2c%22Oid%22%3a%2255d36a50-78be-4ced-bc27-3d06c576cc19
	%22%7d>  \nMeeting ID: 256 188 860 359 \nPasscode: yJZsmm \nDownload Teams
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	8496-4ed7712e255d&threadId=19_meeting_YTk4ZDU3YjItODkxZC00MTdmLTlkZmUtYThk
	NGQ0ZWYyMDZh@thread.v2&messageId=0&language=en-US>  \n____________________
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DTEND;TZID="China Standard Time":20230511T230000
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PRIORITY:5
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SUMMARY;LANGUAGE=en-us:UEFI Memory Map\, GCD\, Page Table discussion - ARM/
	X86
TRANSP:OPAQUE
UID:040000008200E00074C5B7101A82E0080000000020C8B5925882D901000000000000000
	01000000043BF7D9269E0E24899EAE72E7F953601
X-ALT-DESC;FMTTYPE=text/html:\n<html xmlns:v="urn:schemas-microsoft-com:vml
	" xmlns:o="urn:schemas-microsoft-com:office:office" xmlns:w="urn:schemas-m
	icrosoft-com:office:word" xmlns:m="http://schemas.microsoft.com/office/200
	4/12/omml" xmlns="http://www.w3.org/TR/REC-html40"><head><meta name=ProgId
	 content=Word.Document><meta name=Generator content="Microsoft Word 15"><m
	eta name=Originator content="Microsoft Word 15"><link rel=File-List href="
	cid:filelist.xml@01D98258.E5F06450"><!--[if gte mso 9]><xml>\n<o:OfficeDoc
	umentSettings>\n<o:AllowPNG/>\n</o:OfficeDocumentSettings>\n</xml><![endif
	]--><!--[if gte mso 9]><xml>\n<w:WordDocument>\n<w:SpellingState>Clean</w:
	SpellingState>\n<w:GrammarState>Clean</w:GrammarState>\n<w:TrackMoves/>\n<
	w:TrackFormatting/>\n<w:EnvelopeVis/>\n<w:PunctuationKerning/>\n<w:Validat
	eAgainstSchemas/>\n<w:SaveIfXMLInvalid>false</w:SaveIfXMLInvalid>\n<w:Igno
	reMixedContent>false</w:IgnoreMixedContent>\n<w:AlwaysShowPlaceholderText>
	false</w:AlwaysShowPlaceholderText>\n<w:DoNotPromoteQF/>\n<w:LidThemeOther
	>EN-US</w:LidThemeOther>\n<w:LidThemeAsian>ZH-CN</w:LidThemeAsian>\n<w:Lid
	ThemeComplexScript>X-NONE</w:LidThemeComplexScript>\n<w:Compatibility>\n<w
	:BreakWrappedTables/>\n<w:SnapToGridInCell/>\n<w:WrapTextWithPunct/>\n<w:U
	seAsianBreakRules/>\n<w:DontGrowAutofit/>\n<w:SplitPgBreakAndParaMark/>\n<
	w:EnableOpenTypeKerning/>\n<w:DontFlipMirrorIndents/>\n<w:OverrideTableSty
	leHps/>\n<w:UseFELayout/>\n</w:Compatibility>\n<m:mathPr>\n<m:mathFont m:v
	al="Cambria Math"/>\n<m:brkBin m:val="before"/>\n<m:brkBinSub m:val="&#45\
	;-"/>\n<m:smallFrac m:val="off"/>\n<m:dispDef/>\n<m:lMargin m:val="0"/>\n<
	m:rMargin m:val="0"/>\n<m:defJc m:val="centerGroup"/>\n<m:wrapIndent m:val
	="1440"/>\n<m:intLim m:val="subSup"/>\n<m:naryLim m:val="undOvr"/>\n</m:ma
	thPr></w:WordDocument>\n</xml><![endif]--><!--[if gte mso 9]><xml>\n<w:Lat
	entStyles DefLockedState="false" DefUnhideWhenUsed="false" DefSemiHidden="
	false" DefQFormat="false" DefPriority="99" LatentStyleCount="376">\n<w:Lsd
	Exception Locked="false" Priority="0" QFormat="true" Name="Normal"/>\n<w:L
	sdException Locked="false" Priority="9" QFormat="true" Name="heading 1"/>\
	n<w:LsdException Locked="false" Priority="9" SemiHidden="true" UnhideWhenU
	sed="true" QFormat="true" Name="heading 2"/>\n<w:LsdException Locked="fals
	e" Priority="9" SemiHidden="true" UnhideWhenUsed="true" QFormat="true" Nam
	e="heading 3"/>\n<w:LsdException Locked="false" Priority="9" SemiHidden="t
	rue" UnhideWhenUsed="true" QFormat="true" Name="heading 4"/>\n<w:LsdExcept
	ion Locked="false" Priority="9" SemiHidden="true" UnhideWhenUsed="true" QF
	ormat="true" Name="heading 5"/>\n<w:LsdException Locked="false" Priority="
	9" SemiHidden="true" UnhideWhenUsed="true" QFormat="true" Name="heading 6"
	/>\n<w:LsdException Locked="false" Priority="9" SemiHidden="true" UnhideWh
	enUsed="true" QFormat="true" Name="heading 7"/>\n<w:LsdException Locked="f
	alse" Priority="9" SemiHidden="true" UnhideWhenUsed="true" QFormat="true" 
	Name="heading 8"/>\n<w:LsdException Locked="false" Priority="9" SemiHidden
	="true" UnhideWhenUsed="true" QFormat="true" Name="heading 9"/>\n<w:LsdExc
	eption Locked="false" SemiHidden="true" UnhideWhenUsed="true" Name="index 
	1"/>\n<w:LsdException Locked="false" SemiHidden="true" UnhideWhenUsed="tru
	e" Name="index 2"/>\n<w:LsdException Locked="false" SemiHidden="true" Unhi
	deWhenUsed="true" Name="index 3"/>\n<w:LsdException Locked="false" SemiHid
	den="true" UnhideWhenUsed="true" Name="index 4"/>\n<w:LsdException Locked=
	"false" SemiHidden="true" UnhideWhenUsed="true" Name="index 5"/>\n<w:LsdEx
	ception Locked="false" SemiHidden="true" UnhideWhenUsed="true" Name="index
	 6"/>\n<w:LsdException Locked="false" SemiHidden="true" UnhideWhenUsed="tr
	ue" Name="index 7"/>\n<w:LsdException Locked="false" SemiHidden="true" Unh
	ideWhenUsed="true" Name="index 8"/>\n<w:LsdException Locked="false" SemiHi
	dden="true" UnhideWhenUsed="true" Name="index 9"/>\n<w:LsdException Locked
	="false" Priority="39" SemiHidden="true" UnhideWhenUsed="true" Name="toc 1
	"/>\n<w:LsdException Locked="false" Priority="39" SemiHidden="true" Unhide
	WhenUsed="true" Name="toc 2"/>\n<w:LsdException Locked="false" Priority="3
	9" SemiHidden="true" UnhideWhenUsed="true" Name="toc 3"/>\n<w:LsdException
	 Locked="false" Priority="39" SemiHidden="true" UnhideWhenUsed="true" Name
	="toc 4"/>\n<w:LsdException Locked="false" Priority="39" SemiHidden="true"
	 UnhideWhenUsed="true" Name="toc 5"/>\n<w:LsdException Locked="false" Prio
	rity="39" SemiHidden="true" UnhideWhenUsed="true" Name="toc 6"/>\n<w:LsdEx
	ception Locked="false" Priority="39" SemiHidden="true" UnhideWhenUsed="tru
	e" Name="toc 7"/>\n<w:LsdException Locked="false" Priority="39" SemiHidden
	="true" UnhideWhenUsed="true" Name="toc 8"/>\n<w:LsdException Locked="fals
	e" Priority="39" SemiHidden="true" UnhideWhenUsed="true" Name="toc 9"/>\n<
	w:LsdException Locked="false" SemiHidden="true" UnhideWhenUsed="true" Name
	="Normal Indent"/>\n<w:LsdException Locked="false" SemiHidden="true" Unhid
	eWhenUsed="true" Name="footnote text"/>\n<w:LsdException Locked="false" Se
	miHidden="true" UnhideWhenUsed="true" Name="annotation text"/>\n<w:LsdExce
	ption Locked="false" SemiHidden="true" UnhideWhenUsed="true" Name="header"
	/>\n<w:LsdException Locked="false" SemiHidden="true" UnhideWhenUsed="true"
	 Name="footer"/>\n<w:LsdException Locked="false" SemiHidden="true" UnhideW
	henUsed="true" Name="index heading"/>\n<w:LsdException Locked="false" Prio
	rity="35" SemiHidden="true" UnhideWhenUsed="true" QFormat="true" Name="cap
	tion"/>\n<w:LsdException Locked="false" SemiHidden="true" UnhideWhenUsed="
	true" Name="table of figures"/>\n<w:LsdException Locked="false" SemiHidden
	="true" UnhideWhenUsed="true" Name="envelope address"/>\n<w:LsdException L
	ocked="false" SemiHidden="true" UnhideWhenUsed="true" Name="envelope retur
	n"/>\n<w:LsdException Locked="false" SemiHidden="true" UnhideWhenUsed="tru
	e" Name="footnote reference"/>\n<w:LsdException Locked="false" SemiHidden=
	"true" UnhideWhenUsed="true" Name="annotation reference"/>\n<w:LsdExceptio
	n Locked="false" SemiHidden="true" UnhideWhenUsed="true" Name="line number
	"/>\n<w:LsdException Locked="false" SemiHidden="true" UnhideWhenUsed="true
	" Name="page number"/>\n<w:LsdException Locked="false" SemiHidden="true" U
	nhideWhenUsed="true" Name="endnote reference"/>\n<w:LsdException Locked="f
	alse" SemiHidden="true" UnhideWhenUsed="true" Name="endnote text"/>\n<w:Ls
	dException Locked="false" SemiHidden="true" UnhideWhenUsed="true" Name="ta
	ble of authorities"/>\n<w:LsdException Locked="false" SemiHidden="true" Un
	hideWhenUsed="true" Name="macro"/>\n<w:LsdException Locked="false" SemiHid
	den="true" UnhideWhenUsed="true" Name="toa heading"/>\n<w:LsdException Loc
	ked="false" SemiHidden="true" UnhideWhenUsed="true" Name="List"/>\n<w:LsdE
	xception Locked="false" SemiHidden="true" UnhideWhenUsed="true" Name="List
	 Bullet"/>\n<w:LsdException Locked="false" SemiHidden="true" UnhideWhenUse
	d="true" Name="List Number"/>\n<w:LsdException Locked="false" SemiHidden="
	true" UnhideWhenUsed="true" Name="List 2"/>\n<w:LsdException Locked="false
	" SemiHidden="true" UnhideWhenUsed="true" Name="List 3"/>\n<w:LsdException
	 Locked="false" SemiHidden="true" UnhideWhenUsed="true" Name="List 4"/>\n<
	w:LsdException Locked="false" SemiHidden="true" UnhideWhenUsed="true" Name
	="List 5"/>\n<w:LsdException Locked="false" SemiHidden="true" UnhideWhenUs
	ed="true" Name="List Bullet 2"/>\n<w:LsdException Locked="false" SemiHidde
	n="true" UnhideWhenUsed="true" Name="List Bullet 3"/>\n<w:LsdException Loc
	ked="false" SemiHidden="true" UnhideWhenUsed="true" Name="List Bullet 4"/>
	\n<w:LsdException Locked="false" SemiHidden="true" UnhideWhenUsed="true" N
	ame="List Bullet 5"/>\n<w:LsdException Locked="false" SemiHidden="true" Un
	hideWhenUsed="true" Name="List Number 2"/>\n<w:LsdException Locked="false"
	 SemiHidden="true" UnhideWhenUsed="true" Name="List Number 3"/>\n<w:LsdExc
	eption Locked="false" SemiHidden="true" UnhideWhenUsed="true" Name="List N
	umber 4"/>\n<w:LsdException Locked="false" SemiHidden="true" UnhideWhenUse
	d="true" Name="List Number 5"/>\n<w:LsdException Locked="false" Priority="
	10" QFormat="true" Name="Title"/>\n<w:LsdException Locked="false" SemiHidd
	en="true" UnhideWhenUsed="true" Name="Closing"/>\n<w:LsdException Locked="
	false" SemiHidden="true" UnhideWhenUsed="true" Name="Signature"/>\n<w:LsdE
	xception Locked="false" Priority="1" SemiHidden="true" UnhideWhenUsed="tru
	e" Name="Default Paragraph Font"/>\n<w:LsdException Locked="false" SemiHid
	den="true" UnhideWhenUsed="true" Name="Body Text"/>\n<w:LsdException Locke
	d="false" SemiHidden="true" UnhideWhenUsed="true" Name="Body Text Indent"/
	>\n<w:LsdException Locked="false" SemiHidden="true" UnhideWhenUsed="true" 
	Name="List Continue"/>\n<w:LsdException Locked="false" SemiHidden="true" U
	nhideWhenUsed="true" Name="List Continue 2"/>\n<w:LsdException Locked="fal
	se" SemiHidden="true" UnhideWhenUsed="true" Name="List Continue 3"/>\n<w:L
	sdException Locked="false" SemiHidden="true" UnhideWhenUsed="true" Name="L
	ist Continue 4"/>\n<w:LsdException Locked="false" SemiHidden="true" Unhide
	WhenUsed="true" Name="List Continue 5"/>\n<w:LsdException Locked="false" S
	emiHidden="true" UnhideWhenUsed="true" Name="Message Header"/>\n<w:LsdExce
	ption Locked="false" Priority="11" QFormat="true" Name="Subtitle"/>\n<w:Ls
	dException Locked="false" SemiHidden="true" UnhideWhenUsed="true" Name="Sa
	lutation"/>\n<w:LsdException Locked="false" SemiHidden="true" UnhideWhenUs
	ed="true" Name="Date"/>\n<w:LsdException Locked="false" SemiHidden="true" 
	UnhideWhenUsed="true" Name="Body Text First Indent"/>\n<w:LsdException Loc
	ked="false" SemiHidden="true" UnhideWhenUsed="true" Name="Body Text First 
	Indent 2"/>\n<w:LsdException Locked="false" SemiHidden="true" UnhideWhenUs
	ed="true" Name="Note Heading"/>\n<w:LsdException Locked="false" SemiHidden
	="true" UnhideWhenUsed="true" Name="Body Text 2"/>\n<w:LsdException Locked
	="false" SemiHidden="true" UnhideWhenUsed="true" Name="Body Text 3"/>\n<w:
	LsdException Locked="false" SemiHidden="true" UnhideWhenUsed="true" Name="
	Body Text Indent 2"/>\n<w:LsdException Locked="false" SemiHidden="true" Un
	hideWhenUsed="true" Name="Body Text Indent 3"/>\n<w:LsdException Locked="f
	alse" SemiHidden="true" UnhideWhenUsed="true" Name="Block Text"/>\n<w:LsdE
	xception Locked="false" SemiHidden="true" UnhideWhenUsed="true" Name="Hype
	rlink"/>\n<w:LsdException Locked="false" SemiHidden="true" UnhideWhenUsed=
	"true" Name="FollowedHyperlink"/>\n<w:LsdException Locked="false" Priority
	="22" QFormat="true" Name="Strong"/>\n<w:LsdException Locked="false" Prior
	ity="20" QFormat="true" Name="Emphasis"/>\n<w:LsdException Locked="false" 
	SemiHidden="true" UnhideWhenUsed="true" Name="Document Map"/>\n<w:LsdExcep
	tion Locked="false" SemiHidden="true" UnhideWhenUsed="true" Name="Plain Te
	xt"/>\n<w:LsdException Locked="false" SemiHidden="true" UnhideWhenUsed="tr
	ue" Name="E-mail Signature"/>\n<w:LsdException Locked="false" SemiHidden="
	true" UnhideWhenUsed="true" Name="HTML Top of Form"/>\n<w:LsdException Loc
	ked="false" SemiHidden="true" UnhideWhenUsed="true" Name="HTML Bottom of F
	orm"/>\n<w:LsdException Locked="false" SemiHidden="true" UnhideWhenUsed="t
	rue" Name="Normal (Web)"/>\n<w:LsdException Locked="false" SemiHidden="tru
	e" UnhideWhenUsed="true" Name="HTML Acronym"/>\n<w:LsdException Locked="fa
	lse" SemiHidden="true" UnhideWhenUsed="true" Name="HTML Address"/>\n<w:Lsd
	Exception Locked="false" SemiHidden="true" UnhideWhenUsed="true" Name="HTM
	L Cite"/>\n<w:LsdException Locked="false" SemiHidden="true" UnhideWhenUsed
	="true" Name="HTML Code"/>\n<w:LsdException Locked="false" SemiHidden="tru
	e" UnhideWhenUsed="true" Name="HTML Definition"/>\n<w:LsdException Locked=
	"false" SemiHidden="true" UnhideWhenUsed="true" Name="HTML Keyboard"/>\n<w
	:LsdException Locked="false" SemiHidden="true" UnhideWhenUsed="true" Name=
	"HTML Preformatted"/>\n<w:LsdException Locked="false" SemiHidden="true" Un
	hideWhenUsed="true" Name="HTML Sample"/>\n<w:LsdException Locked="false" S
	emiHidden="true" UnhideWhenUsed="true" Name="HTML Typewriter"/>\n<w:LsdExc
	eption Locked="false" SemiHidden="true" UnhideWhenUsed="true" Name="HTML V
	ariable"/>\n<w:LsdException Locked="false" SemiHidden="true" UnhideWhenUse
	d="true" Name="Normal Table"/>\n<w:LsdException Locked="false" SemiHidden=
	"true" UnhideWhenUsed="true" Name="annotation subject"/>\n<w:LsdException 
	Locked="false" SemiHidden="true" UnhideWhenUsed="true" Name="No List"/>\n<
	w:LsdException Locked="false" SemiHidden="true" UnhideWhenUsed="true" Name
	="Outline List 1"/>\n<w:LsdException Locked="false" SemiHidden="true" Unhi
	deWhenUsed="true" Name="Outline List 2"/>\n<w:LsdException Locked="false" 
	SemiHidden="true" UnhideWhenUsed="true" Name="Outline List 3"/>\n<w:LsdExc
	eption Locked="false" SemiHidden="true" UnhideWhenUsed="true" Name="Table 
	Simple 1"/>\n<w:LsdException Locked="false" SemiHidden="true" UnhideWhenUs
	ed="true" Name="Table Simple 2"/>\n<w:LsdException Locked="false" SemiHidd
	en="true" UnhideWhenUsed="true" Name="Table Simple 3"/>\n<w:LsdException L
	ocked="false" SemiHidden="true" UnhideWhenUsed="true" Name="Table Classic 
	1"/>\n<w:LsdException Locked="false" SemiHidden="true" UnhideWhenUsed="tru
	e" Name="Table Classic 2"/>\n<w:LsdException Locked="false" SemiHidden="tr
	ue" UnhideWhenUsed="true" Name="Table Classic 3"/>\n<w:LsdException Locked
	="false" SemiHidden="true" UnhideWhenUsed="true" Name="Table Classic 4"/>\
	n<w:LsdException Locked="false" SemiHidden="true" UnhideWhenUsed="true" Na
	me="Table Colorful 1"/>\n<w:LsdException Locked="false" SemiHidden="true" 
	UnhideWhenUsed="true" Name="Table Colorful 2"/>\n<w:LsdException Locked="f
	alse" SemiHidden="true" UnhideWhenUsed="true" Name="Table Colorful 3"/>\n<
	w:LsdException Locked="false" SemiHidden="true" UnhideWhenUsed="true" Name
	="Table Columns 1"/>\n<w:LsdException Locked="false" SemiHidden="true" Unh
	ideWhenUsed="true" Name="Table Columns 2"/>\n<w:LsdException Locked="false
	" SemiHidden="true" UnhideWhenUsed="true" Name="Table Columns 3"/>\n<w:Lsd
	Exception Locked="false" SemiHidden="true" UnhideWhenUsed="true" Name="Tab
	le Columns 4"/>\n<w:LsdException Locked="false" SemiHidden="true" UnhideWh
	enUsed="true" Name="Table Columns 5"/>\n<w:LsdException Locked="false" Sem
	iHidden="true" UnhideWhenUsed="true" Name="Table Grid 1"/>\n<w:LsdExceptio
	n Locked="false" SemiHidden="true" UnhideWhenUsed="true" Name="Table Grid 
	2"/>\n<w:LsdException Locked="false" SemiHidden="true" UnhideWhenUsed="tru
	e" Name="Table Grid 3"/>\n<w:LsdException Locked="false" SemiHidden="true"
	 UnhideWhenUsed="true" Name="Table Grid 4"/>\n<w:LsdException Locked="fals
	e" SemiHidden="true" UnhideWhenUsed="true" Name="Table Grid 5"/>\n<w:LsdEx
	ception Locked="false" SemiHidden="true" UnhideWhenUsed="true" Name="Table
	 Grid 6"/>\n<w:LsdException Locked="false" SemiHidden="true" UnhideWhenUse
	d="true" Name="Table Grid 7"/>\n<w:LsdException Locked="false" SemiHidden=
	"true" UnhideWhenUsed="true" Name="Table Grid 8"/>\n<w:LsdException Locked
	="false" SemiHidden="true" UnhideWhenUsed="true" Name="Table List 1"/>\n<w
	:LsdException Locked="false" SemiHidden="true" UnhideWhenUsed="true" Name=
	"Table List 2"/>\n<w:LsdException Locked="false" SemiHidden="true" UnhideW
	henUsed="true" Name="Table List 3"/>\n<w:LsdException Locked="false" SemiH
	idden="true" UnhideWhenUsed="true" Name="Table List 4"/>\n<w:LsdException 
	Locked="false" SemiHidden="true" UnhideWhenUsed="true" Name="Table List 5"
	/>\n<w:LsdException Locked="false" SemiHidden="true" UnhideWhenUsed="true"
	 Name="Table List 6"/>\n<w:LsdException Locked="false" SemiHidden="true" U
	nhideWhenUsed="true" Name="Table List 7"/>\n<w:LsdException Locked="false"
	 SemiHidden="true" UnhideWhenUsed="true" Name="Table List 8"/>\n<w:LsdExce
	ption Locked="false" SemiHidden="true" UnhideWhenUsed="true" Name="Table 3
	D effects 1"/>\n<w:LsdException Locked="false" SemiHidden="true" UnhideWhe
	nUsed="true" Name="Table 3D effects 2"/>\n<w:LsdException Locked="false" S
	emiHidden="true" UnhideWhenUsed="true" Name="Table 3D effects 3"/>\n<w:Lsd
	Exception Locked="false" SemiHidden="true" UnhideWhenUsed="true" Name="Tab
	le Contemporary"/>\n<w:LsdException Locked="false" SemiHidden="true" Unhid
	eWhenUsed="true" Name="Table Elegant"/>\n<w:LsdException Locked="false" Se
	miHidden="true" UnhideWhenUsed="true" Name="Table Professional"/>\n<w:LsdE
	xception Locked="false" SemiHidden="true" UnhideWhenUsed="true" Name="Tabl
	e Subtle 1"/>\n<w:LsdException Locked="false" SemiHidden="true" UnhideWhen
	Used="true" Name="Table Subtle 2"/>\n<w:LsdException Locked="false" SemiHi
	dden="true" UnhideWhenUsed="true" Name="Table Web 1"/>\n<w:LsdException Lo
	cked="false" SemiHidden="true" UnhideWhenUsed="true" Name="Table Web 2"/>\
	n<w:LsdException Locked="false" SemiHidden="true" UnhideWhenUsed="true" Na
	me="Table Web 3"/>\n<w:LsdException Locked="false" SemiHidden="true" Unhid
	eWhenUsed="true" Name="Balloon Text"/>\n<w:LsdException Locked="false" Pri
	ority="39" Name="Table Grid"/>\n<w:LsdException Locked="false" SemiHidden=
	"true" UnhideWhenUsed="true" Name="Table Theme"/>\n<w:LsdException Locked=
	"false" SemiHidden="true" Name="Placeholder Text"/>\n<w:LsdException Locke
	d="false" Priority="1" QFormat="true" Name="No Spacing"/>\n<w:LsdException
	 Locked="false" Priority="60" Name="Light Shading"/>\n<w:LsdException Lock
	ed="false" Priority="61" Name="Light List"/>\n<w:LsdException Locked="fals
	e" Priority="62" Name="Light Grid"/>\n<w:LsdException Locked="false" Prior
	ity="63" Name="Medium Shading 1"/>\n<w:LsdException Locked="false" Priorit
	y="64" Name="Medium Shading 2"/>\n<w:LsdException Locked="false" Priority=
	"65" Name="Medium List 1"/>\n<w:LsdException Locked="false" Priority="66" 
	Name="Medium List 2"/>\n<w:LsdException Locked="false" Priority="67" Name=
	"Medium Grid 1"/>\n<w:LsdException Locked="false" Priority="68" Name="Medi
	um Grid 2"/>\n<w:LsdException Locked="false" Priority="69" Name="Medium Gr
	id 3"/>\n<w:LsdException Locked="false" Priority="70" Name="Dark List"/>\n
	<w:LsdException Locked="false" Priority="71" Name="Colorful Shading"/>\n<w
	:LsdException Locked="false" Priority="72" Name="Colorful List"/>\n<w:LsdE
	xception Locked="false" Priority="73" Name="Colorful Grid"/>\n<w:LsdExcept
	ion Locked="false" Priority="60" Name="Light Shading Accent 1"/>\n<w:LsdEx
	ception Locked="false" Priority="61" Name="Light List Accent 1"/>\n<w:LsdE
	xception Locked="false" Priority="62" Name="Light Grid Accent 1"/>\n<w:Lsd
	Exception Locked="false" Priority="63" Name="Medium Shading 1 Accent 1"/>\
	n<w:LsdException Locked="false" Priority="64" Name="Medium Shading 2 Accen
	t 1"/>\n<w:LsdException Locked="false" Priority="65" Name="Medium List 1 A
	ccent 1"/>\n<w:LsdException Locked="false" SemiHidden="true" Name="Revisio
	n"/>\n<w:LsdException Locked="false" Priority="34" QFormat="true" Name="Li
	st Paragraph"/>\n<w:LsdException Locked="false" Priority="29" QFormat="tru
	e" Name="Quote"/>\n<w:LsdException Locked="false" Priority="30" QFormat="t
	rue" Name="Intense Quote"/>\n<w:LsdException Locked="false" Priority="66" 
	Name="Medium List 2 Accent 1"/>\n<w:LsdException Locked="false" Priority="
	67" Name="Medium Grid 1 Accent 1"/>\n<w:LsdException Locked="false" Priori
	ty="68" Name="Medium Grid 2 Accent 1"/>\n<w:LsdException Locked="false" Pr
	iority="69" Name="Medium Grid 3 Accent 1"/>\n<w:LsdException Locked="false
	" Priority="70" Name="Dark List Accent 1"/>\n<w:LsdException Locked="false
	" Priority="71" Name="Colorful Shading Accent 1"/>\n<w:LsdException Locked
	="false" Priority="72" Name="Colorful List Accent 1"/>\n<w:LsdException Lo
	cked="false" Priority="73" Name="Colorful Grid Accent 1"/>\n<w:LsdExceptio
	n Locked="false" Priority="60" Name="Light Shading Accent 2"/>\n<w:LsdExce
	ption Locked="false" Priority="61" Name="Light List Accent 2"/>\n<w:LsdExc
	eption Locked="false" Priority="62" Name="Light Grid Accent 2"/>\n<w:LsdEx
	ception Locked="false" Priority="63" Name="Medium Shading 1 Accent 2"/>\n<
	w:LsdException Locked="false" Priority="64" Name="Medium Shading 2 Accent 
	2"/>\n<w:LsdException Locked="false" Priority="65" Name="Medium List 1 Acc
	ent 2"/>\n<w:LsdException Locked="false" Priority="66" Name="Medium List 2
	 Accent 2"/>\n<w:LsdException Locked="false" Priority="67" Name="Medium Gr
	id 1 Accent 2"/>\n<w:LsdException Locked="false" Priority="68" Name="Mediu
	m Grid 2 Accent 2"/>\n<w:LsdException Locked="false" Priority="69" Name="M
	edium Grid 3 Accent 2"/>\n<w:LsdException Locked="false" Priority="70" Nam
	e="Dark List Accent 2"/>\n<w:LsdException Locked="false" Priority="71" Nam
	e="Colorful Shading Accent 2"/>\n<w:LsdException Locked="false" Priority="
	72" Name="Colorful List Accent 2"/>\n<w:LsdException Locked="false" Priori
	ty="73" Name="Colorful Grid Accent 2"/>\n<w:LsdException Locked="false" Pr
	iority="60" Name="Light Shading Accent 3"/>\n<w:LsdException Locked="false
	" Priority="61" Name="Light List Accent 3"/>\n<w:LsdException Locked="fals
	e" Priority="62" Name="Light Grid Accent 3"/>\n<w:LsdException Locked="fal
	se" Priority="63" Name="Medium Shading 1 Accent 3"/>\n<w:LsdException Lock
	ed="false" Priority="64" Name="Medium Shading 2 Accent 3"/>\n<w:LsdExcepti
	on Locked="false" Priority="65" Name="Medium List 1 Accent 3"/>\n<w:LsdExc
	eption Locked="false" Priority="66" Name="Medium List 2 Accent 3"/>\n<w:Ls
	dException Locked="false" Priority="67" Name="Medium Grid 1 Accent 3"/>\n<
	w:LsdException Locked="false" Priority="68" Name="Medium Grid 2 Accent 3"/
	>\n<w:LsdException Locked="false" Priority="69" Name="Medium Grid 3 Accent
	 3"/>\n<w:LsdException Locked="false" Priority="70" Name="Dark List Accent
	 3"/>\n<w:LsdException Locked="false" Priority="71" Name="Colorful Shading
	 Accent 3"/>\n<w:LsdException Locked="false" Priority="72" Name="Colorful 
	List Accent 3"/>\n<w:LsdException Locked="false" Priority="73" Name="Color
	ful Grid Accent 3"/>\n<w:LsdException Locked="false" Priority="60" Name="L
	ight Shading Accent 4"/>\n<w:LsdException Locked="false" Priority="61" Nam
	e="Light List Accent 4"/>\n<w:LsdException Locked="false" Priority="62" Na
	me="Light Grid Accent 4"/>\n<w:LsdException Locked="false" Priority="63" N
	ame="Medium Shading 1 Accent 4"/>\n<w:LsdException Locked="false" Priority
	="64" Name="Medium Shading 2 Accent 4"/>\n<w:LsdException Locked="false" P
	riority="65" Name="Medium List 1 Accent 4"/>\n<w:LsdException Locked="fals
	e" Priority="66" Name="Medium List 2 Accent 4"/>\n<w:LsdException Locked="
	false" Priority="67" Name="Medium Grid 1 Accent 4"/>\n<w:LsdException Lock
	ed="false" Priority="68" Name="Medium Grid 2 Accent 4"/>\n<w:LsdException 
	Locked="false" Priority="69" Name="Medium Grid 3 Accent 4"/>\n<w:LsdExcept
	ion Locked="false" Priority="70" Name="Dark List Accent 4"/>\n<w:LsdExcept
	ion Locked="false" Priority="71" Name="Colorful Shading Accent 4"/>\n<w:Ls
	dException Locked="false" Priority="72" Name="Colorful List Accent 4"/>\n<
	w:LsdException Locked="false" Priority="73" Name="Colorful Grid Accent 4"/
	>\n<w:LsdException Locked="false" Priority="60" Name="Light Shading Accent
	 5"/>\n<w:LsdException Locked="false" Priority="61" Name="Light List Accen
	t 5"/>\n<w:LsdException Locked="false" Priority="62" Name="Light Grid Acce
	nt 5"/>\n<w:LsdException Locked="false" Priority="63" Name="Medium Shading
	 1 Accent 5"/>\n<w:LsdException Locked="false" Priority="64" Name="Medium 
	Shading 2 Accent 5"/>\n<w:LsdException Locked="false" Priority="65" Name="
	Medium List 1 Accent 5"/>\n<w:LsdException Locked="false" Priority="66" Na
	me="Medium List 2 Accent 5"/>\n<w:LsdException Locked="false" Priority="67
	" Name="Medium Grid 1 Accent 5"/>\n<w:LsdException Locked="false" Priority
	="68" Name="Medium Grid 2 Accent 5"/>\n<w:LsdException Locked="false" Prio
	rity="69" Name="Medium Grid 3 Accent 5"/>\n<w:LsdException Locked="false" 
	Priority="70" Name="Dark List Accent 5"/>\n<w:LsdException Locked="false" 
	Priority="71" Name="Colorful Shading Accent 5"/>\n<w:LsdException Locked="
	false" Priority="72" Name="Colorful List Accent 5"/>\n<w:LsdException Lock
	ed="false" Priority="73" Name="Colorful Grid Accent 5"/>\n<w:LsdException 
	Locked="false" Priority="60" Name="Light Shading Accent 6"/>\n<w:LsdExcept
	ion Locked="false" Priority="61" Name="Light List Accent 6"/>\n<w:LsdExcep
	tion Locked="false" Priority="62" Name="Light Grid Accent 6"/>\n<w:LsdExce
	ption Locked="false" Priority="63" Name="Medium Shading 1 Accent 6"/>\n<w:
	LsdException Locked="false" Priority="64" Name="Medium Shading 2 Accent 6"
	/>\n<w:LsdException Locked="false" Priority="65" Name="Medium List 1 Accen
	t 6"/>\n<w:LsdException Locked="false" Priority="66" Name="Medium List 2 A
	ccent 6"/>\n<w:LsdException Locked="false" Priority="67" Name="Medium Grid
	 1 Accent 6"/>\n<w:LsdException Locked="false" Priority="68" Name="Medium 
	Grid 2 Accent 6"/>\n<w:LsdException Locked="false" Priority="69" Name="Med
	ium Grid 3 Accent 6"/>\n<w:LsdException Locked="false" Priority="70" Name=
	"Dark List Accent 6"/>\n<w:LsdException Locked="false" Priority="71" Name=
	"Colorful Shading Accent 6"/>\n<w:LsdException Locked="false" Priority="72
	" Name="Colorful List Accent 6"/>\n<w:LsdException Locked="false" Priority
	="73" Name="Colorful Grid Accent 6"/>\n<w:LsdException Locked="false" Prio
	rity="19" QFormat="true" Name="Subtle Emphasis"/>\n<w:LsdException Locked=
	"false" Priority="21" QFormat="true" Name="Intense Emphasis"/>\n<w:LsdExce
	ption Locked="false" Priority="31" QFormat="true" Name="Subtle Reference"/
	>\n<w:LsdException Locked="false" Priority="32" QFormat="true" Name="Inten
	se Reference"/>\n<w:LsdException Locked="false" Priority="33" QFormat="tru
	e" Name="Book Title"/>\n<w:LsdException Locked="false" Priority="37" SemiH
	idden="true" UnhideWhenUsed="true" Name="Bibliography"/>\n<w:LsdException 
	Locked="false" Priority="39" SemiHidden="true" UnhideWhenUsed="true" QForm
	at="true" Name="TOC Heading"/>\n<w:LsdException Locked="false" Priority="4
	1" Name="Plain Table 1"/>\n<w:LsdException Locked="false" Priority="42" Na
	me="Plain Table 2"/>\n<w:LsdException Locked="false" Priority="43" Name="P
	lain Table 3"/>\n<w:LsdException Locked="false" Priority="44" Name="Plain 
	Table 4"/>\n<w:LsdException Locked="false" Priority="45" Name="Plain Table
	 5"/>\n<w:LsdException Locked="false" Priority="40" Name="Grid Table Light
	"/>\n<w:LsdException Locked="false" Priority="46" Name="Grid Table 1 Light
	"/>\n<w:LsdException Locked="false" Priority="47" Name="Grid Table 2"/>\n<
	w:LsdException Locked="false" Priority="48" Name="Grid Table 3"/>\n<w:LsdE
	xception Locked="false" Priority="49" Name="Grid Table 4"/>\n<w:LsdExcepti
	on Locked="false" Priority="50" Name="Grid Table 5 Dark"/>\n<w:LsdExceptio
	n Locked="false" Priority="51" Name="Grid Table 6 Colorful"/>\n<w:LsdExcep
	tion Locked="false" Priority="52" Name="Grid Table 7 Colorful"/>\n<w:LsdEx
	ception Locked="false" Priority="46" Name="Grid Table 1 Light Accent 1"/>\
	n<w:LsdException Locked="false" Priority="47" Name="Grid Table 2 Accent 1"
	/>\n<w:LsdException Locked="false" Priority="48" Name="Grid Table 3 Accent
	 1"/>\n<w:LsdException Locked="false" Priority="49" Name="Grid Table 4 Acc
	ent 1"/>\n<w:LsdException Locked="false" Priority="50" Name="Grid Table 5 
	Dark Accent 1"/>\n<w:LsdException Locked="false" Priority="51" Name="Grid 
	Table 6 Colorful Accent 1"/>\n<w:LsdException Locked="false" Priority="52"
	 Name="Grid Table 7 Colorful Accent 1"/>\n<w:LsdException Locked="false" P
	riority="46" Name="Grid Table 1 Light Accent 2"/>\n<w:LsdException Locked=
	"false" Priority="47" Name="Grid Table 2 Accent 2"/>\n<w:LsdException Lock
	ed="false" Priority="48" Name="Grid Table 3 Accent 2"/>\n<w:LsdException L
	ocked="false" Priority="49" Name="Grid Table 4 Accent 2"/>\n<w:LsdExceptio
	n Locked="false" Priority="50" Name="Grid Table 5 Dark Accent 2"/>\n<w:Lsd
	Exception Locked="false" Priority="51" Name="Grid Table 6 Colorful Accent 
	2"/>\n<w:LsdException Locked="false" Priority="52" Name="Grid Table 7 Colo
	rful Accent 2"/>\n<w:LsdException Locked="false" Priority="46" Name="Grid 
	Table 1 Light Accent 3"/>\n<w:LsdException Locked="false" Priority="47" Na
	me="Grid Table 2 Accent 3"/>\n<w:LsdException Locked="false" Priority="48"
	 Name="Grid Table 3 Accent 3"/>\n<w:LsdException Locked="false" Priority="
	49" Name="Grid Table 4 Accent 3"/>\n<w:LsdException Locked="false" Priorit
	y="50" Name="Grid Table 5 Dark Accent 3"/>\n<w:LsdException Locked="false"
	 Priority="51" Name="Grid Table 6 Colorful Accent 3"/>\n<w:LsdException Lo
	cked="false" Priority="52" Name="Grid Table 7 Colorful Accent 3"/>\n<w:Lsd
	Exception Locked="false" Priority="46" Name="Grid Table 1 Light Accent 4"/
	>\n<w:LsdException Locked="false" Priority="47" Name="Grid Table 2 Accent 
	4"/>\n<w:LsdException Locked="false" Priority="48" Name="Grid Table 3 Acce
	nt 4"/>\n<w:LsdException Locked="false" Priority="49" Name="Grid Table 4 A
	ccent 4"/>\n<w:LsdException Locked="false" Priority="50" Name="Grid Table 
	5 Dark Accent 4"/>\n<w:LsdException Locked="false" Priority="51" Name="Gri
	d Table 6 Colorful Accent 4"/>\n<w:LsdException Locked="false" Priority="5
	2" Name="Grid Table 7 Colorful Accent 4"/>\n<w:LsdException Locked="false"
	 Priority="46" Name="Grid Table 1 Light Accent 5"/>\n<w:LsdException Locke
	d="false" Priority="47" Name="Grid Table 2 Accent 5"/>\n<w:LsdException Lo
	cked="false" Priority="48" Name="Grid Table 3 Accent 5"/>\n<w:LsdException
	 Locked="false" Priority="49" Name="Grid Table 4 Accent 5"/>\n<w:LsdExcept
	ion Locked="false" Priority="50" Name="Grid Table 5 Dark Accent 5"/>\n<w:L
	sdException Locked="false" Priority="51" Name="Grid Table 6 Colorful Accen
	t 5"/>\n<w:LsdException Locked="false" Priority="52" Name="Grid Table 7 Co
	lorful Accent 5"/>\n<w:LsdException Locked="false" Priority="46" Name="Gri
	d Table 1 Light Accent 6"/>\n<w:LsdException Locked="false" Priority="47" 
	Name="Grid Table 2 Accent 6"/>\n<w:LsdException Locked="false" Priority="4
	8" Name="Grid Table 3 Accent 6"/>\n<w:LsdException Locked="false" Priority
	="49" Name="Grid Table 4 Accent 6"/>\n<w:LsdException Locked="false" Prior
	ity="50" Name="Grid Table 5 Dark Accent 6"/>\n<w:LsdException Locked="fals
	e" Priority="51" Name="Grid Table 6 Colorful Accent 6"/>\n<w:LsdException 
	Locked="false" Priority="52" Name="Grid Table 7 Colorful Accent 6"/>\n<w:L
	sdException Locked="false" Priority="46" Name="List Table 1 Light"/>\n<w:L
	sdException Locked="false" Priority="47" Name="List Table 2"/>\n<w:LsdExce
	ption Locked="false" Priority="48" Name="List Table 3"/>\n<w:LsdException 
	Locked="false" Priority="49" Name="List Table 4"/>\n<w:LsdException Locked
	="false" Priority="50" Name="List Table 5 Dark"/>\n<w:LsdException Locked=
	"false" Priority="51" Name="List Table 6 Colorful"/>\n<w:LsdException Lock
	ed="false" Priority="52" Name="List Table 7 Colorful"/>\n<w:LsdException L
	ocked="false" Priority="46" Name="List Table 1 Light Accent 1"/>\n<w:LsdEx
	ception Locked="false" Priority="47" Name="List Table 2 Accent 1"/>\n<w:Ls
	dException Locked="false" Priority="48" Name="List Table 3 Accent 1"/>\n<w
	:LsdException Locked="false" Priority="49" Name="List Table 4 Accent 1"/>\
	n<w:LsdException Locked="false" Priority="50" Name="List Table 5 Dark Acce
	nt 1"/>\n<w:LsdException Locked="false" Priority="51" Name="List Table 6 C
	olorful Accent 1"/>\n<w:LsdException Locked="false" Priority="52" Name="Li
	st Table 7 Colorful Accent 1"/>\n<w:LsdException Locked="false" Priority="
	46" Name="List Table 1 Light Accent 2"/>\n<w:LsdException Locked="false" P
	riority="47" Name="List Table 2 Accent 2"/>\n<w:LsdException Locked="false
	" Priority="48" Name="List Table 3 Accent 2"/>\n<w:LsdException Locked="fa
	lse" Priority="49" Name="List Table 4 Accent 2"/>\n<w:LsdException Locked=
	"false" Priority="50" Name="List Table 5 Dark Accent 2"/>\n<w:LsdException
	 Locked="false" Priority="51" Name="List Table 6 Colorful Accent 2"/>\n<w:
	LsdException Locked="false" Priority="52" Name="List Table 7 Colorful Acce
	nt 2"/>\n<w:LsdException Locked="false" Priority="46" Name="List Table 1 L
	ight Accent 3"/>\n<w:LsdException Locked="false" Priority="47" Name="List 
	Table 2 Accent 3"/>\n<w:LsdException Locked="false" Priority="48" Name="Li
	st Table 3 Accent 3"/>\n<w:LsdException Locked="false" Priority="49" Name=
	"List Table 4 Accent 3"/>\n<w:LsdException Locked="false" Priority="50" Na
	me="List Table 5 Dark Accent 3"/>\n<w:LsdException Locked="false" Priority
	="51" Name="List Table 6 Colorful Accent 3"/>\n<w:LsdException Locked="fal
	se" Priority="52" Name="List Table 7 Colorful Accent 3"/>\n<w:LsdException
	 Locked="false" Priority="46" Name="List Table 1 Light Accent 4"/>\n<w:Lsd
	Exception Locked="false" Priority="47" Name="List Table 2 Accent 4"/>\n<w:
	LsdException Locked="false" Priority="48" Name="List Table 3 Accent 4"/>\n
	<w:LsdException Locked="false" Priority="49" Name="List Table 4 Accent 4"/
	>\n<w:LsdException Locked="false" Priority="50" Name="List Table 5 Dark Ac
	cent 4"/>\n<w:LsdException Locked="false" Priority="51" Name="List Table 6
	 Colorful Accent 4"/>\n<w:LsdException Locked="false" Priority="52" Name="
	List Table 7 Colorful Accent 4"/>\n<w:LsdException Locked="false" Priority
	="46" Name="List Table 1 Light Accent 5"/>\n<w:LsdException Locked="false"
	 Priority="47" Name="List Table 2 Accent 5"/>\n<w:LsdException Locked="fal
	se" Priority="48" Name="List Table 3 Accent 5"/>\n<w:LsdException Locked="
	false" Priority="49" Name="List Table 4 Accent 5"/>\n<w:LsdException Locke
	d="false" Priority="50" Name="List Table 5 Dark Accent 5"/>\n<w:LsdExcepti
	on Locked="false" Priority="51" Name="List Table 6 Colorful Accent 5"/>\n<
	w:LsdException Locked="false" Priority="52" Name="List Table 7 Colorful Ac
	cent 5"/>\n<w:LsdException Locked="false" Priority="46" Name="List Table 1
	 Light Accent 6"/>\n<w:LsdException Locked="false" Priority="47" Name="Lis
	t Table 2 Accent 6"/>\n<w:LsdException Locked="false" Priority="48" Name="
	List Table 3 Accent 6"/>\n<w:LsdException Locked="false" Priority="49" Nam
	e="List Table 4 Accent 6"/>\n<w:LsdException Locked="false" Priority="50" 
	Name="List Table 5 Dark Accent 6"/>\n<w:LsdException Locked="false" Priori
	ty="51" Name="List Table 6 Colorful Accent 6"/>\n<w:LsdException Locked="f
	alse" Priority="52" Name="List Table 7 Colorful Accent 6"/>\n<w:LsdExcepti
	on Locked="false" SemiHidden="true" UnhideWhenUsed="true" Name="Mention"/>
	\n<w:LsdException Locked="false" SemiHidden="true" UnhideWhenUsed="true" N
	ame="Smart Hyperlink"/>\n<w:LsdException Locked="false" SemiHidden="true" 
	UnhideWhenUsed="true" Name="Hashtag"/>\n<w:LsdException Locked="false" Sem
	iHidden="true" UnhideWhenUsed="true" Name="Unresolved Mention"/>\n<w:LsdEx
	ception Locked="false" SemiHidden="true" UnhideWhenUsed="true" Name="Smart
	 Link"/>\n</w:LatentStyles>\n</xml><![endif]--><style><!--\n/* Font Defini
	tions */\n@font-face\n	{font-family:"Cambria Math"\;\n	panose-1:2 4 5 3 5 
	4 6 3 2 4\;\n	mso-font-charset:0\;\n	mso-generic-font-family:roman\;\n	mso
	-font-pitch:variable\;\n	mso-font-signature:-536869121 1107305727 33554432
	 0 415 0\;}\n@font-face\n	{font-family:DengXian\;\n	panose-1:2 1 6 0 3 1 1
	 1 1 1\;\n	mso-font-alt:\\7B49\\7EBF\;\n	mso-font-charset:134\;\n	mso-gene
	ric-font-family:auto\;\n	mso-font-pitch:variable\;\n	mso-font-signature:-1
	610612033 953122042 22 0 262159 0\;}\n@font-face\n	{font-family:Calibri\;\
	n	panose-1:2 15 5 2 2 2 4 3 2 4\;\n	mso-font-charset:0\;\n	mso-generic-fon
	t-family:swiss\;\n	mso-font-pitch:variable\;\n	mso-font-signature:-4697500
	17 -1040178053 9 0 511 0\;}\n@font-face\n	{font-family:"Segoe UI"\;\n	pano
	se-1:2 11 5 2 4 2 4 2 2 3\;\n	mso-font-charset:0\;\n	mso-generic-font-fami
	ly:swiss\;\n	mso-font-pitch:variable\;\n	mso-font-signature:-469750017 -10
	73683329 9 0 511 0\;}\n@font-face\n	{font-family:"Microsoft JhengHei"\;\n	
	panose-1:2 11 6 4 3 5 4 4 2 4\;\n	mso-font-charset:136\;\n	mso-generic-fon
	t-family:swiss\;\n	mso-font-pitch:variable\;\n	mso-font-signature:679 6846
	72000 22 0 1048585 0\;}\n@font-face\n	{font-family:"\\@Microsoft JhengHei"
	\;\n	mso-font-charset:136\;\n	mso-generic-font-family:swiss\;\n	mso-font-p
	itch:variable\;\n	mso-font-signature:679 684672000 22 0 1048585 0\;}\n@fon
	t-face\n	{font-family:"Segoe UI Semibold"\;\n	panose-1:2 11 7 2 4 2 4 2 2 
	3\;\n	mso-font-charset:0\;\n	mso-generic-font-family:swiss\;\n	mso-font-pi
	tch:variable\;\n	mso-font-signature:-469750017 -1073683329 9 0 511 0\;}\n@
	font-face\n	{font-family:"\\@DengXian"\;\n	panose-1:2 1 6 0 3 1 1 1 1 1\;\
	n	mso-font-charset:134\;\n	mso-generic-font-family:auto\;\n	mso-font-pitch
	:variable\;\n	mso-font-signature:-1610612033 953122042 22 0 262159 0\;}\n/
	* Style Definitions */\np.MsoNormal\, li.MsoNormal\, div.MsoNormal\n	{mso-
	style-unhide:no\;\n	mso-style-qformat:yes\;\n	mso-style-parent:""\;\n	marg
	in:0in\;\n	mso-pagination:widow-orphan\;\n	font-size:11.0pt\;\n	font-famil
	y:"Calibri"\,sans-serif\;\n	mso-ascii-font-family:Calibri\;\n	mso-fareast-
	font-family:DengXian\;\n	mso-hansi-font-family:Calibri\;\n	mso-bidi-font-f
	amily:"Times New Roman"\;}\na:link\, span.MsoHyperlink\n	{mso-style-noshow
	:yes\;\n	mso-style-priority:99\;\n	color:#0563C1\;\n	text-decoration:under
	line\;\n	text-underline:single\;}\na:visited\, span.MsoHyperlinkFollowed\n
		{mso-style-noshow:yes\;\n	mso-style-priority:99\;\n	color:#954F72\;\n	tex
	t-decoration:underline\;\n	text-underline:single\;}\nspan.EmailStyle17\n	{
	mso-style-type:personal-compose\;\n	mso-style-noshow:yes\;\n	mso-style-unh
	ide:no\;\n	mso-ansi-font-size:11.0pt\;\n	mso-bidi-font-size:11.0pt\;\n	fon
	t-family:"Calibri"\,sans-serif\;\n	mso-ascii-font-family:Calibri\;\n	mso-f
	areast-font-family:DengXian\;\n	mso-hansi-font-family:Calibri\;\n	mso-bidi
	-font-family:"Times New Roman"\;\n	color:windowtext\;}\nspan.SpellE\n	{mso
	-style-name:""\;\n	mso-spl-e:yes\;}\nspan.GramE\n	{mso-style-name:""\;\n	m
	so-gram-e:yes\;}\n.MsoChpDefault\n	{mso-style-type:export-only\;\n	mso-def
	ault-props:yes\;\n	font-family:"Calibri"\,sans-serif\;\n	mso-ascii-font-fa
	mily:Calibri\;\n	mso-fareast-font-family:DengXian\;\n	mso-hansi-font-famil
	y:Calibri\;\n	mso-bidi-font-family:"Times New Roman"\;}\n@page WordSection
	1\n	{size:8.5in 11.0in\;\n	margin:1.0in 1.0in 1.0in 1.0in\;\n	mso-header-m
	argin:.5in\;\n	mso-footer-margin:.5in\;\n	mso-paper-source:0\;}\ndiv.WordS
	ection1\n	{page:WordSection1\;}\n--></style><!--[if gte mso 10]><style>/* 
	Style Definitions */\ntable.MsoNormalTable\n	{mso-style-name:"Table Normal
	"\;\n	mso-tstyle-rowband-size:0\;\n	mso-tstyle-colband-size:0\;\n	mso-styl
	e-noshow:yes\;\n	mso-style-priority:99\;\n	mso-style-parent:""\;\n	mso-pad
	ding-alt:0in 5.4pt 0in 5.4pt\;\n	mso-para-margin:0in\;\n	mso-pagination:wi
	dow-orphan\;\n	font-size:11.0pt\;\n	font-family:"Calibri"\,sans-serif\;\n	
	mso-ascii-font-family:Calibri\;\n	mso-hansi-font-family:Calibri\;\n	mso-bi
	di-font-family:"Times New Roman"\;}\n</style><![endif]--><!--[if gte mso 9
	]><xml>\n<o:shapedefaults v:ext="edit" spidmax="1026" />\n</xml><![endif]-
	-><!--[if gte mso 9]><xml>\n<o:shapelayout v:ext="edit">\n<o:idmap v:ext="
	edit" data="1" />\n</o:shapelayout></xml><![endif]--></head><body lang=EN-
	US link="#0563C1" vlink="#954F72" style='tab-interval:.5in\;word-wrap:brea
	k-word'><div class=WordSection1><p class=MsoNormal><o:p>&nbsp\;</o:p></p><
	div><p class=MsoNormal><span style='mso-fareast-font-family:"Times New Rom
	an"\;color:#5F5F5F'>______________________________________________________
	__________________________</span><span style='mso-fareast-font-family:"Tim
	es New Roman"'> <o:p></o:p></span></p></div><div><div style='margin-top:.2
	5in\;margin-bottom:15.0pt'><p class=MsoNormal><span style='font-size:18.0p
	t\;font-family:"Segoe UI"\,sans-serif\;mso-fareast-font-family:"Times New 
	Roman"\;color:#252424'>Microsoft Teams meeting</span><span style='font-fam
	ily:"Segoe UI"\,sans-serif\;mso-fareast-font-family:"Times New Roman"\;col
	or:#252424'> <o:p></o:p></span></p></div><div style='margin-bottom:15.0pt'
	><div><p class=MsoNormal><b><span style='font-size:10.5pt\;font-family:"Se
	goe UI"\,sans-serif\;mso-fareast-font-family:"Times New Roman"\;color:#252
	424'>Join on your computer\, mobile app or room <span class=GramE>device</
	span></span></b><b><span style='font-family:"Segoe UI"\,sans-serif\;mso-fa
	reast-font-family:"Times New Roman"\;color:#252424'> <o:p></o:p></span></b
	></p></div><p class=MsoNormal><span style='font-family:"Segoe UI"\,sans-se
	rif\;mso-fareast-font-family:"Times New Roman"\;color:#252424'><a href="ht
	tps://teams.microsoft.com/l/meetup-join/19%3ameeting_YTk4ZDU3YjItODkxZC00M
	TdmLTlkZmUtYThkNGQ0ZWYyMDZh%40thread.v2/0?context=%7b%22Tid%22%3a%2246c98d
	88-e344-4ed4-8496-4ed7712e255d%22%2c%22Oid%22%3a%2255d36a50-78be-4ced-bc27
	-3d06c576cc19%22%7d" target="_blank"><span style='font-size:10.5pt\;font-f
	amily:"Segoe UI Semibold"\,sans-serif\;color:#6264A7'>Click here to join t
	he meeting</span></a> <o:p></o:p></span></p></div><div style='margin-top:1
	5.0pt\;margin-bottom:15.0pt'><div style='margin-bottom:3.0pt'><p class=Mso
	Normal><span style='font-size:10.5pt\;font-family:"Segoe UI"\,sans-serif\;
	mso-fareast-font-family:"Times New Roman"\;color:#252424'>Meeting ID: </sp
	an><span style='font-size:12.0pt\;font-family:"Segoe UI"\,sans-serif\;mso-
	fareast-font-family:"Times New Roman"\;color:#252424'>256 188 860 359</spa
	n><span style='font-size:10.5pt\;font-family:"Segoe UI"\,sans-serif\;mso-f
	areast-font-family:"Times New Roman"\;color:#252424'> </span><span style='
	font-family:"Segoe UI"\,sans-serif\;mso-fareast-font-family:"Times New Rom
	an"\;color:#252424'><br></span><span style='font-size:10.5pt\;font-family:
	"Segoe UI"\,sans-serif\;mso-fareast-font-family:"Times New Roman"\;color:#
	252424'>Passcode: </span><span class=SpellE><span style='font-size:12.0pt\
	;font-family:"Segoe UI"\,sans-serif\;mso-fareast-font-family:"Times New Ro
	man"\;color:#252424'>yJZsmm</span></span><span style='font-size:12.0pt\;fo
	nt-family:"Segoe UI"\,sans-serif\;mso-fareast-font-family:"Times New Roman
	"\;color:#252424'> </span><span style='font-family:"Segoe UI"\,sans-serif\
	;mso-fareast-font-family:"Times New Roman"\;color:#252424'><o:p></o:p></sp
	an></p><div><p class=MsoNormal><span style='font-size:10.5pt\;font-family:
	"Segoe UI"\,sans-serif\;mso-fareast-font-family:"Times New Roman"\;color:#
	252424'><a href="https://www.microsoft.com/en-us/microsoft-teams/download-
	app" target="_blank"><span style='color:#6264A7'>Download Teams</span></a>
	 | <a href="https://www.microsoft.com/microsoft-teams/join-a-meeting" targ
	et="_blank"><span style='color:#6264A7'>Join on the web</span></a><o:p></o
	:p></span></p></div></div></div><div style='margin-bottom:3.0pt'><p class=
	MsoNormal><b><span style='font-size:10.5pt\;font-family:"Segoe UI"\,sans-s
	erif\;mso-fareast-font-family:"Times New Roman"\;color:#252424'>Join with 
	a video conferencing <span class=GramE>device</span></span></b><span style
	='font-family:"Segoe UI"\,sans-serif\;mso-fareast-font-family:"Times New R
	oman"\;color:#252424'> <o:p></o:p></span></p></div><div><p class=MsoNormal
	><span style='font-size:10.5pt\;font-family:"Segoe UI"\,sans-serif\;mso-fa
	reast-font-family:"Times New Roman"\;color:#252424'>teams@conf.intel.com <
	o:p></o:p></span></p></div><div><p class=MsoNormal><span style='font-size:
	10.5pt\;font-family:"Segoe UI"\,sans-serif\;mso-fareast-font-family:"Times
	 New Roman"\;color:#252424'>Video Conference ID: </span><span style='font-
	size:12.0pt\;font-family:"Segoe UI"\,sans-serif\;mso-fareast-font-family:"
	Times New Roman"\;color:#252424'>113 587 139 9 </span><span style='font-fa
	mily:"Segoe UI"\,sans-serif\;mso-fareast-font-family:"Times New Roman"\;co
	lor:#252424'><o:p></o:p></span></p></div><div style='margin-bottom:15.0pt'
	><p class=MsoNormal><span style='font-size:10.5pt\;font-family:"Segoe UI"\
	,sans-serif\;mso-fareast-font-family:"Times New Roman"\;color:#252424'><a 
	href="https://conf.intel.com/teams/?conf=1135871399&amp\;ivr=teams&amp\;d=
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^ permalink raw reply	[flat|nested] 26+ messages in thread

* Re: [edk2-devel] [PATCH v1 1/1] ArmPkg: CpuDxe: Sync GCD Capabilities With Page Table Attributes
  2023-05-09  1:35             ` Ni, Ray
@ 2023-05-09  2:03               ` Oliver Smith-Denny
  2023-05-09  2:04                 ` Michael D Kinney
  0 siblings, 1 reply; 26+ messages in thread
From: Oliver Smith-Denny @ 2023-05-09  2:03 UTC (permalink / raw)
  To: Ni, Ray, Kinney, Michael D, Ard Biesheuvel, devel@edk2.groups.io
  Cc: Leif Lindholm, Ard Biesheuvel, Sami Mujawar, Michael Kubacki,
	Sean Brogan

Hi Ray,

Thanks for setting up a meeting on this! We have some
conflicts on our side for this week, does it work
for everyone to have it the following Thursday
(May 18th)?

The time works for us.

Thanks,
Oliver

On 5/8/2023 6:35 PM, Ni, Ray wrote:
> All,
> Can you check if the meeting time is ok for you?
> 
> It will be in this week:
> * PDT Thursday 07:00
> * Paris Thursday 16:00
> * Shanghai Thursday 22:00
> 
> Thanks,
> Ray
> 
> 
>> -----Original Message-----
>> From: Kinney, Michael D <michael.d.kinney@intel.com>
>> Sent: Tuesday, May 2, 2023 1:59 AM
>> To: Oliver Smith-Denny <osde@linux.microsoft.com>; Ard Biesheuvel
>> <ardb@kernel.org>; devel@edk2.groups.io
>> Cc: Ni, Ray <ray.ni@intel.com>; Leif Lindholm <quic_llindhol@quicinc.com>;
>> Ard Biesheuvel <ardb+tianocore@kernel.org>; Sami Mujawar
>> <sami.mujawar@arm.com>; Michael Kubacki
>> <mikuback@linux.microsoft.com>; Sean Brogan
>> <sean.brogan@microsoft.com>; Kinney, Michael D
>> <michael.d.kinney@intel.com>
>> Subject: RE: [edk2-devel] [PATCH v1 1/1] ArmPkg: CpuDxe: Sync GCD
>> Capabilities With Page Table Attributes
>>
>> Thanks for the quick feedback.  Ray is out this week.  I will work with Ray to
>> arrange a time slot, hopefully next week that works for everyone.
>>
>> Mike
>>
>>> -----Original Message-----
>>> From: Oliver Smith-Denny <osde@linux.microsoft.com>
>>> Sent: Monday, May 1, 2023 10:53 AM
>>> To: Ard Biesheuvel <ardb@kernel.org>; devel@edk2.groups.io; Kinney,
>>> Michael D <michael.d.kinney@intel.com>
>>> Cc: Ni, Ray <ray.ni@intel.com>; Leif Lindholm <quic_llindhol@quicinc.com>;
>>> Ard Biesheuvel <ardb+tianocore@kernel.org>; Sami Mujawar
>>> <sami.mujawar@arm.com>; Michael Kubacki
>>> <mikuback@linux.microsoft.com>; Sean Brogan
>>> <sean.brogan@microsoft.com>
>>> Subject: Re: [edk2-devel] [PATCH v1 1/1] ArmPkg: CpuDxe: Sync GCD
>>> Capabilities With Page Table Attributes
>>>
>>> On 5/1/2023 10:50 AM, Ard Biesheuvel wrote:
>>>> On Mon, 1 May 2023 at 19:49, Michael D Kinney
>>>> <michael.d.kinney@intel.com> wrote:
>>>>>
>>>>> Hi,
>>>>>
>>>>> These UEFI Memory Map, GCD, and Page Table interactions can be
>>> complex and I
>>>>> agree there are some UEFI/PI spec clarifications that may help.
>>>>>
>>>>> Ray hosts a TianoCore design meeting when needed.  Do you think a
>>> meeting with
>>>>> an open discussion on these topics would help, or do we prefer to
>>> continue with
>>>>> email discussions?
>>>>>
>>>>
>>>> I'll gladly join a call to discuss this if we can find a timeslot that
>>>> works for everyone in terms of time zone. (I'm on Paris time)
>>>
>>> I also think a call would be great, I certainly would benefit from
>>> learning more here :). I'm sure various members of my team would
>>> be interested in joining, happy to be flexible on timeslot (we are
>>> generally in PST).
>>>
>>> Thanks,
>>> Oliver

^ permalink raw reply	[flat|nested] 26+ messages in thread

* Re: [edk2-devel] [PATCH v1 1/1] ArmPkg: CpuDxe: Sync GCD Capabilities With Page Table Attributes
  2023-05-09  2:03               ` Oliver Smith-Denny
@ 2023-05-09  2:04                 ` Michael D Kinney
  2023-05-09  6:59                   ` Ard Biesheuvel
  0 siblings, 1 reply; 26+ messages in thread
From: Michael D Kinney @ 2023-05-09  2:04 UTC (permalink / raw)
  To: Oliver Smith-Denny, Ni, Ray, Ard Biesheuvel, devel@edk2.groups.io
  Cc: Leif Lindholm, Ard Biesheuvel, Sami Mujawar, Michael Kubacki,
	Sean Brogan, Kinney, Michael D

I would prefer next week as well.

Mike

> -----Original Message-----
> From: Oliver Smith-Denny <osde@linux.microsoft.com>
> Sent: Monday, May 8, 2023 7:03 PM
> To: Ni, Ray <ray.ni@intel.com>; Kinney, Michael D
> <michael.d.kinney@intel.com>; Ard Biesheuvel <ardb@kernel.org>;
> devel@edk2.groups.io
> Cc: Leif Lindholm <quic_llindhol@quicinc.com>; Ard Biesheuvel
> <ardb+tianocore@kernel.org>; Sami Mujawar <sami.mujawar@arm.com>;
> Michael Kubacki <mikuback@linux.microsoft.com>; Sean Brogan
> <sean.brogan@microsoft.com>
> Subject: Re: [edk2-devel] [PATCH v1 1/1] ArmPkg: CpuDxe: Sync GCD
> Capabilities With Page Table Attributes
> 
> Hi Ray,
> 
> Thanks for setting up a meeting on this! We have some
> conflicts on our side for this week, does it work
> for everyone to have it the following Thursday
> (May 18th)?
> 
> The time works for us.
> 
> Thanks,
> Oliver
> 
> On 5/8/2023 6:35 PM, Ni, Ray wrote:
> > All,
> > Can you check if the meeting time is ok for you?
> >
> > It will be in this week:
> > * PDT Thursday 07:00
> > * Paris Thursday 16:00
> > * Shanghai Thursday 22:00
> >
> > Thanks,
> > Ray
> >
> >
> >> -----Original Message-----
> >> From: Kinney, Michael D <michael.d.kinney@intel.com>
> >> Sent: Tuesday, May 2, 2023 1:59 AM
> >> To: Oliver Smith-Denny <osde@linux.microsoft.com>; Ard Biesheuvel
> >> <ardb@kernel.org>; devel@edk2.groups.io
> >> Cc: Ni, Ray <ray.ni@intel.com>; Leif Lindholm
> <quic_llindhol@quicinc.com>;
> >> Ard Biesheuvel <ardb+tianocore@kernel.org>; Sami Mujawar
> >> <sami.mujawar@arm.com>; Michael Kubacki
> >> <mikuback@linux.microsoft.com>; Sean Brogan
> >> <sean.brogan@microsoft.com>; Kinney, Michael D
> >> <michael.d.kinney@intel.com>
> >> Subject: RE: [edk2-devel] [PATCH v1 1/1] ArmPkg: CpuDxe: Sync GCD
> >> Capabilities With Page Table Attributes
> >>
> >> Thanks for the quick feedback.  Ray is out this week.  I will work with Ray to
> >> arrange a time slot, hopefully next week that works for everyone.
> >>
> >> Mike
> >>
> >>> -----Original Message-----
> >>> From: Oliver Smith-Denny <osde@linux.microsoft.com>
> >>> Sent: Monday, May 1, 2023 10:53 AM
> >>> To: Ard Biesheuvel <ardb@kernel.org>; devel@edk2.groups.io; Kinney,
> >>> Michael D <michael.d.kinney@intel.com>
> >>> Cc: Ni, Ray <ray.ni@intel.com>; Leif Lindholm
> <quic_llindhol@quicinc.com>;
> >>> Ard Biesheuvel <ardb+tianocore@kernel.org>; Sami Mujawar
> >>> <sami.mujawar@arm.com>; Michael Kubacki
> >>> <mikuback@linux.microsoft.com>; Sean Brogan
> >>> <sean.brogan@microsoft.com>
> >>> Subject: Re: [edk2-devel] [PATCH v1 1/1] ArmPkg: CpuDxe: Sync GCD
> >>> Capabilities With Page Table Attributes
> >>>
> >>> On 5/1/2023 10:50 AM, Ard Biesheuvel wrote:
> >>>> On Mon, 1 May 2023 at 19:49, Michael D Kinney
> >>>> <michael.d.kinney@intel.com> wrote:
> >>>>>
> >>>>> Hi,
> >>>>>
> >>>>> These UEFI Memory Map, GCD, and Page Table interactions can be
> >>> complex and I
> >>>>> agree there are some UEFI/PI spec clarifications that may help.
> >>>>>
> >>>>> Ray hosts a TianoCore design meeting when needed.  Do you think a
> >>> meeting with
> >>>>> an open discussion on these topics would help, or do we prefer to
> >>> continue with
> >>>>> email discussions?
> >>>>>
> >>>>
> >>>> I'll gladly join a call to discuss this if we can find a timeslot that
> >>>> works for everyone in terms of time zone. (I'm on Paris time)
> >>>
> >>> I also think a call would be great, I certainly would benefit from
> >>> learning more here :). I'm sure various members of my team would
> >>> be interested in joining, happy to be flexible on timeslot (we are
> >>> generally in PST).
> >>>
> >>> Thanks,
> >>> Oliver

^ permalink raw reply	[flat|nested] 26+ messages in thread

* Re: [edk2-devel] [PATCH v1 1/1] ArmPkg: CpuDxe: Sync GCD Capabilities With Page Table Attributes
  2023-05-09  2:04                 ` Michael D Kinney
@ 2023-05-09  6:59                   ` Ard Biesheuvel
  2023-05-09 14:59                     ` Oliver Smith-Denny
  0 siblings, 1 reply; 26+ messages in thread
From: Ard Biesheuvel @ 2023-05-09  6:59 UTC (permalink / raw)
  To: Kinney, Michael D
  Cc: Oliver Smith-Denny, Ni, Ray, devel@edk2.groups.io, Leif Lindholm,
	Ard Biesheuvel, Sami Mujawar, Michael Kubacki, Sean Brogan

On Tue, 9 May 2023 at 04:04, Kinney, Michael D
<michael.d.kinney@intel.com> wrote:
>
> I would prefer next week as well.
>
> Mike
>

Next week, i can only do Wednesday. The week after (22-26), the time
slot works for me on any day of the week.

-- 
Ard.


> > -----Original Message-----
> > From: Oliver Smith-Denny <osde@linux.microsoft.com>
> > Sent: Monday, May 8, 2023 7:03 PM
> > To: Ni, Ray <ray.ni@intel.com>; Kinney, Michael D
> > <michael.d.kinney@intel.com>; Ard Biesheuvel <ardb@kernel.org>;
> > devel@edk2.groups.io
> > Cc: Leif Lindholm <quic_llindhol@quicinc.com>; Ard Biesheuvel
> > <ardb+tianocore@kernel.org>; Sami Mujawar <sami.mujawar@arm.com>;
> > Michael Kubacki <mikuback@linux.microsoft.com>; Sean Brogan
> > <sean.brogan@microsoft.com>
> > Subject: Re: [edk2-devel] [PATCH v1 1/1] ArmPkg: CpuDxe: Sync GCD
> > Capabilities With Page Table Attributes
> >
> > Hi Ray,
> >
> > Thanks for setting up a meeting on this! We have some
> > conflicts on our side for this week, does it work
> > for everyone to have it the following Thursday
> > (May 18th)?
> >
> > The time works for us.
> >
> > Thanks,
> > Oliver
> >
> > On 5/8/2023 6:35 PM, Ni, Ray wrote:
> > > All,
> > > Can you check if the meeting time is ok for you?
> > >
> > > It will be in this week:
> > > * PDT Thursday 07:00
> > > * Paris Thursday 16:00
> > > * Shanghai Thursday 22:00
> > >
> > > Thanks,
> > > Ray
> > >
> > >
> > >> -----Original Message-----
> > >> From: Kinney, Michael D <michael.d.kinney@intel.com>
> > >> Sent: Tuesday, May 2, 2023 1:59 AM
> > >> To: Oliver Smith-Denny <osde@linux.microsoft.com>; Ard Biesheuvel
> > >> <ardb@kernel.org>; devel@edk2.groups.io
> > >> Cc: Ni, Ray <ray.ni@intel.com>; Leif Lindholm
> > <quic_llindhol@quicinc.com>;
> > >> Ard Biesheuvel <ardb+tianocore@kernel.org>; Sami Mujawar
> > >> <sami.mujawar@arm.com>; Michael Kubacki
> > >> <mikuback@linux.microsoft.com>; Sean Brogan
> > >> <sean.brogan@microsoft.com>; Kinney, Michael D
> > >> <michael.d.kinney@intel.com>
> > >> Subject: RE: [edk2-devel] [PATCH v1 1/1] ArmPkg: CpuDxe: Sync GCD
> > >> Capabilities With Page Table Attributes
> > >>
> > >> Thanks for the quick feedback.  Ray is out this week.  I will work with Ray to
> > >> arrange a time slot, hopefully next week that works for everyone.
> > >>
> > >> Mike
> > >>
> > >>> -----Original Message-----
> > >>> From: Oliver Smith-Denny <osde@linux.microsoft.com>
> > >>> Sent: Monday, May 1, 2023 10:53 AM
> > >>> To: Ard Biesheuvel <ardb@kernel.org>; devel@edk2.groups.io; Kinney,
> > >>> Michael D <michael.d.kinney@intel.com>
> > >>> Cc: Ni, Ray <ray.ni@intel.com>; Leif Lindholm
> > <quic_llindhol@quicinc.com>;
> > >>> Ard Biesheuvel <ardb+tianocore@kernel.org>; Sami Mujawar
> > >>> <sami.mujawar@arm.com>; Michael Kubacki
> > >>> <mikuback@linux.microsoft.com>; Sean Brogan
> > >>> <sean.brogan@microsoft.com>
> > >>> Subject: Re: [edk2-devel] [PATCH v1 1/1] ArmPkg: CpuDxe: Sync GCD
> > >>> Capabilities With Page Table Attributes
> > >>>
> > >>> On 5/1/2023 10:50 AM, Ard Biesheuvel wrote:
> > >>>> On Mon, 1 May 2023 at 19:49, Michael D Kinney
> > >>>> <michael.d.kinney@intel.com> wrote:
> > >>>>>
> > >>>>> Hi,
> > >>>>>
> > >>>>> These UEFI Memory Map, GCD, and Page Table interactions can be
> > >>> complex and I
> > >>>>> agree there are some UEFI/PI spec clarifications that may help.
> > >>>>>
> > >>>>> Ray hosts a TianoCore design meeting when needed.  Do you think a
> > >>> meeting with
> > >>>>> an open discussion on these topics would help, or do we prefer to
> > >>> continue with
> > >>>>> email discussions?
> > >>>>>
> > >>>>
> > >>>> I'll gladly join a call to discuss this if we can find a timeslot that
> > >>>> works for everyone in terms of time zone. (I'm on Paris time)
> > >>>
> > >>> I also think a call would be great, I certainly would benefit from
> > >>> learning more here :). I'm sure various members of my team would
> > >>> be interested in joining, happy to be flexible on timeslot (we are
> > >>> generally in PST).
> > >>>
> > >>> Thanks,
> > >>> Oliver

^ permalink raw reply	[flat|nested] 26+ messages in thread

* Re: [edk2-devel] [PATCH v1 1/1] ArmPkg: CpuDxe: Sync GCD Capabilities With Page Table Attributes
  2023-05-09  6:59                   ` Ard Biesheuvel
@ 2023-05-09 14:59                     ` Oliver Smith-Denny
  2023-05-10 16:10                       ` Taylor Beebe
  0 siblings, 1 reply; 26+ messages in thread
From: Oliver Smith-Denny @ 2023-05-09 14:59 UTC (permalink / raw)
  To: Ard Biesheuvel, Kinney, Michael D
  Cc: Ni, Ray, devel@edk2.groups.io, Leif Lindholm, Ard Biesheuvel,
	Sami Mujawar, Michael Kubacki, Sean Brogan

On 5/8/2023 11:59 PM, Ard Biesheuvel wrote:
> On Tue, 9 May 2023 at 04:04, Kinney, Michael D
> <michael.d.kinney@intel.com> wrote:
>>
>> I would prefer next week as well.
>>
>> Mike
>>
> 
> Next week, i can only do Wednesday. The week after (22-26), the time
> slot works for me on any day of the week.
> 

Weds works from our side, the week after also works perfectly well
any day. Thanks for the flexibility and willingness to meet.

For reference for this specific patch, this bz may help cache in
some info: https://bugzilla.tianocore.org/show_bug.cgi?id=753. The
mail links are largely dead, of course, but can be found on other
mailing list retention sites (maybe in the future we will have PRs
and discussions to reference :).

Thanks,
Oliver

^ permalink raw reply	[flat|nested] 26+ messages in thread

* Re: [edk2-devel] [PATCH v1 1/1] ArmPkg: CpuDxe: Sync GCD Capabilities With Page Table Attributes
  2023-05-09 14:59                     ` Oliver Smith-Denny
@ 2023-05-10 16:10                       ` Taylor Beebe
  2023-05-16  2:53                         ` Ni, Ray
  0 siblings, 1 reply; 26+ messages in thread
From: Taylor Beebe @ 2023-05-10 16:10 UTC (permalink / raw)
  To: devel, osde, Ard Biesheuvel, Kinney, Michael D
  Cc: Ni, Ray, Leif Lindholm, Ard Biesheuvel, Sami Mujawar,
	Michael Kubacki, Sean Brogan

Can we schedule the meeting for Wednesday 5/17? I will be out the 
following week and would like to attend.

Thanks :)

On 5/9/2023 7:59 AM, Oliver Smith-Denny wrote:
> On 5/8/2023 11:59 PM, Ard Biesheuvel wrote:
>> On Tue, 9 May 2023 at 04:04, Kinney, Michael D
>> <michael.d.kinney@intel.com> wrote:
>>>
>>> I would prefer next week as well.
>>>
>>> Mike
>>>
>>
>> Next week, i can only do Wednesday. The week after (22-26), the time
>> slot works for me on any day of the week.
>>
> 
> Weds works from our side, the week after also works perfectly well
> any day. Thanks for the flexibility and willingness to meet.
> 
> For reference for this specific patch, this bz may help cache in
> some info: https://bugzilla.tianocore.org/show_bug.cgi?id=753. The
> mail links are largely dead, of course, but can be found on other
> mailing list retention sites (maybe in the future we will have PRs
> and discussions to reference :).
> 
> Thanks,
> Oliver
> 
> 
> 
> 
> 


^ permalink raw reply	[flat|nested] 26+ messages in thread

* Re: [edk2-devel] [PATCH v1 1/1] ArmPkg: CpuDxe: Sync GCD Capabilities With Page Table Attributes
  2023-05-10 16:10                       ` Taylor Beebe
@ 2023-05-16  2:53                         ` Ni, Ray
  2023-05-16 17:11                           ` Oliver Smith-Denny
  0 siblings, 1 reply; 26+ messages in thread
From: Ni, Ray @ 2023-05-16  2:53 UTC (permalink / raw)
  To: devel@edk2.groups.io, osde@linux.microsoft.com, Ard Biesheuvel,
	Kinney, Michael D, t@taylorbeebe.com
  Cc: Leif Lindholm, Ard Biesheuvel, Sami Mujawar, Michael Kubacki,
	Sean Brogan

All,
Can you check if the meeting time is ok for you?

It will be in this week:
* PDT Wednesday 07:00
* Paris Wednesday 16:00
* Shanghai Wednesday 22:00

________________________________________
From: devel@edk2.groups.io <devel@edk2.groups.io> on behalf of Taylor Beebe <t@taylorbeebe.com>
Sent: Thursday, May 11, 2023 0:10
To: devel@edk2.groups.io; osde@linux.microsoft.com; Ard Biesheuvel; Kinney, Michael D
Cc: Ni, Ray; Leif Lindholm; Ard Biesheuvel; Sami Mujawar; Michael Kubacki; Sean Brogan
Subject: Re: [edk2-devel] [PATCH v1 1/1] ArmPkg: CpuDxe: Sync GCD Capabilities With Page Table Attributes

Can we schedule the meeting for Wednesday 5/17? I will be out the
following week and would like to attend.

Thanks :)

On 5/9/2023 7:59 AM, Oliver Smith-Denny wrote:
> On 5/8/2023 11:59 PM, Ard Biesheuvel wrote:
>> On Tue, 9 May 2023 at 04:04, Kinney, Michael D
>> <michael.d.kinney@intel.com> wrote:
>>>
>>> I would prefer next week as well.
>>>
>>> Mike
>>>
>>
>> Next week, i can only do Wednesday. The week after (22-26), the time
>> slot works for me on any day of the week.
>>
>
> Weds works from our side, the week after also works perfectly well
> any day. Thanks for the flexibility and willingness to meet.
>
> For reference for this specific patch, this bz may help cache in
> some info: https://bugzilla.tianocore.org/show_bug.cgi?id=753. The
> mail links are largely dead, of course, but can be found on other
> mailing list retention sites (maybe in the future we will have PRs
> and discussions to reference :).
>
> Thanks,
> Oliver
>
>
>
>
>







^ permalink raw reply	[flat|nested] 26+ messages in thread

* Re: [edk2-devel] [PATCH v1 1/1] ArmPkg: CpuDxe: Sync GCD Capabilities With Page Table Attributes
  2023-05-16  2:53                         ` Ni, Ray
@ 2023-05-16 17:11                           ` Oliver Smith-Denny
  2023-05-17  7:14                             ` Ni, Ray
  0 siblings, 1 reply; 26+ messages in thread
From: Oliver Smith-Denny @ 2023-05-16 17:11 UTC (permalink / raw)
  To: Ni, Ray, devel@edk2.groups.io, Ard Biesheuvel, Kinney, Michael D,
	t@taylorbeebe.com
  Cc: Leif Lindholm, Ard Biesheuvel, Sami Mujawar, Michael Kubacki,
	Sean Brogan

Hi Ray,

That works from our side, thanks for setting up the meeting!

Oliver

On 5/15/2023 7:53 PM, Ni, Ray wrote:
> All,
> Can you check if the meeting time is ok for you?
> 
> It will be in this week:
> * PDT Wednesday 07:00
> * Paris Wednesday 16:00
> * Shanghai Wednesday 22:00
> 
> ________________________________________
> From: devel@edk2.groups.io <devel@edk2.groups.io> on behalf of Taylor Beebe <t@taylorbeebe.com>
> Sent: Thursday, May 11, 2023 0:10
> To: devel@edk2.groups.io; osde@linux.microsoft.com; Ard Biesheuvel; Kinney, Michael D
> Cc: Ni, Ray; Leif Lindholm; Ard Biesheuvel; Sami Mujawar; Michael Kubacki; Sean Brogan
> Subject: Re: [edk2-devel] [PATCH v1 1/1] ArmPkg: CpuDxe: Sync GCD Capabilities With Page Table Attributes
> 
> Can we schedule the meeting for Wednesday 5/17? I will be out the
> following week and would like to attend.
> 
> Thanks :)
> 
> On 5/9/2023 7:59 AM, Oliver Smith-Denny wrote:
>> On 5/8/2023 11:59 PM, Ard Biesheuvel wrote:
>>> On Tue, 9 May 2023 at 04:04, Kinney, Michael D
>>> <michael.d.kinney@intel.com> wrote:
>>>>
>>>> I would prefer next week as well.
>>>>
>>>> Mike
>>>>
>>>
>>> Next week, i can only do Wednesday. The week after (22-26), the time
>>> slot works for me on any day of the week.
>>>
>>
>> Weds works from our side, the week after also works perfectly well
>> any day. Thanks for the flexibility and willingness to meet.
>>
>> For reference for this specific patch, this bz may help cache in
>> some info: https://bugzilla.tianocore.org/show_bug.cgi?id=753. The
>> mail links are largely dead, of course, but can be found on other
>> mailing list retention sites (maybe in the future we will have PRs
>> and discussions to reference :).
>>
>> Thanks,
>> Oliver
>>
>>
>>
>>
>>
> 
> 
> 
> 
> 
> 

^ permalink raw reply	[flat|nested] 26+ messages in thread

* Re: [edk2-devel] [PATCH v1 1/1] ArmPkg: CpuDxe: Sync GCD Capabilities With Page Table Attributes
  2023-05-16 17:11                           ` Oliver Smith-Denny
@ 2023-05-17  7:14                             ` Ni, Ray
  2023-06-02  2:24                               ` Michael Kubacki
  0 siblings, 1 reply; 26+ messages in thread
From: Ni, Ray @ 2023-05-17  7:14 UTC (permalink / raw)
  To: Oliver Smith-Denny, devel@edk2.groups.io, Ard Biesheuvel,
	Kinney, Michael D, t@taylorbeebe.com
  Cc: Leif Lindholm, Ard Biesheuvel, Sami Mujawar, Michael Kubacki,
	Sean Brogan

[-- Attachment #1: Type: text/plain, Size: 2972 bytes --]

I created one event in https://edk2.groups.io/g/devel/calendar.

Microsoft Teams meeting link: https://teams.microsoft.com/l/meetup-join/19%3ameeting_YTk4ZDU3YjItODkxZC00MTdmLTlkZmUtYThkNGQ0ZWYyMDZh%40thread.v2/0?context=%7b%22Tid%22%3a%2246c98d88-e344-4ed4-8496-4ed7712e255d%22%2c%22Oid%22%3a%2255d36a50-78be-4ced-bc27-3d06c576cc19%22%7d

The ICS file is also attached.


> -----Original Message-----
> From: Oliver Smith-Denny <osde@linux.microsoft.com>
> Sent: Wednesday, May 17, 2023 1:12 AM
> To: Ni, Ray <ray.ni@intel.com>; devel@edk2.groups.io; Ard Biesheuvel
> <ardb@kernel.org>; Kinney, Michael D <michael.d.kinney@intel.com>;
> t@taylorbeebe.com
> Cc: Leif Lindholm <quic_llindhol@quicinc.com>; Ard Biesheuvel
> <ardb+tianocore@kernel.org>; Sami Mujawar <sami.mujawar@arm.com>;
> Michael Kubacki <mikuback@linux.microsoft.com>; Sean Brogan
> <sean.brogan@microsoft.com>
> Subject: Re: [edk2-devel] [PATCH v1 1/1] ArmPkg: CpuDxe: Sync GCD Capabilities
> With Page Table Attributes
> 
> Hi Ray,
> 
> That works from our side, thanks for setting up the meeting!
> 
> Oliver
> 
> On 5/15/2023 7:53 PM, Ni, Ray wrote:
> > All,
> > Can you check if the meeting time is ok for you?
> >
> > It will be in this week:
> > * PDT Wednesday 07:00
> > * Paris Wednesday 16:00
> > * Shanghai Wednesday 22:00
> >
> > ________________________________________
> > From: devel@edk2.groups.io <devel@edk2.groups.io> on behalf of Taylor Beebe
> <t@taylorbeebe.com>
> > Sent: Thursday, May 11, 2023 0:10
> > To: devel@edk2.groups.io; osde@linux.microsoft.com; Ard Biesheuvel; Kinney,
> Michael D
> > Cc: Ni, Ray; Leif Lindholm; Ard Biesheuvel; Sami Mujawar; Michael Kubacki;
> Sean Brogan
> > Subject: Re: [edk2-devel] [PATCH v1 1/1] ArmPkg: CpuDxe: Sync GCD
> Capabilities With Page Table Attributes
> >
> > Can we schedule the meeting for Wednesday 5/17? I will be out the
> > following week and would like to attend.
> >
> > Thanks :)
> >
> > On 5/9/2023 7:59 AM, Oliver Smith-Denny wrote:
> >> On 5/8/2023 11:59 PM, Ard Biesheuvel wrote:
> >>> On Tue, 9 May 2023 at 04:04, Kinney, Michael D
> >>> <michael.d.kinney@intel.com> wrote:
> >>>>
> >>>> I would prefer next week as well.
> >>>>
> >>>> Mike
> >>>>
> >>>
> >>> Next week, i can only do Wednesday. The week after (22-26), the time
> >>> slot works for me on any day of the week.
> >>>
> >>
> >> Weds works from our side, the week after also works perfectly well
> >> any day. Thanks for the flexibility and willingness to meet.
> >>
> >> For reference for this specific patch, this bz may help cache in
> >> some info: https://bugzilla.tianocore.org/show_bug.cgi?id=753. The
> >> mail links are largely dead, of course, but can be found on other
> >> mailing list retention sites (maybe in the future we will have PRs
> >> and discussions to reference :).
> >>
> >> Thanks,
> >> Oliver
> >>
> >>
> >>
> >>
> >>
> >
> >
> >
> > 
> >
> >

[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #2: UEFI Memory Map GCD Page Table discussion - ARMX86.ics --]
[-- Type: text/calendar; name="UEFI Memory Map GCD Page Table discussion - ARMX86.ics", Size: 51448 bytes --]

BEGIN:VCALENDAR
PRODID:-//Microsoft Corporation//Outlook 16.0 MIMEDIR//EN
VERSION:2.0
METHOD:REQUEST
X-MS-OLK-FORCEINSPECTOROPEN:TRUE
BEGIN:VTIMEZONE
TZID:China Standard Time
BEGIN:STANDARD
DTSTART:16010101T000000
TZOFFSETFROM:+0800
TZOFFSETTO:+0800
END:STANDARD
END:VTIMEZONE
BEGIN:VEVENT
CLASS:PUBLIC
CREATED:20230517T070852Z
DESCRIPTION: \n____________________________________________________________
	____________________ \nMicrosoft Teams meeting \nJoin on your computer\, m
	obile app or room device \nClick here to join the meeting <https://teams.m
	icrosoft.com/l/meetup-join/19%3ameeting_YTk4ZDU3YjItODkxZC00MTdmLTlkZmUtYT
	hkNGQ0ZWYyMDZh%40thread.v2/0?context=%7b%22Tid%22%3a%2246c98d88-e344-4ed4-
	8496-4ed7712e255d%22%2c%22Oid%22%3a%2255d36a50-78be-4ced-bc27-3d06c576cc19
	%22%7d>  \nMeeting ID: 256 188 860 359 \nPasscode: yJZsmm \nDownload Teams
	 <https://www.microsoft.com/en-us/microsoft-teams/download-app>  | Join on
	 the web <https://www.microsoft.com/microsoft-teams/join-a-meeting> \nJoin
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	eams/?conf=1135871399&ivr=teams&d=conf.intel.com&test=test_call>  \nOr cal
	l in (audio only) \n+86 10 5697 1340\,\,703118725# <tel:+861056971340\,\,7
	03118725#>    China\, 北京 (Beijing) \nPhone Conference ID: 703 118 725#
	 \nFind a local number <https://dialin.teams.microsoft.com/d195d438-2daa-4
	20e-b9ea-da26f9d1d6d5?id=703118725>  | Reset PIN <https://dialin.teams.mic
	rosoft.com/usp/pstnconferencing>  \nLearn More <https://aka.ms/JoinTeamsMe
	eting>  | Meeting options <https://teams.microsoft.com/meetingOptions/?org
	anizerId=55d36a50-78be-4ced-bc27-3d06c576cc19&tenantId=46c98d88-e344-4ed4-
	8496-4ed7712e255d&threadId=19_meeting_YTk4ZDU3YjItODkxZC00MTdmLTlkZmUtYThk
	NGQ0ZWYyMDZh@thread.v2&messageId=0&language=en-US>  \n____________________
	____________________________________________________________ \n \n
DTEND;TZID="China Standard Time":20230517T230000
DTSTAMP:20230517T070852Z
DTSTART;TZID="China Standard Time":20230517T220000
LAST-MODIFIED:20230517T070852Z
LOCATION:Microsoft Teams Meeting
ORGANIZER;CN="Ni, Ray":mailto:ray.ni@intel.com
PRIORITY:5
SEQUENCE:0
SUMMARY;LANGUAGE=en-us:UEFI Memory Map\, GCD\, Page Table discussion - ARM/
	X86
TRANSP:OPAQUE
UID:040000008200E00074C5B7101A82E0080000000020C8B5925882D901000000000000000
	01000000043BF7D9269E0E24899EAE72E7F953601
X-ALT-DESC;FMTTYPE=text/html:\n<html xmlns:v="urn:schemas-microsoft-com:vml
	" xmlns:o="urn:schemas-microsoft-com:office:office" xmlns:w="urn:schemas-m
	icrosoft-com:office:word" xmlns:m="http://schemas.microsoft.com/office/200
	4/12/omml" xmlns="http://www.w3.org/TR/REC-html40"><head><meta name=ProgId
	 content=Word.Document><meta name=Generator content="Microsoft Word 15"><m
	eta name=Originator content="Microsoft Word 15"><link rel=File-List href="
	cid:filelist.xml@01D98258.E5F06450"><!--[if gte mso 9]><xml>\n<o:OfficeDoc
	umentSettings>\n<o:AllowPNG/>\n</o:OfficeDocumentSettings>\n</xml><![endif
	]--><!--[if gte mso 9]><xml>\n<w:WordDocument>\n<w:SpellingState>Clean</w:
	SpellingState>\n<w:GrammarState>Clean</w:GrammarState>\n<w:TrackMoves/>\n<
	w:TrackFormatting/>\n<w:EnvelopeVis/>\n<w:PunctuationKerning/>\n<w:Validat
	eAgainstSchemas/>\n<w:SaveIfXMLInvalid>false</w:SaveIfXMLInvalid>\n<w:Igno
	reMixedContent>false</w:IgnoreMixedContent>\n<w:AlwaysShowPlaceholderText>
	false</w:AlwaysShowPlaceholderText>\n<w:DoNotPromoteQF/>\n<w:LidThemeOther
	>EN-US</w:LidThemeOther>\n<w:LidThemeAsian>ZH-CN</w:LidThemeAsian>\n<w:Lid
	ThemeComplexScript>X-NONE</w:LidThemeComplexScript>\n<w:Compatibility>\n<w
	:BreakWrappedTables/>\n<w:SnapToGridInCell/>\n<w:WrapTextWithPunct/>\n<w:U
	seAsianBreakRules/>\n<w:DontGrowAutofit/>\n<w:SplitPgBreakAndParaMark/>\n<
	w:EnableOpenTypeKerning/>\n<w:DontFlipMirrorIndents/>\n<w:OverrideTableSty
	leHps/>\n<w:UseFELayout/>\n</w:Compatibility>\n<m:mathPr>\n<m:mathFont m:v
	al="Cambria Math"/>\n<m:brkBin m:val="before"/>\n<m:brkBinSub m:val="&#45\
	;-"/>\n<m:smallFrac m:val="off"/>\n<m:dispDef/>\n<m:lMargin m:val="0"/>\n<
	m:rMargin m:val="0"/>\n<m:defJc m:val="centerGroup"/>\n<m:wrapIndent m:val
	="1440"/>\n<m:intLim m:val="subSup"/>\n<m:naryLim m:val="undOvr"/>\n</m:ma
	thPr></w:WordDocument>\n</xml><![endif]--><!--[if gte mso 9]><xml>\n<w:Lat
	entStyles DefLockedState="false" DefUnhideWhenUsed="false" DefSemiHidden="
	false" DefQFormat="false" DefPriority="99" LatentStyleCount="376">\n<w:Lsd
	Exception Locked="false" Priority="0" QFormat="true" Name="Normal"/>\n<w:L
	sdException Locked="false" Priority="9" QFormat="true" Name="heading 1"/>\
	n<w:LsdException Locked="false" Priority="9" SemiHidden="true" UnhideWhenU
	sed="true" QFormat="true" Name="heading 2"/>\n<w:LsdException Locked="fals
	e" Priority="9" SemiHidden="true" UnhideWhenUsed="true" QFormat="true" Nam
	e="heading 3"/>\n<w:LsdException Locked="false" Priority="9" SemiHidden="t
	rue" UnhideWhenUsed="true" QFormat="true" Name="heading 4"/>\n<w:LsdExcept
	ion Locked="false" Priority="9" SemiHidden="true" UnhideWhenUsed="true" QF
	ormat="true" Name="heading 5"/>\n<w:LsdException Locked="false" Priority="
	9" SemiHidden="true" UnhideWhenUsed="true" QFormat="true" Name="heading 6"
	/>\n<w:LsdException Locked="false" Priority="9" SemiHidden="true" UnhideWh
	enUsed="true" QFormat="true" Name="heading 7"/>\n<w:LsdException Locked="f
	alse" Priority="9" SemiHidden="true" UnhideWhenUsed="true" QFormat="true" 
	Name="heading 8"/>\n<w:LsdException Locked="false" Priority="9" SemiHidden
	="true" UnhideWhenUsed="true" QFormat="true" Name="heading 9"/>\n<w:LsdExc
	eption Locked="false" SemiHidden="true" UnhideWhenUsed="true" Name="index 
	1"/>\n<w:LsdException Locked="false" SemiHidden="true" UnhideWhenUsed="tru
	e" Name="index 2"/>\n<w:LsdException Locked="false" SemiHidden="true" Unhi
	deWhenUsed="true" Name="index 3"/>\n<w:LsdException Locked="false" SemiHid
	den="true" UnhideWhenUsed="true" Name="index 4"/>\n<w:LsdException Locked=
	"false" SemiHidden="true" UnhideWhenUsed="true" Name="index 5"/>\n<w:LsdEx
	ception Locked="false" SemiHidden="true" UnhideWhenUsed="true" Name="index
	 6"/>\n<w:LsdException Locked="false" SemiHidden="true" UnhideWhenUsed="tr
	ue" Name="index 7"/>\n<w:LsdException Locked="false" SemiHidden="true" Unh
	ideWhenUsed="true" Name="index 8"/>\n<w:LsdException Locked="false" SemiHi
	dden="true" UnhideWhenUsed="true" Name="index 9"/>\n<w:LsdException Locked
	="false" Priority="39" SemiHidden="true" UnhideWhenUsed="true" Name="toc 1
	"/>\n<w:LsdException Locked="false" Priority="39" SemiHidden="true" Unhide
	WhenUsed="true" Name="toc 2"/>\n<w:LsdException Locked="false" Priority="3
	9" SemiHidden="true" UnhideWhenUsed="true" Name="toc 3"/>\n<w:LsdException
	 Locked="false" Priority="39" SemiHidden="true" UnhideWhenUsed="true" Name
	="toc 4"/>\n<w:LsdException Locked="false" Priority="39" SemiHidden="true"
	 UnhideWhenUsed="true" Name="toc 5"/>\n<w:LsdException Locked="false" Prio
	rity="39" SemiHidden="true" UnhideWhenUsed="true" Name="toc 6"/>\n<w:LsdEx
	ception Locked="false" Priority="39" SemiHidden="true" UnhideWhenUsed="tru
	e" Name="toc 7"/>\n<w:LsdException Locked="false" Priority="39" SemiHidden
	="true" UnhideWhenUsed="true" Name="toc 8"/>\n<w:LsdException Locked="fals
	e" Priority="39" SemiHidden="true" UnhideWhenUsed="true" Name="toc 9"/>\n<
	w:LsdException Locked="false" SemiHidden="true" UnhideWhenUsed="true" Name
	="Normal Indent"/>\n<w:LsdException Locked="false" SemiHidden="true" Unhid
	eWhenUsed="true" Name="footnote text"/>\n<w:LsdException Locked="false" Se
	miHidden="true" UnhideWhenUsed="true" Name="annotation text"/>\n<w:LsdExce
	ption Locked="false" SemiHidden="true" UnhideWhenUsed="true" Name="header"
	/>\n<w:LsdException Locked="false" SemiHidden="true" UnhideWhenUsed="true"
	 Name="footer"/>\n<w:LsdException Locked="false" SemiHidden="true" UnhideW
	henUsed="true" Name="index heading"/>\n<w:LsdException Locked="false" Prio
	rity="35" SemiHidden="true" UnhideWhenUsed="true" QFormat="true" Name="cap
	tion"/>\n<w:LsdException Locked="false" SemiHidden="true" UnhideWhenUsed="
	true" Name="table of figures"/>\n<w:LsdException Locked="false" SemiHidden
	="true" UnhideWhenUsed="true" Name="envelope address"/>\n<w:LsdException L
	ocked="false" SemiHidden="true" UnhideWhenUsed="true" Name="envelope retur
	n"/>\n<w:LsdException Locked="false" SemiHidden="true" UnhideWhenUsed="tru
	e" Name="footnote reference"/>\n<w:LsdException Locked="false" SemiHidden=
	"true" UnhideWhenUsed="true" Name="annotation reference"/>\n<w:LsdExceptio
	n Locked="false" SemiHidden="true" UnhideWhenUsed="true" Name="line number
	"/>\n<w:LsdException Locked="false" SemiHidden="true" UnhideWhenUsed="true
	" Name="page number"/>\n<w:LsdException Locked="false" SemiHidden="true" U
	nhideWhenUsed="true" Name="endnote reference"/>\n<w:LsdException Locked="f
	alse" SemiHidden="true" UnhideWhenUsed="true" Name="endnote text"/>\n<w:Ls
	dException Locked="false" SemiHidden="true" UnhideWhenUsed="true" Name="ta
	ble of authorities"/>\n<w:LsdException Locked="false" SemiHidden="true" Un
	hideWhenUsed="true" Name="macro"/>\n<w:LsdException Locked="false" SemiHid
	den="true" UnhideWhenUsed="true" Name="toa heading"/>\n<w:LsdException Loc
	ked="false" SemiHidden="true" UnhideWhenUsed="true" Name="List"/>\n<w:LsdE
	xception Locked="false" SemiHidden="true" UnhideWhenUsed="true" Name="List
	 Bullet"/>\n<w:LsdException Locked="false" SemiHidden="true" UnhideWhenUse
	d="true" Name="List Number"/>\n<w:LsdException Locked="false" SemiHidden="
	true" UnhideWhenUsed="true" Name="List 2"/>\n<w:LsdException Locked="false
	" SemiHidden="true" UnhideWhenUsed="true" Name="List 3"/>\n<w:LsdException
	 Locked="false" SemiHidden="true" UnhideWhenUsed="true" Name="List 4"/>\n<
	w:LsdException Locked="false" SemiHidden="true" UnhideWhenUsed="true" Name
	="List 5"/>\n<w:LsdException Locked="false" SemiHidden="true" UnhideWhenUs
	ed="true" Name="List Bullet 2"/>\n<w:LsdException Locked="false" SemiHidde
	n="true" UnhideWhenUsed="true" Name="List Bullet 3"/>\n<w:LsdException Loc
	ked="false" SemiHidden="true" UnhideWhenUsed="true" Name="List Bullet 4"/>
	\n<w:LsdException Locked="false" SemiHidden="true" UnhideWhenUsed="true" N
	ame="List Bullet 5"/>\n<w:LsdException Locked="false" SemiHidden="true" Un
	hideWhenUsed="true" Name="List Number 2"/>\n<w:LsdException Locked="false"
	 SemiHidden="true" UnhideWhenUsed="true" Name="List Number 3"/>\n<w:LsdExc
	eption Locked="false" SemiHidden="true" UnhideWhenUsed="true" Name="List N
	umber 4"/>\n<w:LsdException Locked="false" SemiHidden="true" UnhideWhenUse
	d="true" Name="List Number 5"/>\n<w:LsdException Locked="false" Priority="
	10" QFormat="true" Name="Title"/>\n<w:LsdException Locked="false" SemiHidd
	en="true" UnhideWhenUsed="true" Name="Closing"/>\n<w:LsdException Locked="
	false" SemiHidden="true" UnhideWhenUsed="true" Name="Signature"/>\n<w:LsdE
	xception Locked="false" Priority="1" SemiHidden="true" UnhideWhenUsed="tru
	e" Name="Default Paragraph Font"/>\n<w:LsdException Locked="false" SemiHid
	den="true" UnhideWhenUsed="true" Name="Body Text"/>\n<w:LsdException Locke
	d="false" SemiHidden="true" UnhideWhenUsed="true" Name="Body Text Indent"/
	>\n<w:LsdException Locked="false" SemiHidden="true" UnhideWhenUsed="true" 
	Name="List Continue"/>\n<w:LsdException Locked="false" SemiHidden="true" U
	nhideWhenUsed="true" Name="List Continue 2"/>\n<w:LsdException Locked="fal
	se" SemiHidden="true" UnhideWhenUsed="true" Name="List Continue 3"/>\n<w:L
	sdException Locked="false" SemiHidden="true" UnhideWhenUsed="true" Name="L
	ist Continue 4"/>\n<w:LsdException Locked="false" SemiHidden="true" Unhide
	WhenUsed="true" Name="List Continue 5"/>\n<w:LsdException Locked="false" S
	emiHidden="true" UnhideWhenUsed="true" Name="Message Header"/>\n<w:LsdExce
	ption Locked="false" Priority="11" QFormat="true" Name="Subtitle"/>\n<w:Ls
	dException Locked="false" SemiHidden="true" UnhideWhenUsed="true" Name="Sa
	lutation"/>\n<w:LsdException Locked="false" SemiHidden="true" UnhideWhenUs
	ed="true" Name="Date"/>\n<w:LsdException Locked="false" SemiHidden="true" 
	UnhideWhenUsed="true" Name="Body Text First Indent"/>\n<w:LsdException Loc
	ked="false" SemiHidden="true" UnhideWhenUsed="true" Name="Body Text First 
	Indent 2"/>\n<w:LsdException Locked="false" SemiHidden="true" UnhideWhenUs
	ed="true" Name="Note Heading"/>\n<w:LsdException Locked="false" SemiHidden
	="true" UnhideWhenUsed="true" Name="Body Text 2"/>\n<w:LsdException Locked
	="false" SemiHidden="true" UnhideWhenUsed="true" Name="Body Text 3"/>\n<w:
	LsdException Locked="false" SemiHidden="true" UnhideWhenUsed="true" Name="
	Body Text Indent 2"/>\n<w:LsdException Locked="false" SemiHidden="true" Un
	hideWhenUsed="true" Name="Body Text Indent 3"/>\n<w:LsdException Locked="f
	alse" SemiHidden="true" UnhideWhenUsed="true" Name="Block Text"/>\n<w:LsdE
	xception Locked="false" SemiHidden="true" UnhideWhenUsed="true" Name="Hype
	rlink"/>\n<w:LsdException Locked="false" SemiHidden="true" UnhideWhenUsed=
	"true" Name="FollowedHyperlink"/>\n<w:LsdException Locked="false" Priority
	="22" QFormat="true" Name="Strong"/>\n<w:LsdException Locked="false" Prior
	ity="20" QFormat="true" Name="Emphasis"/>\n<w:LsdException Locked="false" 
	SemiHidden="true" UnhideWhenUsed="true" Name="Document Map"/>\n<w:LsdExcep
	tion Locked="false" SemiHidden="true" UnhideWhenUsed="true" Name="Plain Te
	xt"/>\n<w:LsdException Locked="false" SemiHidden="true" UnhideWhenUsed="tr
	ue" Name="E-mail Signature"/>\n<w:LsdException Locked="false" SemiHidden="
	true" UnhideWhenUsed="true" Name="HTML Top of Form"/>\n<w:LsdException Loc
	ked="false" SemiHidden="true" UnhideWhenUsed="true" Name="HTML Bottom of F
	orm"/>\n<w:LsdException Locked="false" SemiHidden="true" UnhideWhenUsed="t
	rue" Name="Normal (Web)"/>\n<w:LsdException Locked="false" SemiHidden="tru
	e" UnhideWhenUsed="true" Name="HTML Acronym"/>\n<w:LsdException Locked="fa
	lse" SemiHidden="true" UnhideWhenUsed="true" Name="HTML Address"/>\n<w:Lsd
	Exception Locked="false" SemiHidden="true" UnhideWhenUsed="true" Name="HTM
	L Cite"/>\n<w:LsdException Locked="false" SemiHidden="true" UnhideWhenUsed
	="true" Name="HTML Code"/>\n<w:LsdException Locked="false" SemiHidden="tru
	e" UnhideWhenUsed="true" Name="HTML Definition"/>\n<w:LsdException Locked=
	"false" SemiHidden="true" UnhideWhenUsed="true" Name="HTML Keyboard"/>\n<w
	:LsdException Locked="false" SemiHidden="true" UnhideWhenUsed="true" Name=
	"HTML Preformatted"/>\n<w:LsdException Locked="false" SemiHidden="true" Un
	hideWhenUsed="true" Name="HTML Sample"/>\n<w:LsdException Locked="false" S
	emiHidden="true" UnhideWhenUsed="true" Name="HTML Typewriter"/>\n<w:LsdExc
	eption Locked="false" SemiHidden="true" UnhideWhenUsed="true" Name="HTML V
	ariable"/>\n<w:LsdException Locked="false" SemiHidden="true" UnhideWhenUse
	d="true" Name="Normal Table"/>\n<w:LsdException Locked="false" SemiHidden=
	"true" UnhideWhenUsed="true" Name="annotation subject"/>\n<w:LsdException 
	Locked="false" SemiHidden="true" UnhideWhenUsed="true" Name="No List"/>\n<
	w:LsdException Locked="false" SemiHidden="true" UnhideWhenUsed="true" Name
	="Outline List 1"/>\n<w:LsdException Locked="false" SemiHidden="true" Unhi
	deWhenUsed="true" Name="Outline List 2"/>\n<w:LsdException Locked="false" 
	SemiHidden="true" UnhideWhenUsed="true" Name="Outline List 3"/>\n<w:LsdExc
	eption Locked="false" SemiHidden="true" UnhideWhenUsed="true" Name="Table 
	Simple 1"/>\n<w:LsdException Locked="false" SemiHidden="true" UnhideWhenUs
	ed="true" Name="Table Simple 2"/>\n<w:LsdException Locked="false" SemiHidd
	en="true" UnhideWhenUsed="true" Name="Table Simple 3"/>\n<w:LsdException L
	ocked="false" SemiHidden="true" UnhideWhenUsed="true" Name="Table Classic 
	1"/>\n<w:LsdException Locked="false" SemiHidden="true" UnhideWhenUsed="tru
	e" Name="Table Classic 2"/>\n<w:LsdException Locked="false" SemiHidden="tr
	ue" UnhideWhenUsed="true" Name="Table Classic 3"/>\n<w:LsdException Locked
	="false" SemiHidden="true" UnhideWhenUsed="true" Name="Table Classic 4"/>\
	n<w:LsdException Locked="false" SemiHidden="true" UnhideWhenUsed="true" Na
	me="Table Colorful 1"/>\n<w:LsdException Locked="false" SemiHidden="true" 
	UnhideWhenUsed="true" Name="Table Colorful 2"/>\n<w:LsdException Locked="f
	alse" SemiHidden="true" UnhideWhenUsed="true" Name="Table Colorful 3"/>\n<
	w:LsdException Locked="false" SemiHidden="true" UnhideWhenUsed="true" Name
	="Table Columns 1"/>\n<w:LsdException Locked="false" SemiHidden="true" Unh
	ideWhenUsed="true" Name="Table Columns 2"/>\n<w:LsdException Locked="false
	" SemiHidden="true" UnhideWhenUsed="true" Name="Table Columns 3"/>\n<w:Lsd
	Exception Locked="false" SemiHidden="true" UnhideWhenUsed="true" Name="Tab
	le Columns 4"/>\n<w:LsdException Locked="false" SemiHidden="true" UnhideWh
	enUsed="true" Name="Table Columns 5"/>\n<w:LsdException Locked="false" Sem
	iHidden="true" UnhideWhenUsed="true" Name="Table Grid 1"/>\n<w:LsdExceptio
	n Locked="false" SemiHidden="true" UnhideWhenUsed="true" Name="Table Grid 
	2"/>\n<w:LsdException Locked="false" SemiHidden="true" UnhideWhenUsed="tru
	e" Name="Table Grid 3"/>\n<w:LsdException Locked="false" SemiHidden="true"
	 UnhideWhenUsed="true" Name="Table Grid 4"/>\n<w:LsdException Locked="fals
	e" SemiHidden="true" UnhideWhenUsed="true" Name="Table Grid 5"/>\n<w:LsdEx
	ception Locked="false" SemiHidden="true" UnhideWhenUsed="true" Name="Table
	 Grid 6"/>\n<w:LsdException Locked="false" SemiHidden="true" UnhideWhenUse
	d="true" Name="Table Grid 7"/>\n<w:LsdException Locked="false" SemiHidden=
	"true" UnhideWhenUsed="true" Name="Table Grid 8"/>\n<w:LsdException Locked
	="false" SemiHidden="true" UnhideWhenUsed="true" Name="Table List 1"/>\n<w
	:LsdException Locked="false" SemiHidden="true" UnhideWhenUsed="true" Name=
	"Table List 2"/>\n<w:LsdException Locked="false" SemiHidden="true" UnhideW
	henUsed="true" Name="Table List 3"/>\n<w:LsdException Locked="false" SemiH
	idden="true" UnhideWhenUsed="true" Name="Table List 4"/>\n<w:LsdException 
	Locked="false" SemiHidden="true" UnhideWhenUsed="true" Name="Table List 5"
	/>\n<w:LsdException Locked="false" SemiHidden="true" UnhideWhenUsed="true"
	 Name="Table List 6"/>\n<w:LsdException Locked="false" SemiHidden="true" U
	nhideWhenUsed="true" Name="Table List 7"/>\n<w:LsdException Locked="false"
	 SemiHidden="true" UnhideWhenUsed="true" Name="Table List 8"/>\n<w:LsdExce
	ption Locked="false" SemiHidden="true" UnhideWhenUsed="true" Name="Table 3
	D effects 1"/>\n<w:LsdException Locked="false" SemiHidden="true" UnhideWhe
	nUsed="true" Name="Table 3D effects 2"/>\n<w:LsdException Locked="false" S
	emiHidden="true" UnhideWhenUsed="true" Name="Table 3D effects 3"/>\n<w:Lsd
	Exception Locked="false" SemiHidden="true" UnhideWhenUsed="true" Name="Tab
	le Contemporary"/>\n<w:LsdException Locked="false" SemiHidden="true" Unhid
	eWhenUsed="true" Name="Table Elegant"/>\n<w:LsdException Locked="false" Se
	miHidden="true" UnhideWhenUsed="true" Name="Table Professional"/>\n<w:LsdE
	xception Locked="false" SemiHidden="true" UnhideWhenUsed="true" Name="Tabl
	e Subtle 1"/>\n<w:LsdException Locked="false" SemiHidden="true" UnhideWhen
	Used="true" Name="Table Subtle 2"/>\n<w:LsdException Locked="false" SemiHi
	dden="true" UnhideWhenUsed="true" Name="Table Web 1"/>\n<w:LsdException Lo
	cked="false" SemiHidden="true" UnhideWhenUsed="true" Name="Table Web 2"/>\
	n<w:LsdException Locked="false" SemiHidden="true" UnhideWhenUsed="true" Na
	me="Table Web 3"/>\n<w:LsdException Locked="false" SemiHidden="true" Unhid
	eWhenUsed="true" Name="Balloon Text"/>\n<w:LsdException Locked="false" Pri
	ority="39" Name="Table Grid"/>\n<w:LsdException Locked="false" SemiHidden=
	"true" UnhideWhenUsed="true" Name="Table Theme"/>\n<w:LsdException Locked=
	"false" SemiHidden="true" Name="Placeholder Text"/>\n<w:LsdException Locke
	d="false" Priority="1" QFormat="true" Name="No Spacing"/>\n<w:LsdException
	 Locked="false" Priority="60" Name="Light Shading"/>\n<w:LsdException Lock
	ed="false" Priority="61" Name="Light List"/>\n<w:LsdException Locked="fals
	e" Priority="62" Name="Light Grid"/>\n<w:LsdException Locked="false" Prior
	ity="63" Name="Medium Shading 1"/>\n<w:LsdException Locked="false" Priorit
	y="64" Name="Medium Shading 2"/>\n<w:LsdException Locked="false" Priority=
	"65" Name="Medium List 1"/>\n<w:LsdException Locked="false" Priority="66" 
	Name="Medium List 2"/>\n<w:LsdException Locked="false" Priority="67" Name=
	"Medium Grid 1"/>\n<w:LsdException Locked="false" Priority="68" Name="Medi
	um Grid 2"/>\n<w:LsdException Locked="false" Priority="69" Name="Medium Gr
	id 3"/>\n<w:LsdException Locked="false" Priority="70" Name="Dark List"/>\n
	<w:LsdException Locked="false" Priority="71" Name="Colorful Shading"/>\n<w
	:LsdException Locked="false" Priority="72" Name="Colorful List"/>\n<w:LsdE
	xception Locked="false" Priority="73" Name="Colorful Grid"/>\n<w:LsdExcept
	ion Locked="false" Priority="60" Name="Light Shading Accent 1"/>\n<w:LsdEx
	ception Locked="false" Priority="61" Name="Light List Accent 1"/>\n<w:LsdE
	xception Locked="false" Priority="62" Name="Light Grid Accent 1"/>\n<w:Lsd
	Exception Locked="false" Priority="63" Name="Medium Shading 1 Accent 1"/>\
	n<w:LsdException Locked="false" Priority="64" Name="Medium Shading 2 Accen
	t 1"/>\n<w:LsdException Locked="false" Priority="65" Name="Medium List 1 A
	ccent 1"/>\n<w:LsdException Locked="false" SemiHidden="true" Name="Revisio
	n"/>\n<w:LsdException Locked="false" Priority="34" QFormat="true" Name="Li
	st Paragraph"/>\n<w:LsdException Locked="false" Priority="29" QFormat="tru
	e" Name="Quote"/>\n<w:LsdException Locked="false" Priority="30" QFormat="t
	rue" Name="Intense Quote"/>\n<w:LsdException Locked="false" Priority="66" 
	Name="Medium List 2 Accent 1"/>\n<w:LsdException Locked="false" Priority="
	67" Name="Medium Grid 1 Accent 1"/>\n<w:LsdException Locked="false" Priori
	ty="68" Name="Medium Grid 2 Accent 1"/>\n<w:LsdException Locked="false" Pr
	iority="69" Name="Medium Grid 3 Accent 1"/>\n<w:LsdException Locked="false
	" Priority="70" Name="Dark List Accent 1"/>\n<w:LsdException Locked="false
	" Priority="71" Name="Colorful Shading Accent 1"/>\n<w:LsdException Locked
	="false" Priority="72" Name="Colorful List Accent 1"/>\n<w:LsdException Lo
	cked="false" Priority="73" Name="Colorful Grid Accent 1"/>\n<w:LsdExceptio
	n Locked="false" Priority="60" Name="Light Shading Accent 2"/>\n<w:LsdExce
	ption Locked="false" Priority="61" Name="Light List Accent 2"/>\n<w:LsdExc
	eption Locked="false" Priority="62" Name="Light Grid Accent 2"/>\n<w:LsdEx
	ception Locked="false" Priority="63" Name="Medium Shading 1 Accent 2"/>\n<
	w:LsdException Locked="false" Priority="64" Name="Medium Shading 2 Accent 
	2"/>\n<w:LsdException Locked="false" Priority="65" Name="Medium List 1 Acc
	ent 2"/>\n<w:LsdException Locked="false" Priority="66" Name="Medium List 2
	 Accent 2"/>\n<w:LsdException Locked="false" Priority="67" Name="Medium Gr
	id 1 Accent 2"/>\n<w:LsdException Locked="false" Priority="68" Name="Mediu
	m Grid 2 Accent 2"/>\n<w:LsdException Locked="false" Priority="69" Name="M
	edium Grid 3 Accent 2"/>\n<w:LsdException Locked="false" Priority="70" Nam
	e="Dark List Accent 2"/>\n<w:LsdException Locked="false" Priority="71" Nam
	e="Colorful Shading Accent 2"/>\n<w:LsdException Locked="false" Priority="
	72" Name="Colorful List Accent 2"/>\n<w:LsdException Locked="false" Priori
	ty="73" Name="Colorful Grid Accent 2"/>\n<w:LsdException Locked="false" Pr
	iority="60" Name="Light Shading Accent 3"/>\n<w:LsdException Locked="false
	" Priority="61" Name="Light List Accent 3"/>\n<w:LsdException Locked="fals
	e" Priority="62" Name="Light Grid Accent 3"/>\n<w:LsdException Locked="fal
	se" Priority="63" Name="Medium Shading 1 Accent 3"/>\n<w:LsdException Lock
	ed="false" Priority="64" Name="Medium Shading 2 Accent 3"/>\n<w:LsdExcepti
	on Locked="false" Priority="65" Name="Medium List 1 Accent 3"/>\n<w:LsdExc
	eption Locked="false" Priority="66" Name="Medium List 2 Accent 3"/>\n<w:Ls
	dException Locked="false" Priority="67" Name="Medium Grid 1 Accent 3"/>\n<
	w:LsdException Locked="false" Priority="68" Name="Medium Grid 2 Accent 3"/
	>\n<w:LsdException Locked="false" Priority="69" Name="Medium Grid 3 Accent
	 3"/>\n<w:LsdException Locked="false" Priority="70" Name="Dark List Accent
	 3"/>\n<w:LsdException Locked="false" Priority="71" Name="Colorful Shading
	 Accent 3"/>\n<w:LsdException Locked="false" Priority="72" Name="Colorful 
	List Accent 3"/>\n<w:LsdException Locked="false" Priority="73" Name="Color
	ful Grid Accent 3"/>\n<w:LsdException Locked="false" Priority="60" Name="L
	ight Shading Accent 4"/>\n<w:LsdException Locked="false" Priority="61" Nam
	e="Light List Accent 4"/>\n<w:LsdException Locked="false" Priority="62" Na
	me="Light Grid Accent 4"/>\n<w:LsdException Locked="false" Priority="63" N
	ame="Medium Shading 1 Accent 4"/>\n<w:LsdException Locked="false" Priority
	="64" Name="Medium Shading 2 Accent 4"/>\n<w:LsdException Locked="false" P
	riority="65" Name="Medium List 1 Accent 4"/>\n<w:LsdException Locked="fals
	e" Priority="66" Name="Medium List 2 Accent 4"/>\n<w:LsdException Locked="
	false" Priority="67" Name="Medium Grid 1 Accent 4"/>\n<w:LsdException Lock
	ed="false" Priority="68" Name="Medium Grid 2 Accent 4"/>\n<w:LsdException 
	Locked="false" Priority="69" Name="Medium Grid 3 Accent 4"/>\n<w:LsdExcept
	ion Locked="false" Priority="70" Name="Dark List Accent 4"/>\n<w:LsdExcept
	ion Locked="false" Priority="71" Name="Colorful Shading Accent 4"/>\n<w:Ls
	dException Locked="false" Priority="72" Name="Colorful List Accent 4"/>\n<
	w:LsdException Locked="false" Priority="73" Name="Colorful Grid Accent 4"/
	>\n<w:LsdException Locked="false" Priority="60" Name="Light Shading Accent
	 5"/>\n<w:LsdException Locked="false" Priority="61" Name="Light List Accen
	t 5"/>\n<w:LsdException Locked="false" Priority="62" Name="Light Grid Acce
	nt 5"/>\n<w:LsdException Locked="false" Priority="63" Name="Medium Shading
	 1 Accent 5"/>\n<w:LsdException Locked="false" Priority="64" Name="Medium 
	Shading 2 Accent 5"/>\n<w:LsdException Locked="false" Priority="65" Name="
	Medium List 1 Accent 5"/>\n<w:LsdException Locked="false" Priority="66" Na
	me="Medium List 2 Accent 5"/>\n<w:LsdException Locked="false" Priority="67
	" Name="Medium Grid 1 Accent 5"/>\n<w:LsdException Locked="false" Priority
	="68" Name="Medium Grid 2 Accent 5"/>\n<w:LsdException Locked="false" Prio
	rity="69" Name="Medium Grid 3 Accent 5"/>\n<w:LsdException Locked="false" 
	Priority="70" Name="Dark List Accent 5"/>\n<w:LsdException Locked="false" 
	Priority="71" Name="Colorful Shading Accent 5"/>\n<w:LsdException Locked="
	false" Priority="72" Name="Colorful List Accent 5"/>\n<w:LsdException Lock
	ed="false" Priority="73" Name="Colorful Grid Accent 5"/>\n<w:LsdException 
	Locked="false" Priority="60" Name="Light Shading Accent 6"/>\n<w:LsdExcept
	ion Locked="false" Priority="61" Name="Light List Accent 6"/>\n<w:LsdExcep
	tion Locked="false" Priority="62" Name="Light Grid Accent 6"/>\n<w:LsdExce
	ption Locked="false" Priority="63" Name="Medium Shading 1 Accent 6"/>\n<w:
	LsdException Locked="false" Priority="64" Name="Medium Shading 2 Accent 6"
	/>\n<w:LsdException Locked="false" Priority="65" Name="Medium List 1 Accen
	t 6"/>\n<w:LsdException Locked="false" Priority="66" Name="Medium List 2 A
	ccent 6"/>\n<w:LsdException Locked="false" Priority="67" Name="Medium Grid
	 1 Accent 6"/>\n<w:LsdException Locked="false" Priority="68" Name="Medium 
	Grid 2 Accent 6"/>\n<w:LsdException Locked="false" Priority="69" Name="Med
	ium Grid 3 Accent 6"/>\n<w:LsdException Locked="false" Priority="70" Name=
	"Dark List Accent 6"/>\n<w:LsdException Locked="false" Priority="71" Name=
	"Colorful Shading Accent 6"/>\n<w:LsdException Locked="false" Priority="72
	" Name="Colorful List Accent 6"/>\n<w:LsdException Locked="false" Priority
	="73" Name="Colorful Grid Accent 6"/>\n<w:LsdException Locked="false" Prio
	rity="19" QFormat="true" Name="Subtle Emphasis"/>\n<w:LsdException Locked=
	"false" Priority="21" QFormat="true" Name="Intense Emphasis"/>\n<w:LsdExce
	ption Locked="false" Priority="31" QFormat="true" Name="Subtle Reference"/
	>\n<w:LsdException Locked="false" Priority="32" QFormat="true" Name="Inten
	se Reference"/>\n<w:LsdException Locked="false" Priority="33" QFormat="tru
	e" Name="Book Title"/>\n<w:LsdException Locked="false" Priority="37" SemiH
	idden="true" UnhideWhenUsed="true" Name="Bibliography"/>\n<w:LsdException 
	Locked="false" Priority="39" SemiHidden="true" UnhideWhenUsed="true" QForm
	at="true" Name="TOC Heading"/>\n<w:LsdException Locked="false" Priority="4
	1" Name="Plain Table 1"/>\n<w:LsdException Locked="false" Priority="42" Na
	me="Plain Table 2"/>\n<w:LsdException Locked="false" Priority="43" Name="P
	lain Table 3"/>\n<w:LsdException Locked="false" Priority="44" Name="Plain 
	Table 4"/>\n<w:LsdException Locked="false" Priority="45" Name="Plain Table
	 5"/>\n<w:LsdException Locked="false" Priority="40" Name="Grid Table Light
	"/>\n<w:LsdException Locked="false" Priority="46" Name="Grid Table 1 Light
	"/>\n<w:LsdException Locked="false" Priority="47" Name="Grid Table 2"/>\n<
	w:LsdException Locked="false" Priority="48" Name="Grid Table 3"/>\n<w:LsdE
	xception Locked="false" Priority="49" Name="Grid Table 4"/>\n<w:LsdExcepti
	on Locked="false" Priority="50" Name="Grid Table 5 Dark"/>\n<w:LsdExceptio
	n Locked="false" Priority="51" Name="Grid Table 6 Colorful"/>\n<w:LsdExcep
	tion Locked="false" Priority="52" Name="Grid Table 7 Colorful"/>\n<w:LsdEx
	ception Locked="false" Priority="46" Name="Grid Table 1 Light Accent 1"/>\
	n<w:LsdException Locked="false" Priority="47" Name="Grid Table 2 Accent 1"
	/>\n<w:LsdException Locked="false" Priority="48" Name="Grid Table 3 Accent
	 1"/>\n<w:LsdException Locked="false" Priority="49" Name="Grid Table 4 Acc
	ent 1"/>\n<w:LsdException Locked="false" Priority="50" Name="Grid Table 5 
	Dark Accent 1"/>\n<w:LsdException Locked="false" Priority="51" Name="Grid 
	Table 6 Colorful Accent 1"/>\n<w:LsdException Locked="false" Priority="52"
	 Name="Grid Table 7 Colorful Accent 1"/>\n<w:LsdException Locked="false" P
	riority="46" Name="Grid Table 1 Light Accent 2"/>\n<w:LsdException Locked=
	"false" Priority="47" Name="Grid Table 2 Accent 2"/>\n<w:LsdException Lock
	ed="false" Priority="48" Name="Grid Table 3 Accent 2"/>\n<w:LsdException L
	ocked="false" Priority="49" Name="Grid Table 4 Accent 2"/>\n<w:LsdExceptio
	n Locked="false" Priority="50" Name="Grid Table 5 Dark Accent 2"/>\n<w:Lsd
	Exception Locked="false" Priority="51" Name="Grid Table 6 Colorful Accent 
	2"/>\n<w:LsdException Locked="false" Priority="52" Name="Grid Table 7 Colo
	rful Accent 2"/>\n<w:LsdException Locked="false" Priority="46" Name="Grid 
	Table 1 Light Accent 3"/>\n<w:LsdException Locked="false" Priority="47" Na
	me="Grid Table 2 Accent 3"/>\n<w:LsdException Locked="false" Priority="48"
	 Name="Grid Table 3 Accent 3"/>\n<w:LsdException Locked="false" Priority="
	49" Name="Grid Table 4 Accent 3"/>\n<w:LsdException Locked="false" Priorit
	y="50" Name="Grid Table 5 Dark Accent 3"/>\n<w:LsdException Locked="false"
	 Priority="51" Name="Grid Table 6 Colorful Accent 3"/>\n<w:LsdException Lo
	cked="false" Priority="52" Name="Grid Table 7 Colorful Accent 3"/>\n<w:Lsd
	Exception Locked="false" Priority="46" Name="Grid Table 1 Light Accent 4"/
	>\n<w:LsdException Locked="false" Priority="47" Name="Grid Table 2 Accent 
	4"/>\n<w:LsdException Locked="false" Priority="48" Name="Grid Table 3 Acce
	nt 4"/>\n<w:LsdException Locked="false" Priority="49" Name="Grid Table 4 A
	ccent 4"/>\n<w:LsdException Locked="false" Priority="50" Name="Grid Table 
	5 Dark Accent 4"/>\n<w:LsdException Locked="false" Priority="51" Name="Gri
	d Table 6 Colorful Accent 4"/>\n<w:LsdException Locked="false" Priority="5
	2" Name="Grid Table 7 Colorful Accent 4"/>\n<w:LsdException Locked="false"
	 Priority="46" Name="Grid Table 1 Light Accent 5"/>\n<w:LsdException Locke
	d="false" Priority="47" Name="Grid Table 2 Accent 5"/>\n<w:LsdException Lo
	cked="false" Priority="48" Name="Grid Table 3 Accent 5"/>\n<w:LsdException
	 Locked="false" Priority="49" Name="Grid Table 4 Accent 5"/>\n<w:LsdExcept
	ion Locked="false" Priority="50" Name="Grid Table 5 Dark Accent 5"/>\n<w:L
	sdException Locked="false" Priority="51" Name="Grid Table 6 Colorful Accen
	t 5"/>\n<w:LsdException Locked="false" Priority="52" Name="Grid Table 7 Co
	lorful Accent 5"/>\n<w:LsdException Locked="false" Priority="46" Name="Gri
	d Table 1 Light Accent 6"/>\n<w:LsdException Locked="false" Priority="47" 
	Name="Grid Table 2 Accent 6"/>\n<w:LsdException Locked="false" Priority="4
	8" Name="Grid Table 3 Accent 6"/>\n<w:LsdException Locked="false" Priority
	="49" Name="Grid Table 4 Accent 6"/>\n<w:LsdException Locked="false" Prior
	ity="50" Name="Grid Table 5 Dark Accent 6"/>\n<w:LsdException Locked="fals
	e" Priority="51" Name="Grid Table 6 Colorful Accent 6"/>\n<w:LsdException 
	Locked="false" Priority="52" Name="Grid Table 7 Colorful Accent 6"/>\n<w:L
	sdException Locked="false" Priority="46" Name="List Table 1 Light"/>\n<w:L
	sdException Locked="false" Priority="47" Name="List Table 2"/>\n<w:LsdExce
	ption Locked="false" Priority="48" Name="List Table 3"/>\n<w:LsdException 
	Locked="false" Priority="49" Name="List Table 4"/>\n<w:LsdException Locked
	="false" Priority="50" Name="List Table 5 Dark"/>\n<w:LsdException Locked=
	"false" Priority="51" Name="List Table 6 Colorful"/>\n<w:LsdException Lock
	ed="false" Priority="52" Name="List Table 7 Colorful"/>\n<w:LsdException L
	ocked="false" Priority="46" Name="List Table 1 Light Accent 1"/>\n<w:LsdEx
	ception Locked="false" Priority="47" Name="List Table 2 Accent 1"/>\n<w:Ls
	dException Locked="false" Priority="48" Name="List Table 3 Accent 1"/>\n<w
	:LsdException Locked="false" Priority="49" Name="List Table 4 Accent 1"/>\
	n<w:LsdException Locked="false" Priority="50" Name="List Table 5 Dark Acce
	nt 1"/>\n<w:LsdException Locked="false" Priority="51" Name="List Table 6 C
	olorful Accent 1"/>\n<w:LsdException Locked="false" Priority="52" Name="Li
	st Table 7 Colorful Accent 1"/>\n<w:LsdException Locked="false" Priority="
	46" Name="List Table 1 Light Accent 2"/>\n<w:LsdException Locked="false" P
	riority="47" Name="List Table 2 Accent 2"/>\n<w:LsdException Locked="false
	" Priority="48" Name="List Table 3 Accent 2"/>\n<w:LsdException Locked="fa
	lse" Priority="49" Name="List Table 4 Accent 2"/>\n<w:LsdException Locked=
	"false" Priority="50" Name="List Table 5 Dark Accent 2"/>\n<w:LsdException
	 Locked="false" Priority="51" Name="List Table 6 Colorful Accent 2"/>\n<w:
	LsdException Locked="false" Priority="52" Name="List Table 7 Colorful Acce
	nt 2"/>\n<w:LsdException Locked="false" Priority="46" Name="List Table 1 L
	ight Accent 3"/>\n<w:LsdException Locked="false" Priority="47" Name="List 
	Table 2 Accent 3"/>\n<w:LsdException Locked="false" Priority="48" Name="Li
	st Table 3 Accent 3"/>\n<w:LsdException Locked="false" Priority="49" Name=
	"List Table 4 Accent 3"/>\n<w:LsdException Locked="false" Priority="50" Na
	me="List Table 5 Dark Accent 3"/>\n<w:LsdException Locked="false" Priority
	="51" Name="List Table 6 Colorful Accent 3"/>\n<w:LsdException Locked="fal
	se" Priority="52" Name="List Table 7 Colorful Accent 3"/>\n<w:LsdException
	 Locked="false" Priority="46" Name="List Table 1 Light Accent 4"/>\n<w:Lsd
	Exception Locked="false" Priority="47" Name="List Table 2 Accent 4"/>\n<w:
	LsdException Locked="false" Priority="48" Name="List Table 3 Accent 4"/>\n
	<w:LsdException Locked="false" Priority="49" Name="List Table 4 Accent 4"/
	>\n<w:LsdException Locked="false" Priority="50" Name="List Table 5 Dark Ac
	cent 4"/>\n<w:LsdException Locked="false" Priority="51" Name="List Table 6
	 Colorful Accent 4"/>\n<w:LsdException Locked="false" Priority="52" Name="
	List Table 7 Colorful Accent 4"/>\n<w:LsdException Locked="false" Priority
	="46" Name="List Table 1 Light Accent 5"/>\n<w:LsdException Locked="false"
	 Priority="47" Name="List Table 2 Accent 5"/>\n<w:LsdException Locked="fal
	se" Priority="48" Name="List Table 3 Accent 5"/>\n<w:LsdException Locked="
	false" Priority="49" Name="List Table 4 Accent 5"/>\n<w:LsdException Locke
	d="false" Priority="50" Name="List Table 5 Dark Accent 5"/>\n<w:LsdExcepti
	on Locked="false" Priority="51" Name="List Table 6 Colorful Accent 5"/>\n<
	w:LsdException Locked="false" Priority="52" Name="List Table 7 Colorful Ac
	cent 5"/>\n<w:LsdException Locked="false" Priority="46" Name="List Table 1
	 Light Accent 6"/>\n<w:LsdException Locked="false" Priority="47" Name="Lis
	t Table 2 Accent 6"/>\n<w:LsdException Locked="false" Priority="48" Name="
	List Table 3 Accent 6"/>\n<w:LsdException Locked="false" Priority="49" Nam
	e="List Table 4 Accent 6"/>\n<w:LsdException Locked="false" Priority="50" 
	Name="List Table 5 Dark Accent 6"/>\n<w:LsdException Locked="false" Priori
	ty="51" Name="List Table 6 Colorful Accent 6"/>\n<w:LsdException Locked="f
	alse" Priority="52" Name="List Table 7 Colorful Accent 6"/>\n<w:LsdExcepti
	on Locked="false" SemiHidden="true" UnhideWhenUsed="true" Name="Mention"/>
	\n<w:LsdException Locked="false" SemiHidden="true" UnhideWhenUsed="true" N
	ame="Smart Hyperlink"/>\n<w:LsdException Locked="false" SemiHidden="true" 
	UnhideWhenUsed="true" Name="Hashtag"/>\n<w:LsdException Locked="false" Sem
	iHidden="true" UnhideWhenUsed="true" Name="Unresolved Mention"/>\n<w:LsdEx
	ception Locked="false" SemiHidden="true" UnhideWhenUsed="true" Name="Smart
	 Link"/>\n</w:LatentStyles>\n</xml><![endif]--><style><!--\n/* Font Defini
	tions */\n@font-face\n	{font-family:"Cambria Math"\;\n	panose-1:2 4 5 3 5 
	4 6 3 2 4\;\n	mso-font-charset:0\;\n	mso-generic-font-family:roman\;\n	mso
	-font-pitch:variable\;\n	mso-font-signature:-536869121 1107305727 33554432
	 0 415 0\;}\n@font-face\n	{font-family:DengXian\;\n	panose-1:2 1 6 0 3 1 1
	 1 1 1\;\n	mso-font-alt:\\7B49\\7EBF\;\n	mso-font-charset:134\;\n	mso-gene
	ric-font-family:auto\;\n	mso-font-pitch:variable\;\n	mso-font-signature:-1
	610612033 953122042 22 0 262159 0\;}\n@font-face\n	{font-family:Calibri\;\
	n	panose-1:2 15 5 2 2 2 4 3 2 4\;\n	mso-font-charset:0\;\n	mso-generic-fon
	t-family:swiss\;\n	mso-font-pitch:variable\;\n	mso-font-signature:-4697500
	17 -1040178053 9 0 511 0\;}\n@font-face\n	{font-family:"Segoe UI"\;\n	pano
	se-1:2 11 5 2 4 2 4 2 2 3\;\n	mso-font-charset:0\;\n	mso-generic-font-fami
	ly:swiss\;\n	mso-font-pitch:variable\;\n	mso-font-signature:-469750017 -10
	73683329 9 0 511 0\;}\n@font-face\n	{font-family:"Microsoft JhengHei"\;\n	
	panose-1:2 11 6 4 3 5 4 4 2 4\;\n	mso-font-charset:136\;\n	mso-generic-fon
	t-family:swiss\;\n	mso-font-pitch:variable\;\n	mso-font-signature:679 6846
	72000 22 0 1048585 0\;}\n@font-face\n	{font-family:"\\@Microsoft JhengHei"
	\;\n	mso-font-charset:136\;\n	mso-generic-font-family:swiss\;\n	mso-font-p
	itch:variable\;\n	mso-font-signature:679 684672000 22 0 1048585 0\;}\n@fon
	t-face\n	{font-family:"Segoe UI Semibold"\;\n	panose-1:2 11 7 2 4 2 4 2 2 
	3\;\n	mso-font-charset:0\;\n	mso-generic-font-family:swiss\;\n	mso-font-pi
	tch:variable\;\n	mso-font-signature:-469750017 -1073683329 9 0 511 0\;}\n@
	font-face\n	{font-family:"\\@DengXian"\;\n	panose-1:2 1 6 0 3 1 1 1 1 1\;\
	n	mso-font-charset:134\;\n	mso-generic-font-family:auto\;\n	mso-font-pitch
	:variable\;\n	mso-font-signature:-1610612033 953122042 22 0 262159 0\;}\n/
	* Style Definitions */\np.MsoNormal\, li.MsoNormal\, div.MsoNormal\n	{mso-
	style-unhide:no\;\n	mso-style-qformat:yes\;\n	mso-style-parent:""\;\n	marg
	in:0in\;\n	mso-pagination:widow-orphan\;\n	font-size:11.0pt\;\n	font-famil
	y:"Calibri"\,sans-serif\;\n	mso-ascii-font-family:Calibri\;\n	mso-fareast-
	font-family:DengXian\;\n	mso-hansi-font-family:Calibri\;\n	mso-bidi-font-f
	amily:"Times New Roman"\;}\na:link\, span.MsoHyperlink\n	{mso-style-noshow
	:yes\;\n	mso-style-priority:99\;\n	color:#0563C1\;\n	text-decoration:under
	line\;\n	text-underline:single\;}\na:visited\, span.MsoHyperlinkFollowed\n
		{mso-style-noshow:yes\;\n	mso-style-priority:99\;\n	color:#954F72\;\n	tex
	t-decoration:underline\;\n	text-underline:single\;}\nspan.EmailStyle17\n	{
	mso-style-type:personal-compose\;\n	mso-style-noshow:yes\;\n	mso-style-unh
	ide:no\;\n	mso-ansi-font-size:11.0pt\;\n	mso-bidi-font-size:11.0pt\;\n	fon
	t-family:"Calibri"\,sans-serif\;\n	mso-ascii-font-family:Calibri\;\n	mso-f
	areast-font-family:DengXian\;\n	mso-hansi-font-family:Calibri\;\n	mso-bidi
	-font-family:"Times New Roman"\;\n	color:windowtext\;}\nspan.SpellE\n	{mso
	-style-name:""\;\n	mso-spl-e:yes\;}\nspan.GramE\n	{mso-style-name:""\;\n	m
	so-gram-e:yes\;}\n.MsoChpDefault\n	{mso-style-type:export-only\;\n	mso-def
	ault-props:yes\;\n	font-family:"Calibri"\,sans-serif\;\n	mso-ascii-font-fa
	mily:Calibri\;\n	mso-fareast-font-family:DengXian\;\n	mso-hansi-font-famil
	y:Calibri\;\n	mso-bidi-font-family:"Times New Roman"\;}\n@page WordSection
	1\n	{size:8.5in 11.0in\;\n	margin:1.0in 1.0in 1.0in 1.0in\;\n	mso-header-m
	argin:.5in\;\n	mso-footer-margin:.5in\;\n	mso-paper-source:0\;}\ndiv.WordS
	ection1\n	{page:WordSection1\;}\n--></style><!--[if gte mso 10]><style>/* 
	Style Definitions */\ntable.MsoNormalTable\n	{mso-style-name:"Table Normal
	"\;\n	mso-tstyle-rowband-size:0\;\n	mso-tstyle-colband-size:0\;\n	mso-styl
	e-noshow:yes\;\n	mso-style-priority:99\;\n	mso-style-parent:""\;\n	mso-pad
	ding-alt:0in 5.4pt 0in 5.4pt\;\n	mso-para-margin:0in\;\n	mso-pagination:wi
	dow-orphan\;\n	font-size:11.0pt\;\n	font-family:"Calibri"\,sans-serif\;\n	
	mso-ascii-font-family:Calibri\;\n	mso-hansi-font-family:Calibri\;\n	mso-bi
	di-font-family:"Times New Roman"\;}\n</style><![endif]--><!--[if gte mso 9
	]><xml>\n<o:shapedefaults v:ext="edit" spidmax="1026" />\n</xml><![endif]-
	-><!--[if gte mso 9]><xml>\n<o:shapelayout v:ext="edit">\n<o:idmap v:ext="
	edit" data="1" />\n</o:shapelayout></xml><![endif]--></head><body lang=EN-
	US link="#0563C1" vlink="#954F72" style='tab-interval:.5in\;word-wrap:brea
	k-word'><div class=WordSection1><p class=MsoNormal><o:p>&nbsp\;</o:p></p><
	div><p class=MsoNormal><span style='mso-fareast-font-family:"Times New Rom
	an"\;color:#5F5F5F'>______________________________________________________
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	Roman"\;color:#252424'>Microsoft Teams meeting</span><span style='font-fam
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	><div><p class=MsoNormal><b><span style='font-size:10.5pt\;font-family:"Se
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	TdmLTlkZmUtYThkNGQ0ZWYyMDZh%40thread.v2/0?context=%7b%22Tid%22%3a%2246c98d
	88-e344-4ed4-8496-4ed7712e255d%22%2c%22Oid%22%3a%2255d36a50-78be-4ced-bc27
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	style='margin-bottom:3.0pt'><p class=MsoNormal><span style='font-family:"S
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	d4-8496-4ed7712e255d&amp\;threadId=19_meeting_YTk4ZDU3YjItODkxZC00MTdmLTlk
	ZmUtYThkNGQ0ZWYyMDZh@thread.v2&amp\;messageId=0&amp\;language=en-US" targe
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	/o:p></span></p></div><p class=MsoNormal><o:p>&nbsp\;</o:p></p></div></bod
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X-MICROSOFT-CDO-BUSYSTATUS:BUSY
X-MICROSOFT-CDO-IMPORTANCE:1
X-MICROSOFT-DISALLOW-COUNTER:FALSE
X-MS-OLK-AUTOFILLLOCATION:FALSE
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^ permalink raw reply	[flat|nested] 26+ messages in thread

* Re: [edk2-devel] [PATCH v1 1/1] ArmPkg: CpuDxe: Sync GCD Capabilities With Page Table Attributes
  2023-05-17  7:14                             ` Ni, Ray
@ 2023-06-02  2:24                               ` Michael Kubacki
  2023-06-02  2:42                                 ` Ni, Ray
  0 siblings, 1 reply; 26+ messages in thread
From: Michael Kubacki @ 2023-06-02  2:24 UTC (permalink / raw)
  To: Ni, Ray, Oliver Smith-Denny, devel@edk2.groups.io, Ard Biesheuvel,
	Kinney, Michael D, t@taylorbeebe.com
  Cc: Leif Lindholm, Ard Biesheuvel, Sami Mujawar, Sean Brogan

Hi Ray,

We found the last meeting to be very helpful. Can you please set up an 
agenda for an upcoming meeting to discuss what's happened since and next 
steps?

If you're available, perhaps we could see if Wednesday next week at the 
same time would work?

We'd also like to share how GitHub Projects [1] can be used to track 
future work in the memory protection work stream. We've talked about 
Projects for a while in the TianoCore Tools & CI working group and this 
looks like a great opportunity to try it out. A public project has been 
created in the TianoCore org [2]. I've placed some initial high-level 
pillars in the project at the moment.

Projects can help break down larger complex items and show how the 
pieces fit together in a single place. It helps visualize who is working 
on what, when they roughly expect to complete it, and what pillars of 
memory protection work such as compatibility, testing, etc. are defined 
and how we're making progress toward them. In this meeting, we'd like to 
discuss how we can most effectively use it to collaborate in upcoming 
work areas.

It is not meant to replace the mailing list for communication or change 
code review process but to organize and visualize agreed upon memory 
protection work items. Ideally, this will help track that the areas are 
covered we expect, simplify planning to intercept the changes in 
platforms, show how work items are connected, and enable new 
contributors to quickly see how they can contribute.

[1] - 
https://docs.github.com/en/issues/planning-and-tracking-with-projects/learning-about-projects/about-projects
[2] - https://github.com/orgs/tianocore/projects/3

Thanks,
Michael

On 5/17/2023 3:14 AM, Ni, Ray wrote:
> I created one event in https://edk2.groups.io/g/devel/calendar.
> 
> Microsoft Teams meeting link: https://teams.microsoft.com/l/meetup-join/19%3ameeting_YTk4ZDU3YjItODkxZC00MTdmLTlkZmUtYThkNGQ0ZWYyMDZh%40thread.v2/0?context=%7b%22Tid%22%3a%2246c98d88-e344-4ed4-8496-4ed7712e255d%22%2c%22Oid%22%3a%2255d36a50-78be-4ced-bc27-3d06c576cc19%22%7d
> 
> The ICS file is also attached.
> 
> 
>> -----Original Message-----
>> From: Oliver Smith-Denny <osde@linux.microsoft.com>
>> Sent: Wednesday, May 17, 2023 1:12 AM
>> To: Ni, Ray <ray.ni@intel.com>; devel@edk2.groups.io; Ard Biesheuvel
>> <ardb@kernel.org>; Kinney, Michael D <michael.d.kinney@intel.com>;
>> t@taylorbeebe.com
>> Cc: Leif Lindholm <quic_llindhol@quicinc.com>; Ard Biesheuvel
>> <ardb+tianocore@kernel.org>; Sami Mujawar <sami.mujawar@arm.com>;
>> Michael Kubacki <mikuback@linux.microsoft.com>; Sean Brogan
>> <sean.brogan@microsoft.com>
>> Subject: Re: [edk2-devel] [PATCH v1 1/1] ArmPkg: CpuDxe: Sync GCD Capabilities
>> With Page Table Attributes
>>
>> Hi Ray,
>>
>> That works from our side, thanks for setting up the meeting!
>>
>> Oliver
>>
>> On 5/15/2023 7:53 PM, Ni, Ray wrote:
>>> All,
>>> Can you check if the meeting time is ok for you?
>>>
>>> It will be in this week:
>>> * PDT Wednesday 07:00
>>> * Paris Wednesday 16:00
>>> * Shanghai Wednesday 22:00
>>>
>>> ________________________________________
>>> From: devel@edk2.groups.io <devel@edk2.groups.io> on behalf of Taylor Beebe
>> <t@taylorbeebe.com>
>>> Sent: Thursday, May 11, 2023 0:10
>>> To: devel@edk2.groups.io; osde@linux.microsoft.com; Ard Biesheuvel; Kinney,
>> Michael D
>>> Cc: Ni, Ray; Leif Lindholm; Ard Biesheuvel; Sami Mujawar; Michael Kubacki;
>> Sean Brogan
>>> Subject: Re: [edk2-devel] [PATCH v1 1/1] ArmPkg: CpuDxe: Sync GCD
>> Capabilities With Page Table Attributes
>>>
>>> Can we schedule the meeting for Wednesday 5/17? I will be out the
>>> following week and would like to attend.
>>>
>>> Thanks :)
>>>
>>> On 5/9/2023 7:59 AM, Oliver Smith-Denny wrote:
>>>> On 5/8/2023 11:59 PM, Ard Biesheuvel wrote:
>>>>> On Tue, 9 May 2023 at 04:04, Kinney, Michael D
>>>>> <michael.d.kinney@intel.com> wrote:
>>>>>>
>>>>>> I would prefer next week as well.
>>>>>>
>>>>>> Mike
>>>>>>
>>>>>
>>>>> Next week, i can only do Wednesday. The week after (22-26), the time
>>>>> slot works for me on any day of the week.
>>>>>
>>>>
>>>> Weds works from our side, the week after also works perfectly well
>>>> any day. Thanks for the flexibility and willingness to meet.
>>>>
>>>> For reference for this specific patch, this bz may help cache in
>>>> some info: https://bugzilla.tianocore.org/show_bug.cgi?id=753. The
>>>> mail links are largely dead, of course, but can be found on other
>>>> mailing list retention sites (maybe in the future we will have PRs
>>>> and discussions to reference :).
>>>>
>>>> Thanks,
>>>> Oliver
>>>>
>>>>
>>>>
>>>>
>>>>
>>>
>>>
>>>
>>> 
>>>
>>>

^ permalink raw reply	[flat|nested] 26+ messages in thread

* Re: [edk2-devel] [PATCH v1 1/1] ArmPkg: CpuDxe: Sync GCD Capabilities With Page Table Attributes
  2023-06-02  2:24                               ` Michael Kubacki
@ 2023-06-02  2:42                                 ` Ni, Ray
  2023-06-02  3:09                                   ` Michael Kubacki
  0 siblings, 1 reply; 26+ messages in thread
From: Ni, Ray @ 2023-06-02  2:42 UTC (permalink / raw)
  To: Michael Kubacki, Oliver Smith-Denny, devel@edk2.groups.io,
	Ard Biesheuvel, Kinney, Michael D, t@taylorbeebe.com
  Cc: Leif Lindholm, Ard Biesheuvel, Sami Mujawar, Sean Brogan

It's a good idea to have a focus area ("project") for everyone working together on the same problem.
I see the benefit of having "project" is to align everyone's priority so the "project" can be done within a certain deadline.

Let's talk more about following items in next meeting:
1. Alignment of the problem to solve
2. Alignment of the priority

I am available at 10pm~11pm (GMT+8) next Wednesday night.

Thanks,
Ray

> -----Original Message-----
> From: Michael Kubacki <mikuback@linux.microsoft.com>
> Sent: Friday, June 2, 2023 10:24 AM
> To: Ni, Ray <ray.ni@intel.com>; Oliver Smith-Denny <osde@linux.microsoft.com>;
> devel@edk2.groups.io; Ard Biesheuvel <ardb@kernel.org>; Kinney, Michael D
> <michael.d.kinney@intel.com>; t@taylorbeebe.com
> Cc: Leif Lindholm <quic_llindhol@quicinc.com>; Ard Biesheuvel
> <ardb+tianocore@kernel.org>; Sami Mujawar <sami.mujawar@arm.com>; Sean
> Brogan <sean.brogan@microsoft.com>
> Subject: Re: [edk2-devel] [PATCH v1 1/1] ArmPkg: CpuDxe: Sync GCD Capabilities
> With Page Table Attributes
> 
> Hi Ray,
> 
> We found the last meeting to be very helpful. Can you please set up an
> agenda for an upcoming meeting to discuss what's happened since and next
> steps?
> 
> If you're available, perhaps we could see if Wednesday next week at the
> same time would work?
> 
> We'd also like to share how GitHub Projects [1] can be used to track
> future work in the memory protection work stream. We've talked about
> Projects for a while in the TianoCore Tools & CI working group and this
> looks like a great opportunity to try it out. A public project has been
> created in the TianoCore org [2]. I've placed some initial high-level
> pillars in the project at the moment.
> 
> Projects can help break down larger complex items and show how the
> pieces fit together in a single place. It helps visualize who is working
> on what, when they roughly expect to complete it, and what pillars of
> memory protection work such as compatibility, testing, etc. are defined
> and how we're making progress toward them. In this meeting, we'd like to
> discuss how we can most effectively use it to collaborate in upcoming
> work areas.
> 
> It is not meant to replace the mailing list for communication or change
> code review process but to organize and visualize agreed upon memory
> protection work items. Ideally, this will help track that the areas are
> covered we expect, simplify planning to intercept the changes in
> platforms, show how work items are connected, and enable new
> contributors to quickly see how they can contribute.
> 
> [1] -
> https://docs.github.com/en/issues/planning-and-tracking-with-projects/learning-
> about-projects/about-projects
> [2] - https://github.com/orgs/tianocore/projects/3
> 
> Thanks,
> Michael
> 
> On 5/17/2023 3:14 AM, Ni, Ray wrote:
> > I created one event in https://edk2.groups.io/g/devel/calendar.
> >
> > Microsoft Teams meeting link: https://teams.microsoft.com/l/meetup-
> join/19%3ameeting_YTk4ZDU3YjItODkxZC00MTdmLTlkZmUtYThkNGQ0ZWYyMDZ
> h%40thread.v2/0?context=%7b%22Tid%22%3a%2246c98d88-e344-4ed4-8496-
> 4ed7712e255d%22%2c%22Oid%22%3a%2255d36a50-78be-4ced-bc27-
> 3d06c576cc19%22%7d
> >
> > The ICS file is also attached.
> >
> >
> >> -----Original Message-----
> >> From: Oliver Smith-Denny <osde@linux.microsoft.com>
> >> Sent: Wednesday, May 17, 2023 1:12 AM
> >> To: Ni, Ray <ray.ni@intel.com>; devel@edk2.groups.io; Ard Biesheuvel
> >> <ardb@kernel.org>; Kinney, Michael D <michael.d.kinney@intel.com>;
> >> t@taylorbeebe.com
> >> Cc: Leif Lindholm <quic_llindhol@quicinc.com>; Ard Biesheuvel
> >> <ardb+tianocore@kernel.org>; Sami Mujawar <sami.mujawar@arm.com>;
> >> Michael Kubacki <mikuback@linux.microsoft.com>; Sean Brogan
> >> <sean.brogan@microsoft.com>
> >> Subject: Re: [edk2-devel] [PATCH v1 1/1] ArmPkg: CpuDxe: Sync GCD
> Capabilities
> >> With Page Table Attributes
> >>
> >> Hi Ray,
> >>
> >> That works from our side, thanks for setting up the meeting!
> >>
> >> Oliver
> >>
> >> On 5/15/2023 7:53 PM, Ni, Ray wrote:
> >>> All,
> >>> Can you check if the meeting time is ok for you?
> >>>
> >>> It will be in this week:
> >>> * PDT Wednesday 07:00
> >>> * Paris Wednesday 16:00
> >>> * Shanghai Wednesday 22:00
> >>>
> >>> ________________________________________
> >>> From: devel@edk2.groups.io <devel@edk2.groups.io> on behalf of Taylor
> Beebe
> >> <t@taylorbeebe.com>
> >>> Sent: Thursday, May 11, 2023 0:10
> >>> To: devel@edk2.groups.io; osde@linux.microsoft.com; Ard Biesheuvel;
> Kinney,
> >> Michael D
> >>> Cc: Ni, Ray; Leif Lindholm; Ard Biesheuvel; Sami Mujawar; Michael Kubacki;
> >> Sean Brogan
> >>> Subject: Re: [edk2-devel] [PATCH v1 1/1] ArmPkg: CpuDxe: Sync GCD
> >> Capabilities With Page Table Attributes
> >>>
> >>> Can we schedule the meeting for Wednesday 5/17? I will be out the
> >>> following week and would like to attend.
> >>>
> >>> Thanks :)
> >>>
> >>> On 5/9/2023 7:59 AM, Oliver Smith-Denny wrote:
> >>>> On 5/8/2023 11:59 PM, Ard Biesheuvel wrote:
> >>>>> On Tue, 9 May 2023 at 04:04, Kinney, Michael D
> >>>>> <michael.d.kinney@intel.com> wrote:
> >>>>>>
> >>>>>> I would prefer next week as well.
> >>>>>>
> >>>>>> Mike
> >>>>>>
> >>>>>
> >>>>> Next week, i can only do Wednesday. The week after (22-26), the time
> >>>>> slot works for me on any day of the week.
> >>>>>
> >>>>
> >>>> Weds works from our side, the week after also works perfectly well
> >>>> any day. Thanks for the flexibility and willingness to meet.
> >>>>
> >>>> For reference for this specific patch, this bz may help cache in
> >>>> some info: https://bugzilla.tianocore.org/show_bug.cgi?id=753. The
> >>>> mail links are largely dead, of course, but can be found on other
> >>>> mailing list retention sites (maybe in the future we will have PRs
> >>>> and discussions to reference :).
> >>>>
> >>>> Thanks,
> >>>> Oliver
> >>>>
> >>>>
> >>>>
> >>>>
> >>>>
> >>>
> >>>
> >>>
> >>> 
> >>>
> >>>

^ permalink raw reply	[flat|nested] 26+ messages in thread

* Re: [edk2-devel] [PATCH v1 1/1] ArmPkg: CpuDxe: Sync GCD Capabilities With Page Table Attributes
  2023-06-02  2:42                                 ` Ni, Ray
@ 2023-06-02  3:09                                   ` Michael Kubacki
  2023-06-02  9:31                                     ` Ard Biesheuvel
  2023-06-06  2:13                                     ` Michael Kubacki
  0 siblings, 2 replies; 26+ messages in thread
From: Michael Kubacki @ 2023-06-02  3:09 UTC (permalink / raw)
  To: Ni, Ray, Oliver Smith-Denny, devel@edk2.groups.io, Ard Biesheuvel,
	Kinney, Michael D, t@taylorbeebe.com
  Cc: Leif Lindholm, Ard Biesheuvel, Sami Mujawar, Sean Brogan

Sounds good, thanks for the quick response. Can you please send a 
calendar invite when you get a chance?

On 6/1/2023 10:42 PM, Ni, Ray wrote:
> It's a good idea to have a focus area ("project") for everyone working together on the same problem.
> I see the benefit of having "project" is to align everyone's priority so the "project" can be done within a certain deadline.
> 
> Let's talk more about following items in next meeting:
> 1. Alignment of the problem to solve
> 2. Alignment of the priority
> 
> I am available at 10pm~11pm (GMT+8) next Wednesday night.
> 
> Thanks,
> Ray
> 
>> -----Original Message-----
>> From: Michael Kubacki <mikuback@linux.microsoft.com>
>> Sent: Friday, June 2, 2023 10:24 AM
>> To: Ni, Ray <ray.ni@intel.com>; Oliver Smith-Denny <osde@linux.microsoft.com>;
>> devel@edk2.groups.io; Ard Biesheuvel <ardb@kernel.org>; Kinney, Michael D
>> <michael.d.kinney@intel.com>; t@taylorbeebe.com
>> Cc: Leif Lindholm <quic_llindhol@quicinc.com>; Ard Biesheuvel
>> <ardb+tianocore@kernel.org>; Sami Mujawar <sami.mujawar@arm.com>; Sean
>> Brogan <sean.brogan@microsoft.com>
>> Subject: Re: [edk2-devel] [PATCH v1 1/1] ArmPkg: CpuDxe: Sync GCD Capabilities
>> With Page Table Attributes
>>
>> Hi Ray,
>>
>> We found the last meeting to be very helpful. Can you please set up an
>> agenda for an upcoming meeting to discuss what's happened since and next
>> steps?
>>
>> If you're available, perhaps we could see if Wednesday next week at the
>> same time would work?
>>
>> We'd also like to share how GitHub Projects [1] can be used to track
>> future work in the memory protection work stream. We've talked about
>> Projects for a while in the TianoCore Tools & CI working group and this
>> looks like a great opportunity to try it out. A public project has been
>> created in the TianoCore org [2]. I've placed some initial high-level
>> pillars in the project at the moment.
>>
>> Projects can help break down larger complex items and show how the
>> pieces fit together in a single place. It helps visualize who is working
>> on what, when they roughly expect to complete it, and what pillars of
>> memory protection work such as compatibility, testing, etc. are defined
>> and how we're making progress toward them. In this meeting, we'd like to
>> discuss how we can most effectively use it to collaborate in upcoming
>> work areas.
>>
>> It is not meant to replace the mailing list for communication or change
>> code review process but to organize and visualize agreed upon memory
>> protection work items. Ideally, this will help track that the areas are
>> covered we expect, simplify planning to intercept the changes in
>> platforms, show how work items are connected, and enable new
>> contributors to quickly see how they can contribute.
>>
>> [1] -
>> https://docs.github.com/en/issues/planning-and-tracking-with-projects/learning-
>> about-projects/about-projects
>> [2] - https://github.com/orgs/tianocore/projects/3
>>
>> Thanks,
>> Michael
>>
>> On 5/17/2023 3:14 AM, Ni, Ray wrote:
>>> I created one event in https://edk2.groups.io/g/devel/calendar.
>>>
>>> Microsoft Teams meeting link: https://teams.microsoft.com/l/meetup-
>> join/19%3ameeting_YTk4ZDU3YjItODkxZC00MTdmLTlkZmUtYThkNGQ0ZWYyMDZ
>> h%40thread.v2/0?context=%7b%22Tid%22%3a%2246c98d88-e344-4ed4-8496-
>> 4ed7712e255d%22%2c%22Oid%22%3a%2255d36a50-78be-4ced-bc27-
>> 3d06c576cc19%22%7d
>>>
>>> The ICS file is also attached.
>>>
>>>
>>>> -----Original Message-----
>>>> From: Oliver Smith-Denny <osde@linux.microsoft.com>
>>>> Sent: Wednesday, May 17, 2023 1:12 AM
>>>> To: Ni, Ray <ray.ni@intel.com>; devel@edk2.groups.io; Ard Biesheuvel
>>>> <ardb@kernel.org>; Kinney, Michael D <michael.d.kinney@intel.com>;
>>>> t@taylorbeebe.com
>>>> Cc: Leif Lindholm <quic_llindhol@quicinc.com>; Ard Biesheuvel
>>>> <ardb+tianocore@kernel.org>; Sami Mujawar <sami.mujawar@arm.com>;
>>>> Michael Kubacki <mikuback@linux.microsoft.com>; Sean Brogan
>>>> <sean.brogan@microsoft.com>
>>>> Subject: Re: [edk2-devel] [PATCH v1 1/1] ArmPkg: CpuDxe: Sync GCD
>> Capabilities
>>>> With Page Table Attributes
>>>>
>>>> Hi Ray,
>>>>
>>>> That works from our side, thanks for setting up the meeting!
>>>>
>>>> Oliver
>>>>
>>>> On 5/15/2023 7:53 PM, Ni, Ray wrote:
>>>>> All,
>>>>> Can you check if the meeting time is ok for you?
>>>>>
>>>>> It will be in this week:
>>>>> * PDT Wednesday 07:00
>>>>> * Paris Wednesday 16:00
>>>>> * Shanghai Wednesday 22:00
>>>>>
>>>>> ________________________________________
>>>>> From: devel@edk2.groups.io <devel@edk2.groups.io> on behalf of Taylor
>> Beebe
>>>> <t@taylorbeebe.com>
>>>>> Sent: Thursday, May 11, 2023 0:10
>>>>> To: devel@edk2.groups.io; osde@linux.microsoft.com; Ard Biesheuvel;
>> Kinney,
>>>> Michael D
>>>>> Cc: Ni, Ray; Leif Lindholm; Ard Biesheuvel; Sami Mujawar; Michael Kubacki;
>>>> Sean Brogan
>>>>> Subject: Re: [edk2-devel] [PATCH v1 1/1] ArmPkg: CpuDxe: Sync GCD
>>>> Capabilities With Page Table Attributes
>>>>>
>>>>> Can we schedule the meeting for Wednesday 5/17? I will be out the
>>>>> following week and would like to attend.
>>>>>
>>>>> Thanks :)
>>>>>
>>>>> On 5/9/2023 7:59 AM, Oliver Smith-Denny wrote:
>>>>>> On 5/8/2023 11:59 PM, Ard Biesheuvel wrote:
>>>>>>> On Tue, 9 May 2023 at 04:04, Kinney, Michael D
>>>>>>> <michael.d.kinney@intel.com> wrote:
>>>>>>>>
>>>>>>>> I would prefer next week as well.
>>>>>>>>
>>>>>>>> Mike
>>>>>>>>
>>>>>>>
>>>>>>> Next week, i can only do Wednesday. The week after (22-26), the time
>>>>>>> slot works for me on any day of the week.
>>>>>>>
>>>>>>
>>>>>> Weds works from our side, the week after also works perfectly well
>>>>>> any day. Thanks for the flexibility and willingness to meet.
>>>>>>
>>>>>> For reference for this specific patch, this bz may help cache in
>>>>>> some info: https://bugzilla.tianocore.org/show_bug.cgi?id=753. The
>>>>>> mail links are largely dead, of course, but can be found on other
>>>>>> mailing list retention sites (maybe in the future we will have PRs
>>>>>> and discussions to reference :).
>>>>>>
>>>>>> Thanks,
>>>>>> Oliver
>>>>>>
>>>>>>
>>>>>>
>>>>>>
>>>>>>
>>>>>
>>>>>
>>>>>
>>>>> 
>>>>>
>>>>>

^ permalink raw reply	[flat|nested] 26+ messages in thread

* Re: [edk2-devel] [PATCH v1 1/1] ArmPkg: CpuDxe: Sync GCD Capabilities With Page Table Attributes
  2023-06-02  3:09                                   ` Michael Kubacki
@ 2023-06-02  9:31                                     ` Ard Biesheuvel
  2023-06-06  2:13                                     ` Michael Kubacki
  1 sibling, 0 replies; 26+ messages in thread
From: Ard Biesheuvel @ 2023-06-02  9:31 UTC (permalink / raw)
  To: devel, mikuback
  Cc: Ni, Ray, Oliver Smith-Denny, Kinney, Michael D, t@taylorbeebe.com,
	Leif Lindholm, Ard Biesheuvel, Sami Mujawar, Sean Brogan

On Fri, 2 Jun 2023 at 05:10, Michael Kubacki
<mikuback@linux.microsoft.com> wrote:
>
> Sounds good, thanks for the quick response. Can you please send a
> calendar invite when you get a chance?
>
> On 6/1/2023 10:42 PM, Ni, Ray wrote:
> > It's a good idea to have a focus area ("project") for everyone working together on the same problem.
> > I see the benefit of having "project" is to align everyone's priority so the "project" can be done within a certain deadline.
> >
> > Let's talk more about following items in next meeting:
> > 1. Alignment of the problem to solve
> > 2. Alignment of the priority
> >
> > I am available at 10pm~11pm (GMT+8) next Wednesday night.
> >

This works for me as well.

^ permalink raw reply	[flat|nested] 26+ messages in thread

* Re: [edk2-devel] [PATCH v1 1/1] ArmPkg: CpuDxe: Sync GCD Capabilities With Page Table Attributes
  2023-06-02  3:09                                   ` Michael Kubacki
  2023-06-02  9:31                                     ` Ard Biesheuvel
@ 2023-06-06  2:13                                     ` Michael Kubacki
  2023-06-06  3:00                                       ` Ni, Ray
  1 sibling, 1 reply; 26+ messages in thread
From: Michael Kubacki @ 2023-06-06  2:13 UTC (permalink / raw)
  To: Ni, Ray, devel@edk2.groups.io
  Cc: Leif Lindholm, Ard Biesheuvel, Sami Mujawar, Sean Brogan,
	Oliver Smith-Denny, Ard Biesheuvel, Kinney, Michael D,
	t@taylorbeebe.com

Hi Ray,

I still haven't seen a calendar invitation. Could you please send one 
for us to reserve the slot on our calendars?

Thanks,
Michael

On 6/1/2023 11:09 PM, Michael Kubacki wrote:
> Sounds good, thanks for the quick response. Can you please send a 
> calendar invite when you get a chance?
> 
> On 6/1/2023 10:42 PM, Ni, Ray wrote:
>> It's a good idea to have a focus area ("project") for everyone working 
>> together on the same problem.
>> I see the benefit of having "project" is to align everyone's priority 
>> so the "project" can be done within a certain deadline.
>>
>> Let's talk more about following items in next meeting:
>> 1. Alignment of the problem to solve
>> 2. Alignment of the priority
>>
>> I am available at 10pm~11pm (GMT+8) next Wednesday night.
>>
>> Thanks,
>> Ray
>>
>>> -----Original Message-----
>>> From: Michael Kubacki <mikuback@linux.microsoft.com>
>>> Sent: Friday, June 2, 2023 10:24 AM
>>> To: Ni, Ray <ray.ni@intel.com>; Oliver Smith-Denny 
>>> <osde@linux.microsoft.com>;
>>> devel@edk2.groups.io; Ard Biesheuvel <ardb@kernel.org>; Kinney, 
>>> Michael D
>>> <michael.d.kinney@intel.com>; t@taylorbeebe.com
>>> Cc: Leif Lindholm <quic_llindhol@quicinc.com>; Ard Biesheuvel
>>> <ardb+tianocore@kernel.org>; Sami Mujawar <sami.mujawar@arm.com>; Sean
>>> Brogan <sean.brogan@microsoft.com>
>>> Subject: Re: [edk2-devel] [PATCH v1 1/1] ArmPkg: CpuDxe: Sync GCD 
>>> Capabilities
>>> With Page Table Attributes
>>>
>>> Hi Ray,
>>>
>>> We found the last meeting to be very helpful. Can you please set up an
>>> agenda for an upcoming meeting to discuss what's happened since and next
>>> steps?
>>>
>>> If you're available, perhaps we could see if Wednesday next week at the
>>> same time would work?
>>>
>>> We'd also like to share how GitHub Projects [1] can be used to track
>>> future work in the memory protection work stream. We've talked about
>>> Projects for a while in the TianoCore Tools & CI working group and this
>>> looks like a great opportunity to try it out. A public project has been
>>> created in the TianoCore org [2]. I've placed some initial high-level
>>> pillars in the project at the moment.
>>>
>>> Projects can help break down larger complex items and show how the
>>> pieces fit together in a single place. It helps visualize who is working
>>> on what, when they roughly expect to complete it, and what pillars of
>>> memory protection work such as compatibility, testing, etc. are defined
>>> and how we're making progress toward them. In this meeting, we'd like to
>>> discuss how we can most effectively use it to collaborate in upcoming
>>> work areas.
>>>
>>> It is not meant to replace the mailing list for communication or change
>>> code review process but to organize and visualize agreed upon memory
>>> protection work items. Ideally, this will help track that the areas are
>>> covered we expect, simplify planning to intercept the changes in
>>> platforms, show how work items are connected, and enable new
>>> contributors to quickly see how they can contribute.
>>>
>>> [1] -
>>> https://docs.github.com/en/issues/planning-and-tracking-with-projects/learning-
>>> about-projects/about-projects
>>> [2] - https://github.com/orgs/tianocore/projects/3
>>>
>>> Thanks,
>>> Michael
>>>
>>> On 5/17/2023 3:14 AM, Ni, Ray wrote:
>>>> I created one event in https://edk2.groups.io/g/devel/calendar.
>>>>
>>>> Microsoft Teams meeting link: https://teams.microsoft.com/l/meetup-
>>> join/19%3ameeting_YTk4ZDU3YjItODkxZC00MTdmLTlkZmUtYThkNGQ0ZWYyMDZ
>>> h%40thread.v2/0?context=%7b%22Tid%22%3a%2246c98d88-e344-4ed4-8496-
>>> 4ed7712e255d%22%2c%22Oid%22%3a%2255d36a50-78be-4ced-bc27-
>>> 3d06c576cc19%22%7d
>>>>
>>>> The ICS file is also attached.
>>>>
>>>>
>>>>> -----Original Message-----
>>>>> From: Oliver Smith-Denny <osde@linux.microsoft.com>
>>>>> Sent: Wednesday, May 17, 2023 1:12 AM
>>>>> To: Ni, Ray <ray.ni@intel.com>; devel@edk2.groups.io; Ard Biesheuvel
>>>>> <ardb@kernel.org>; Kinney, Michael D <michael.d.kinney@intel.com>;
>>>>> t@taylorbeebe.com
>>>>> Cc: Leif Lindholm <quic_llindhol@quicinc.com>; Ard Biesheuvel
>>>>> <ardb+tianocore@kernel.org>; Sami Mujawar <sami.mujawar@arm.com>;
>>>>> Michael Kubacki <mikuback@linux.microsoft.com>; Sean Brogan
>>>>> <sean.brogan@microsoft.com>
>>>>> Subject: Re: [edk2-devel] [PATCH v1 1/1] ArmPkg: CpuDxe: Sync GCD
>>> Capabilities
>>>>> With Page Table Attributes
>>>>>
>>>>> Hi Ray,
>>>>>
>>>>> That works from our side, thanks for setting up the meeting!
>>>>>
>>>>> Oliver
>>>>>
>>>>> On 5/15/2023 7:53 PM, Ni, Ray wrote:
>>>>>> All,
>>>>>> Can you check if the meeting time is ok for you?
>>>>>>
>>>>>> It will be in this week:
>>>>>> * PDT Wednesday 07:00
>>>>>> * Paris Wednesday 16:00
>>>>>> * Shanghai Wednesday 22:00
>>>>>>
>>>>>> ________________________________________
>>>>>> From: devel@edk2.groups.io <devel@edk2.groups.io> on behalf of Taylor
>>> Beebe
>>>>> <t@taylorbeebe.com>
>>>>>> Sent: Thursday, May 11, 2023 0:10
>>>>>> To: devel@edk2.groups.io; osde@linux.microsoft.com; Ard Biesheuvel;
>>> Kinney,
>>>>> Michael D
>>>>>> Cc: Ni, Ray; Leif Lindholm; Ard Biesheuvel; Sami Mujawar; Michael 
>>>>>> Kubacki;
>>>>> Sean Brogan
>>>>>> Subject: Re: [edk2-devel] [PATCH v1 1/1] ArmPkg: CpuDxe: Sync GCD
>>>>> Capabilities With Page Table Attributes
>>>>>>
>>>>>> Can we schedule the meeting for Wednesday 5/17? I will be out the
>>>>>> following week and would like to attend.
>>>>>>
>>>>>> Thanks :)
>>>>>>
>>>>>> On 5/9/2023 7:59 AM, Oliver Smith-Denny wrote:
>>>>>>> On 5/8/2023 11:59 PM, Ard Biesheuvel wrote:
>>>>>>>> On Tue, 9 May 2023 at 04:04, Kinney, Michael D
>>>>>>>> <michael.d.kinney@intel.com> wrote:
>>>>>>>>>
>>>>>>>>> I would prefer next week as well.
>>>>>>>>>
>>>>>>>>> Mike
>>>>>>>>>
>>>>>>>>
>>>>>>>> Next week, i can only do Wednesday. The week after (22-26), the 
>>>>>>>> time
>>>>>>>> slot works for me on any day of the week.
>>>>>>>>
>>>>>>>
>>>>>>> Weds works from our side, the week after also works perfectly well
>>>>>>> any day. Thanks for the flexibility and willingness to meet.
>>>>>>>
>>>>>>> For reference for this specific patch, this bz may help cache in
>>>>>>> some info: https://bugzilla.tianocore.org/show_bug.cgi?id=753. The
>>>>>>> mail links are largely dead, of course, but can be found on other
>>>>>>> mailing list retention sites (maybe in the future we will have PRs
>>>>>>> and discussions to reference :).
>>>>>>>
>>>>>>> Thanks,
>>>>>>> Oliver
>>>>>>>
>>>>>>>
>>>>>>>
>>>>>>>
>>>>>>>
>>>>>>
>>>>>>
>>>>>>
>>>>>> 
>>>>>>
>>>>>>

^ permalink raw reply	[flat|nested] 26+ messages in thread

* Re: [edk2-devel] [PATCH v1 1/1] ArmPkg: CpuDxe: Sync GCD Capabilities With Page Table Attributes
  2023-06-06  2:13                                     ` Michael Kubacki
@ 2023-06-06  3:00                                       ` Ni, Ray
  0 siblings, 0 replies; 26+ messages in thread
From: Ni, Ray @ 2023-06-06  3:00 UTC (permalink / raw)
  To: devel@edk2.groups.io, mikuback@linux.microsoft.com
  Cc: Leif Lindholm, Ard Biesheuvel, Sami Mujawar, Sean Brogan,
	Oliver Smith-Denny, Ard Biesheuvel, Kinney, Michael D,
	t@taylorbeebe.com

[-- Attachment #1: Type: text/plain, Size: 7838 bytes --]

I just set it up.
It's in https://edk2.groups.io/g/devel/calendar, also in attachment.

> -----Original Message-----
> From: devel@edk2.groups.io <devel@edk2.groups.io> On Behalf Of Michael
> Kubacki
> Sent: Tuesday, June 6, 2023 10:14 AM
> To: Ni, Ray <ray.ni@intel.com>; devel@edk2.groups.io
> Cc: Leif Lindholm <quic_llindhol@quicinc.com>; Ard Biesheuvel
> <ardb+tianocore@kernel.org>; Sami Mujawar <sami.mujawar@arm.com>; Sean
> Brogan <sean.brogan@microsoft.com>; Oliver Smith-Denny
> <osde@linux.microsoft.com>; Ard Biesheuvel <ardb@kernel.org>; Kinney,
> Michael D <michael.d.kinney@intel.com>; t@taylorbeebe.com
> Subject: Re: [edk2-devel] [PATCH v1 1/1] ArmPkg: CpuDxe: Sync GCD Capabilities
> With Page Table Attributes
> 
> Hi Ray,
> 
> I still haven't seen a calendar invitation. Could you please send one
> for us to reserve the slot on our calendars?
> 
> Thanks,
> Michael
> 
> On 6/1/2023 11:09 PM, Michael Kubacki wrote:
> > Sounds good, thanks for the quick response. Can you please send a
> > calendar invite when you get a chance?
> >
> > On 6/1/2023 10:42 PM, Ni, Ray wrote:
> >> It's a good idea to have a focus area ("project") for everyone working
> >> together on the same problem.
> >> I see the benefit of having "project" is to align everyone's priority
> >> so the "project" can be done within a certain deadline.
> >>
> >> Let's talk more about following items in next meeting:
> >> 1. Alignment of the problem to solve
> >> 2. Alignment of the priority
> >>
> >> I am available at 10pm~11pm (GMT+8) next Wednesday night.
> >>
> >> Thanks,
> >> Ray
> >>
> >>> -----Original Message-----
> >>> From: Michael Kubacki <mikuback@linux.microsoft.com>
> >>> Sent: Friday, June 2, 2023 10:24 AM
> >>> To: Ni, Ray <ray.ni@intel.com>; Oliver Smith-Denny
> >>> <osde@linux.microsoft.com>;
> >>> devel@edk2.groups.io; Ard Biesheuvel <ardb@kernel.org>; Kinney,
> >>> Michael D
> >>> <michael.d.kinney@intel.com>; t@taylorbeebe.com
> >>> Cc: Leif Lindholm <quic_llindhol@quicinc.com>; Ard Biesheuvel
> >>> <ardb+tianocore@kernel.org>; Sami Mujawar <sami.mujawar@arm.com>;
> Sean
> >>> Brogan <sean.brogan@microsoft.com>
> >>> Subject: Re: [edk2-devel] [PATCH v1 1/1] ArmPkg: CpuDxe: Sync GCD
> >>> Capabilities
> >>> With Page Table Attributes
> >>>
> >>> Hi Ray,
> >>>
> >>> We found the last meeting to be very helpful. Can you please set up an
> >>> agenda for an upcoming meeting to discuss what's happened since and next
> >>> steps?
> >>>
> >>> If you're available, perhaps we could see if Wednesday next week at the
> >>> same time would work?
> >>>
> >>> We'd also like to share how GitHub Projects [1] can be used to track
> >>> future work in the memory protection work stream. We've talked about
> >>> Projects for a while in the TianoCore Tools & CI working group and this
> >>> looks like a great opportunity to try it out. A public project has been
> >>> created in the TianoCore org [2]. I've placed some initial high-level
> >>> pillars in the project at the moment.
> >>>
> >>> Projects can help break down larger complex items and show how the
> >>> pieces fit together in a single place. It helps visualize who is working
> >>> on what, when they roughly expect to complete it, and what pillars of
> >>> memory protection work such as compatibility, testing, etc. are defined
> >>> and how we're making progress toward them. In this meeting, we'd like to
> >>> discuss how we can most effectively use it to collaborate in upcoming
> >>> work areas.
> >>>
> >>> It is not meant to replace the mailing list for communication or change
> >>> code review process but to organize and visualize agreed upon memory
> >>> protection work items. Ideally, this will help track that the areas are
> >>> covered we expect, simplify planning to intercept the changes in
> >>> platforms, show how work items are connected, and enable new
> >>> contributors to quickly see how they can contribute.
> >>>
> >>> [1] -
> >>> https://docs.github.com/en/issues/planning-and-tracking-with-
> projects/learning-
> >>> about-projects/about-projects
> >>> [2] - https://github.com/orgs/tianocore/projects/3
> >>>
> >>> Thanks,
> >>> Michael
> >>>
> >>> On 5/17/2023 3:14 AM, Ni, Ray wrote:
> >>>> I created one event in https://edk2.groups.io/g/devel/calendar.
> >>>>
> >>>> Microsoft Teams meeting link: https://teams.microsoft.com/l/meetup-
> >>>
> join/19%3ameeting_YTk4ZDU3YjItODkxZC00MTdmLTlkZmUtYThkNGQ0ZWYyMDZ
> >>> h%40thread.v2/0?context=%7b%22Tid%22%3a%2246c98d88-e344-4ed4-
> 8496-
> >>> 4ed7712e255d%22%2c%22Oid%22%3a%2255d36a50-78be-4ced-bc27-
> >>> 3d06c576cc19%22%7d
> >>>>
> >>>> The ICS file is also attached.
> >>>>
> >>>>
> >>>>> -----Original Message-----
> >>>>> From: Oliver Smith-Denny <osde@linux.microsoft.com>
> >>>>> Sent: Wednesday, May 17, 2023 1:12 AM
> >>>>> To: Ni, Ray <ray.ni@intel.com>; devel@edk2.groups.io; Ard Biesheuvel
> >>>>> <ardb@kernel.org>; Kinney, Michael D <michael.d.kinney@intel.com>;
> >>>>> t@taylorbeebe.com
> >>>>> Cc: Leif Lindholm <quic_llindhol@quicinc.com>; Ard Biesheuvel
> >>>>> <ardb+tianocore@kernel.org>; Sami Mujawar <sami.mujawar@arm.com>;
> >>>>> Michael Kubacki <mikuback@linux.microsoft.com>; Sean Brogan
> >>>>> <sean.brogan@microsoft.com>
> >>>>> Subject: Re: [edk2-devel] [PATCH v1 1/1] ArmPkg: CpuDxe: Sync GCD
> >>> Capabilities
> >>>>> With Page Table Attributes
> >>>>>
> >>>>> Hi Ray,
> >>>>>
> >>>>> That works from our side, thanks for setting up the meeting!
> >>>>>
> >>>>> Oliver
> >>>>>
> >>>>> On 5/15/2023 7:53 PM, Ni, Ray wrote:
> >>>>>> All,
> >>>>>> Can you check if the meeting time is ok for you?
> >>>>>>
> >>>>>> It will be in this week:
> >>>>>> * PDT Wednesday 07:00
> >>>>>> * Paris Wednesday 16:00
> >>>>>> * Shanghai Wednesday 22:00
> >>>>>>
> >>>>>> ________________________________________
> >>>>>> From: devel@edk2.groups.io <devel@edk2.groups.io> on behalf of Taylor
> >>> Beebe
> >>>>> <t@taylorbeebe.com>
> >>>>>> Sent: Thursday, May 11, 2023 0:10
> >>>>>> To: devel@edk2.groups.io; osde@linux.microsoft.com; Ard Biesheuvel;
> >>> Kinney,
> >>>>> Michael D
> >>>>>> Cc: Ni, Ray; Leif Lindholm; Ard Biesheuvel; Sami Mujawar; Michael
> >>>>>> Kubacki;
> >>>>> Sean Brogan
> >>>>>> Subject: Re: [edk2-devel] [PATCH v1 1/1] ArmPkg: CpuDxe: Sync GCD
> >>>>> Capabilities With Page Table Attributes
> >>>>>>
> >>>>>> Can we schedule the meeting for Wednesday 5/17? I will be out the
> >>>>>> following week and would like to attend.
> >>>>>>
> >>>>>> Thanks :)
> >>>>>>
> >>>>>> On 5/9/2023 7:59 AM, Oliver Smith-Denny wrote:
> >>>>>>> On 5/8/2023 11:59 PM, Ard Biesheuvel wrote:
> >>>>>>>> On Tue, 9 May 2023 at 04:04, Kinney, Michael D
> >>>>>>>> <michael.d.kinney@intel.com> wrote:
> >>>>>>>>>
> >>>>>>>>> I would prefer next week as well.
> >>>>>>>>>
> >>>>>>>>> Mike
> >>>>>>>>>
> >>>>>>>>
> >>>>>>>> Next week, i can only do Wednesday. The week after (22-26), the
> >>>>>>>> time
> >>>>>>>> slot works for me on any day of the week.
> >>>>>>>>
> >>>>>>>
> >>>>>>> Weds works from our side, the week after also works perfectly well
> >>>>>>> any day. Thanks for the flexibility and willingness to meet.
> >>>>>>>
> >>>>>>> For reference for this specific patch, this bz may help cache in
> >>>>>>> some info: https://bugzilla.tianocore.org/show_bug.cgi?id=753. The
> >>>>>>> mail links are largely dead, of course, but can be found on other
> >>>>>>> mailing list retention sites (maybe in the future we will have PRs
> >>>>>>> and discussions to reference :).
> >>>>>>>
> >>>>>>> Thanks,
> >>>>>>> Oliver
> >>>>>>>
> >>>>>>>
> >>>>>>>
> >>>>>>>
> >>>>>>>
> >>>>>>
> >>>>>>
> >>>>>>
> >>>>>>
> >>>>>>
> >>>>>>
> 
> 
> 
> 


[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #2: invite (1).ics --]
[-- Type: text/calendar; name="invite (1).ics", Size: 1045 bytes --]

BEGIN:VCALENDAR
VERSION:2.0
PRODID:-//Groups.io Inc//Groups.io Calendar//EN
METHOD:PUBLISH
REFRESH-INTERVAL;VALUE=DURATION:PT1H
X-PUBLISHED-TTL:PT1H
CALSCALE:GREGORIAN
BEGIN:VTIMEZONE
TZID:Asia/Shanghai
LAST-MODIFIED:20230407T050750Z
TZURL:https://www.tzurl.org/zoneinfo-outlook/Asia/Shanghai
X-LIC-LOCATION:Asia/Shanghai
BEGIN:STANDARD
TZNAME:CST
TZOFFSETFROM:+0800
TZOFFSETTO:+0800
DTSTART:19700101T000000
END:STANDARD
END:VTIMEZONE
BEGIN:VEVENT
X-GIOIDS:Event:1953410 
UID:z7xI.1686020349727420558.jYkC@groups.io
DTSTAMP:20230606T025938Z
ORGANIZER;CN=Ray Ni:mailto:ray.ni@intel.com
DTSTART:20230607T140000Z
DTEND:20230607T150000Z
SUMMARY:UEFI Memory Map\, GCD\, Page Table discussion - ARM/X86 (2nd sess
 ion)
LOCATION:https://teams.microsoft.com/l/meetup-join/19%3ameeting_M2RjMDI1N
 jEtMmQ3MS00ZWM0LTlkMzEtOWU1NGE2MGUwYmYx%40thread.v2/0?context=%7b%22Tid%2
 2%3a%2246c98d88-e344-4ed4-8496-4ed7712e255d%22%2c%22Oid%22%3a%2255d36a50-
 78be-4ced-bc27-3d06c576cc19%22%7d
SEQUENCE:1
END:VEVENT
END:VCALENDAR


^ permalink raw reply	[flat|nested] 26+ messages in thread

* Re: [edk2-devel][PATCH v1 1/1] ArmPkg: CpuDxe: Sync GCD Capabilities With Page Table Attributes
       [not found] <1759538694580A69.7408@groups.io>
@ 2023-06-07 16:10 ` Oliver Smith-Denny
  2023-06-07 17:31   ` Ard Biesheuvel
  0 siblings, 1 reply; 26+ messages in thread
From: Oliver Smith-Denny @ 2023-06-07 16:10 UTC (permalink / raw)
  To: devel
  Cc: Leif Lindholm, Ard Biesheuvel, Sami Mujawar, Michael Kubacki,
	Sean Brogan

Per the discussion in the memory protections design meeting
this morning, I am kicking this patch back to the top of
the inbox for review. If folks would like me to resend this
patchset since the thread got bogged down with scheduling
meetings, just let me know.

I'll also pull up the BZ link for when the equivalent
change went into the x86 CpuDxe driver in 2017:

https://bugzilla.tianocore.org/show_bug.cgi?id=753

This contains lots of information about why the change went
in on the x86 side (some dead mail links, but they can be
retrieved through some digging). AFAICT, this change wasn't
applied to ARM at the time due to an oversight, not a general
design decision.

Thanks,
Oliver

On 4/25/2023 5:09 PM, Oliver Smith-Denny wrote:
> When ArmPkg's CpuDxe driver initializes, it attempts to sync the
> 
> GCD with the page table. However, unlike when the UefiCpuPkg's
> 
> CpuDxe initializes, the Arm version does not update the GCD
> 
> capabilities with EFI_MEMORY_[RO|RP|XP] (this could also set
> 
> the capabilities to be the existing page table attributes for
> 
> this range, but the UefiCpuPkg CpuDxe sets the above attributes
> 
> as they are software constructs, possible to set for any memory
> 
> hardware).
> 
> 
> 
> As a result, when the GCD attributes are attempted to be set
> 
> against the old GCD capabilities, attributes that are set in the
> 
> page table can get lost because the new attributes are not in the
> 
> old GCD capabilities (and yet they are already set in the page
> 
> table) meaning that the attempted sync between the GCD and the
> 
> page table was a failure and drivers querying one vs the other
> 
> will see different state. This can lead to RWX memory regions
> 
> even with the no-execute policy set, because core drivers (such
> 
> as NonDiscoverablePciDeviceIo, to be fixed up in a later patchset)
> 
> allocate pages, query the GCD attributes, attempt to set a new
> 
> cache attribute and end up clearing the XP bit in the page table
> 
> because the GCD attributes do not have XP set.
> 
> 
> 
> This patch follows the UefiCpuPkg pattern and adds
> 
> EFI_MEMORY_[RO|RP|XP] to the GCD capabilities during CpuDxe
> 
> initialization. This ensures that memory regions which already have
> 
> these attributes set get them set in the GCD attributes, properly
> 
> syncing between the GCD and the page table.
> 
> 
> 
> This mitigates the issue seen, however, additional investigations
> 
> into setting the GCD attributes earlier and maintaining a better
> 
> sync between the GCD and the page table are being done.
> 
> 
> 
> Feedback on this proposal is greatly appreciated, particularly
> 
> any pitfalls or more architectural solutions to issues seen
> 
> with syncing the GCD and the page table.
> 
> 
> 
> PR: https://github.com/tianocore/edk2/pull/4311
> 
> Personal branch: https://github.com/os-d/edk2/tree/osde/sync_aarch64_gcd_capabilities_v1
> 
> 
> 
> Cc: Leif Lindholm <quic_llindhol@quicinc.com>
> 
> Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
> 
> Cc: Sami Mujawar <sami.mujawar@arm.com>
> 
> Cc: Michael Kubacki <mikuback@linux.microsoft.com>
> 
> Cc: Sean Brogan <sean.brogan@microsoft.com>
> 
> 
> 
> Signed-off-by: Oliver Smith-Denny <osde@linux.microsoft.com>
> 
> ---
> 
>   ArmPkg/Drivers/CpuDxe/CpuMmuCommon.c | 55 +++++++++++++++++---
> 
>   1 file changed, 49 insertions(+), 6 deletions(-)
> 
> 
> 
> diff --git a/ArmPkg/Drivers/CpuDxe/CpuMmuCommon.c b/ArmPkg/Drivers/CpuDxe/CpuMmuCommon.c
> 
> index 2e73719dce04..3ef0380e084f 100644
> 
> --- a/ArmPkg/Drivers/CpuDxe/CpuMmuCommon.c
> 
> +++ b/ArmPkg/Drivers/CpuDxe/CpuMmuCommon.c
> 
> @@ -90,6 +90,7 @@ SetGcdMemorySpaceAttributes (
> 
>     UINTN                 EndIndex;
> 
>     EFI_PHYSICAL_ADDRESS  RegionStart;
> 
>     UINT64                RegionLength;
> 
> +  UINT64                Capabilities;
> 
>   
> 
>     DEBUG ((
> 
>       DEBUG_GCD,
> 
> @@ -146,14 +147,56 @@ SetGcdMemorySpaceAttributes (
> 
>         RegionLength = MemorySpaceMap[Index].BaseAddress + MemorySpaceMap[Index].Length - RegionStart;
> 
>       }
> 
>   
> 
> +    // Always add RO, RP, and XP as all memory is capable of supporting these types (they are software
> 
> +    // constructs, not hardware features) and they are critical to maintaining a security boundary
> 
> +    Capabilities = MemorySpaceMap[Index].Capabilities | EFI_MEMORY_RO | EFI_MEMORY_RP | EFI_MEMORY_XP;
> 
> +
> 
>       //
> 
> -    // Set memory attributes according to MTRR attribute and the original attribute of descriptor
> 
> +    // Update GCD capabilities as these may have changed in the page table since the GCD was created
> 
> +    // this follows the same pattern as x86 GCD and Page Table syncing
> 
>       //
> 
> -    gDS->SetMemorySpaceAttributes (
> 
> -           RegionStart,
> 
> -           RegionLength,
> 
> -           (MemorySpaceMap[Index].Attributes & ~EFI_MEMORY_CACHETYPE_MASK) | (MemorySpaceMap[Index].Capabilities & Attributes)
> 
> -           );
> 
> +    Status = gDS->SetMemorySpaceCapabilities (
> 
> +                    RegionStart,
> 
> +                    RegionLength,
> 
> +                    Capabilities
> 
> +                    );
> 
> +
> 
> +    if (EFI_ERROR (Status)) {
> 
> +      DEBUG ((
> 
> +        DEBUG_ERROR,
> 
> +        "%a - failed to update GCD capabilities: 0x%llx on memory region: 0x%llx length: 0x%llx Status: %r\n",
> 
> +        __func__,
> 
> +        Capabilities,
> 
> +        RegionStart,
> 
> +        RegionLength,
> 
> +        Status
> 
> +        ));
> 
> +      ASSERT_EFI_ERROR (Status);
> 
> +      continue;
> 
> +    }
> 
> +
> 
> +    //
> 
> +    // Set memory attributes according to the page table attribute and the original attribute of descriptor
> 
> +    //
> 
> +    Status = gDS->SetMemorySpaceAttributes (
> 
> +                    RegionStart,
> 
> +                    RegionLength,
> 
> +                    (MemorySpaceMap[Index].Attributes & ~EFI_MEMORY_CACHETYPE_MASK) | (Attributes & Capabilities)
> 
> +                    );
> 
> +
> 
> +    if (EFI_ERROR (Status)) {
> 
> +      DEBUG ((
> 
> +        DEBUG_ERROR,
> 
> +        "%a - failed to update GCD attributes: 0x%llx on memory region: 0x%llx length: 0x%llx Status: %r\n",
> 
> +        __func__,
> 
> +        Attributes,
> 
> +        RegionStart,
> 
> +        RegionLength,
> 
> +        Status
> 
> +        ));
> 
> +      ASSERT_EFI_ERROR (Status);
> 
> +      continue;
> 
> +    }
> 
>     }
> 
>   
> 
>     return EFI_SUCCESS;
> 

^ permalink raw reply	[flat|nested] 26+ messages in thread

* Re: [edk2-devel][PATCH v1 1/1] ArmPkg: CpuDxe: Sync GCD Capabilities With Page Table Attributes
  2023-06-07 16:10 ` [edk2-devel][PATCH v1 1/1] ArmPkg: CpuDxe: Sync GCD Capabilities With Page Table Attributes Oliver Smith-Denny
@ 2023-06-07 17:31   ` Ard Biesheuvel
  2023-06-07 18:03     ` Oliver Smith-Denny
       [not found]     ` <176672827230FBF7.32008@groups.io>
  0 siblings, 2 replies; 26+ messages in thread
From: Ard Biesheuvel @ 2023-06-07 17:31 UTC (permalink / raw)
  To: devel, osde
  Cc: Leif Lindholm, Ard Biesheuvel, Sami Mujawar, Michael Kubacki,
	Sean Brogan

On Wed, 7 Jun 2023 at 18:10, Oliver Smith-Denny
<osde@linux.microsoft.com> wrote:
>
> Per the discussion in the memory protections design meeting
> this morning, I am kicking this patch back to the top of
> the inbox for review. If folks would like me to resend this
> patchset since the thread got bogged down with scheduling
> meetings, just let me know.
>
> I'll also pull up the BZ link for when the equivalent
> change went into the x86 CpuDxe driver in 2017:
>
> https://bugzilla.tianocore.org/show_bug.cgi?id=753
>
> This contains lots of information about why the change went
> in on the x86 side (some dead mail links, but they can be
> retrieved through some digging). AFAICT, this change wasn't
> applied to ARM at the time due to an oversight, not a general
> design decision.
>

Thanks for the background, this is useful.

So I agree that for all system memory regions, we should be setting
the RP, RO and XP capabilities. But what I don't understand is why
these are not set to begin with.

IOW, the resource descriptor HOBs that the initial regions are based
on should have these capabilities set already, and then, we wouldn't
have to do anything to at this point. If there is anything missing
from the generic plumbing to make sure this transformation happens
correctly, we should fix that first, and fix the existing ARM
platforms to set the correct resource attributes.

For example, ArmVirtQemu uses

  ResourceAttributes = (
                        EFI_RESOURCE_ATTRIBUTE_PRESENT |
                        EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
                        EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE |
                        EFI_RESOURCE_ATTRIBUTE_TESTED
                        );

for the resource descriptor HOBs, and afaict, this should include

EFI_RESOURCE_ATTRIBUTE_WRITE_PROTECTABLE
EFI_RESOURCE_ATTRIBUTE_EXECUTION_PROTECTABLE
EFI_RESOURCE_ATTRIBUTE_READ_ONLY_PROTECTABLE

to accurately describe the region's capabilities.

WIth that out of the way, I wonder if we still need this patch at all.

Thanks,
Ard.



>
> On 4/25/2023 5:09 PM, Oliver Smith-Denny wrote:
> > When ArmPkg's CpuDxe driver initializes, it attempts to sync the
> >
> > GCD with the page table. However, unlike when the UefiCpuPkg's
> >
> > CpuDxe initializes, the Arm version does not update the GCD
> >
> > capabilities with EFI_MEMORY_[RO|RP|XP] (this could also set
> >
> > the capabilities to be the existing page table attributes for
> >
> > this range, but the UefiCpuPkg CpuDxe sets the above attributes
> >
> > as they are software constructs, possible to set for any memory
> >
> > hardware).
> >
> >
> >
> > As a result, when the GCD attributes are attempted to be set
> >
> > against the old GCD capabilities, attributes that are set in the
> >
> > page table can get lost because the new attributes are not in the
> >
> > old GCD capabilities (and yet they are already set in the page
> >
> > table) meaning that the attempted sync between the GCD and the
> >
> > page table was a failure and drivers querying one vs the other
> >
> > will see different state. This can lead to RWX memory regions
> >
> > even with the no-execute policy set, because core drivers (such
> >
> > as NonDiscoverablePciDeviceIo, to be fixed up in a later patchset)
> >
> > allocate pages, query the GCD attributes, attempt to set a new
> >
> > cache attribute and end up clearing the XP bit in the page table
> >
> > because the GCD attributes do not have XP set.
> >
> >
> >
> > This patch follows the UefiCpuPkg pattern and adds
> >
> > EFI_MEMORY_[RO|RP|XP] to the GCD capabilities during CpuDxe
> >
> > initialization. This ensures that memory regions which already have
> >
> > these attributes set get them set in the GCD attributes, properly
> >
> > syncing between the GCD and the page table.
> >
> >
> >
> > This mitigates the issue seen, however, additional investigations
> >
> > into setting the GCD attributes earlier and maintaining a better
> >
> > sync between the GCD and the page table are being done.
> >
> >
> >
> > Feedback on this proposal is greatly appreciated, particularly
> >
> > any pitfalls or more architectural solutions to issues seen
> >
> > with syncing the GCD and the page table.
> >
> >
> >
> > PR: https://github.com/tianocore/edk2/pull/4311
> >
> > Personal branch: https://github.com/os-d/edk2/tree/osde/sync_aarch64_gcd_capabilities_v1
> >
> >
> >
> > Cc: Leif Lindholm <quic_llindhol@quicinc.com>
> >
> > Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
> >
> > Cc: Sami Mujawar <sami.mujawar@arm.com>
> >
> > Cc: Michael Kubacki <mikuback@linux.microsoft.com>
> >
> > Cc: Sean Brogan <sean.brogan@microsoft.com>
> >
> >
> >
> > Signed-off-by: Oliver Smith-Denny <osde@linux.microsoft.com>
> >
> > ---
> >
> >   ArmPkg/Drivers/CpuDxe/CpuMmuCommon.c | 55 +++++++++++++++++---
> >
> >   1 file changed, 49 insertions(+), 6 deletions(-)
> >
> >
> >
> > diff --git a/ArmPkg/Drivers/CpuDxe/CpuMmuCommon.c b/ArmPkg/Drivers/CpuDxe/CpuMmuCommon.c
> >
> > index 2e73719dce04..3ef0380e084f 100644
> >
> > --- a/ArmPkg/Drivers/CpuDxe/CpuMmuCommon.c
> >
> > +++ b/ArmPkg/Drivers/CpuDxe/CpuMmuCommon.c
> >
> > @@ -90,6 +90,7 @@ SetGcdMemorySpaceAttributes (
> >
> >     UINTN                 EndIndex;
> >
> >     EFI_PHYSICAL_ADDRESS  RegionStart;
> >
> >     UINT64                RegionLength;
> >
> > +  UINT64                Capabilities;
> >
> >
> >
> >     DEBUG ((
> >
> >       DEBUG_GCD,
> >
> > @@ -146,14 +147,56 @@ SetGcdMemorySpaceAttributes (
> >
> >         RegionLength = MemorySpaceMap[Index].BaseAddress + MemorySpaceMap[Index].Length - RegionStart;
> >
> >       }
> >
> >
> >
> > +    // Always add RO, RP, and XP as all memory is capable of supporting these types (they are software
> >
> > +    // constructs, not hardware features) and they are critical to maintaining a security boundary
> >
> > +    Capabilities = MemorySpaceMap[Index].Capabilities | EFI_MEMORY_RO | EFI_MEMORY_RP | EFI_MEMORY_XP;
> >
> > +
> >
> >       //
> >
> > -    // Set memory attributes according to MTRR attribute and the original attribute of descriptor
> >
> > +    // Update GCD capabilities as these may have changed in the page table since the GCD was created
> >
> > +    // this follows the same pattern as x86 GCD and Page Table syncing
> >
> >       //
> >
> > -    gDS->SetMemorySpaceAttributes (
> >
> > -           RegionStart,
> >
> > -           RegionLength,
> >
> > -           (MemorySpaceMap[Index].Attributes & ~EFI_MEMORY_CACHETYPE_MASK) | (MemorySpaceMap[Index].Capabilities & Attributes)
> >
> > -           );
> >
> > +    Status = gDS->SetMemorySpaceCapabilities (
> >
> > +                    RegionStart,
> >
> > +                    RegionLength,
> >
> > +                    Capabilities
> >
> > +                    );
> >
> > +
> >
> > +    if (EFI_ERROR (Status)) {
> >
> > +      DEBUG ((
> >
> > +        DEBUG_ERROR,
> >
> > +        "%a - failed to update GCD capabilities: 0x%llx on memory region: 0x%llx length: 0x%llx Status: %r\n",
> >
> > +        __func__,
> >
> > +        Capabilities,
> >
> > +        RegionStart,
> >
> > +        RegionLength,
> >
> > +        Status
> >
> > +        ));
> >
> > +      ASSERT_EFI_ERROR (Status);
> >
> > +      continue;
> >
> > +    }
> >
> > +
> >
> > +    //
> >
> > +    // Set memory attributes according to the page table attribute and the original attribute of descriptor
> >
> > +    //
> >
> > +    Status = gDS->SetMemorySpaceAttributes (
> >
> > +                    RegionStart,
> >
> > +                    RegionLength,
> >
> > +                    (MemorySpaceMap[Index].Attributes & ~EFI_MEMORY_CACHETYPE_MASK) | (Attributes & Capabilities)
> >
> > +                    );
> >
> > +
> >
> > +    if (EFI_ERROR (Status)) {
> >
> > +      DEBUG ((
> >
> > +        DEBUG_ERROR,
> >
> > +        "%a - failed to update GCD attributes: 0x%llx on memory region: 0x%llx length: 0x%llx Status: %r\n",
> >
> > +        __func__,
> >
> > +        Attributes,
> >
> > +        RegionStart,
> >
> > +        RegionLength,
> >
> > +        Status
> >
> > +        ));
> >
> > +      ASSERT_EFI_ERROR (Status);
> >
> > +      continue;
> >
> > +    }
> >
> >     }
> >
> >
> >
> >     return EFI_SUCCESS;
> >

^ permalink raw reply	[flat|nested] 26+ messages in thread

* Re: [edk2-devel][PATCH v1 1/1] ArmPkg: CpuDxe: Sync GCD Capabilities With Page Table Attributes
  2023-06-07 17:31   ` Ard Biesheuvel
@ 2023-06-07 18:03     ` Oliver Smith-Denny
       [not found]     ` <176672827230FBF7.32008@groups.io>
  1 sibling, 0 replies; 26+ messages in thread
From: Oliver Smith-Denny @ 2023-06-07 18:03 UTC (permalink / raw)
  To: devel, ardb
  Cc: Leif Lindholm, Ard Biesheuvel, Sami Mujawar, Michael Kubacki,
	Sean Brogan

On 6/7/2023 10:31 AM, Ard Biesheuvel wrote:
> On Wed, 7 Jun 2023 at 18:10, Oliver Smith-Denny
> <osde@linux.microsoft.com> wrote:
>>
>> Per the discussion in the memory protections design meeting
>> this morning, I am kicking this patch back to the top of
>> the inbox for review. If folks would like me to resend this
>> patchset since the thread got bogged down with scheduling
>> meetings, just let me know.
>>
>> I'll also pull up the BZ link for when the equivalent
>> change went into the x86 CpuDxe driver in 2017:
>>
>> https://bugzilla.tianocore.org/show_bug.cgi?id=753
>>
>> This contains lots of information about why the change went
>> in on the x86 side (some dead mail links, but they can be
>> retrieved through some digging). AFAICT, this change wasn't
>> applied to ARM at the time due to an oversight, not a general
>> design decision.
>>
> 
> Thanks for the background, this is useful.
> 
> So I agree that for all system memory regions, we should be setting
> the RP, RO and XP capabilities. But what I don't understand is why
> these are not set to begin with.
> 
> IOW, the resource descriptor HOBs that the initial regions are based
> on should have these capabilities set already, and then, we wouldn't
> have to do anything to at this point. If there is anything missing
> from the generic plumbing to make sure this transformation happens
> correctly, we should fix that first, and fix the existing ARM
> platforms to set the correct resource attributes.
> 
> For example, ArmVirtQemu uses
> 
>    ResourceAttributes = (
>                          EFI_RESOURCE_ATTRIBUTE_PRESENT |
>                          EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
>                          EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE |
>                          EFI_RESOURCE_ATTRIBUTE_TESTED
>                          );
> 
> for the resource descriptor HOBs, and afaict, this should include
> 
> EFI_RESOURCE_ATTRIBUTE_WRITE_PROTECTABLE
> EFI_RESOURCE_ATTRIBUTE_EXECUTION_PROTECTABLE
> EFI_RESOURCE_ATTRIBUTE_READ_ONLY_PROTECTABLE
> 
> to accurately describe the region's capabilities.
> 
> WIth that out of the way, I wonder if we still need this patch at all.
> 
> Thanks,
> Ard.
> 

I definitely agree this should be set at GCD initialization. Looking
at the code path you present, I think this could work. My initial
concern was that the resource descriptor HOB was passing attributes
not capabilities, but I see that it actually passes both in a field
called attributes :).

On ARM, as you point out, this looks like we would intercept at
MemoryInitPeiLib when it builds the HOBs. This would be a separate
method from what x86 does, but I can take a look at aligning x86
to initializing the capabilities through the resource descriptor
HOBs.

I'll take a crack at this and see how it shapes up. Seems reasonable
to me, though. I'll need to look into adding memory ranges, we would
want new ranges to have the capabilities, too.

Thanks,
Oliver

> 
> 
>>
>> On 4/25/2023 5:09 PM, Oliver Smith-Denny wrote:
>>> When ArmPkg's CpuDxe driver initializes, it attempts to sync the
>>>
>>> GCD with the page table. However, unlike when the UefiCpuPkg's
>>>
>>> CpuDxe initializes, the Arm version does not update the GCD
>>>
>>> capabilities with EFI_MEMORY_[RO|RP|XP] (this could also set
>>>
>>> the capabilities to be the existing page table attributes for
>>>
>>> this range, but the UefiCpuPkg CpuDxe sets the above attributes
>>>
>>> as they are software constructs, possible to set for any memory
>>>
>>> hardware).
>>>
>>>
>>>
>>> As a result, when the GCD attributes are attempted to be set
>>>
>>> against the old GCD capabilities, attributes that are set in the
>>>
>>> page table can get lost because the new attributes are not in the
>>>
>>> old GCD capabilities (and yet they are already set in the page
>>>
>>> table) meaning that the attempted sync between the GCD and the
>>>
>>> page table was a failure and drivers querying one vs the other
>>>
>>> will see different state. This can lead to RWX memory regions
>>>
>>> even with the no-execute policy set, because core drivers (such
>>>
>>> as NonDiscoverablePciDeviceIo, to be fixed up in a later patchset)
>>>
>>> allocate pages, query the GCD attributes, attempt to set a new
>>>
>>> cache attribute and end up clearing the XP bit in the page table
>>>
>>> because the GCD attributes do not have XP set.
>>>
>>>
>>>
>>> This patch follows the UefiCpuPkg pattern and adds
>>>
>>> EFI_MEMORY_[RO|RP|XP] to the GCD capabilities during CpuDxe
>>>
>>> initialization. This ensures that memory regions which already have
>>>
>>> these attributes set get them set in the GCD attributes, properly
>>>
>>> syncing between the GCD and the page table.
>>>
>>>
>>>
>>> This mitigates the issue seen, however, additional investigations
>>>
>>> into setting the GCD attributes earlier and maintaining a better
>>>
>>> sync between the GCD and the page table are being done.
>>>
>>>
>>>
>>> Feedback on this proposal is greatly appreciated, particularly
>>>
>>> any pitfalls or more architectural solutions to issues seen
>>>
>>> with syncing the GCD and the page table.
>>>
>>>
>>>
>>> PR: https://github.com/tianocore/edk2/pull/4311
>>>
>>> Personal branch: https://github.com/os-d/edk2/tree/osde/sync_aarch64_gcd_capabilities_v1
>>>
>>>
>>>
>>> Cc: Leif Lindholm <quic_llindhol@quicinc.com>
>>>
>>> Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
>>>
>>> Cc: Sami Mujawar <sami.mujawar@arm.com>
>>>
>>> Cc: Michael Kubacki <mikuback@linux.microsoft.com>
>>>
>>> Cc: Sean Brogan <sean.brogan@microsoft.com>
>>>
>>>
>>>
>>> Signed-off-by: Oliver Smith-Denny <osde@linux.microsoft.com>
>>>
>>> ---
>>>
>>>    ArmPkg/Drivers/CpuDxe/CpuMmuCommon.c | 55 +++++++++++++++++---
>>>
>>>    1 file changed, 49 insertions(+), 6 deletions(-)
>>>
>>>
>>>
>>> diff --git a/ArmPkg/Drivers/CpuDxe/CpuMmuCommon.c b/ArmPkg/Drivers/CpuDxe/CpuMmuCommon.c
>>>
>>> index 2e73719dce04..3ef0380e084f 100644
>>>
>>> --- a/ArmPkg/Drivers/CpuDxe/CpuMmuCommon.c
>>>
>>> +++ b/ArmPkg/Drivers/CpuDxe/CpuMmuCommon.c
>>>
>>> @@ -90,6 +90,7 @@ SetGcdMemorySpaceAttributes (
>>>
>>>      UINTN                 EndIndex;
>>>
>>>      EFI_PHYSICAL_ADDRESS  RegionStart;
>>>
>>>      UINT64                RegionLength;
>>>
>>> +  UINT64                Capabilities;
>>>
>>>
>>>
>>>      DEBUG ((
>>>
>>>        DEBUG_GCD,
>>>
>>> @@ -146,14 +147,56 @@ SetGcdMemorySpaceAttributes (
>>>
>>>          RegionLength = MemorySpaceMap[Index].BaseAddress + MemorySpaceMap[Index].Length - RegionStart;
>>>
>>>        }
>>>
>>>
>>>
>>> +    // Always add RO, RP, and XP as all memory is capable of supporting these types (they are software
>>>
>>> +    // constructs, not hardware features) and they are critical to maintaining a security boundary
>>>
>>> +    Capabilities = MemorySpaceMap[Index].Capabilities | EFI_MEMORY_RO | EFI_MEMORY_RP | EFI_MEMORY_XP;
>>>
>>> +
>>>
>>>        //
>>>
>>> -    // Set memory attributes according to MTRR attribute and the original attribute of descriptor
>>>
>>> +    // Update GCD capabilities as these may have changed in the page table since the GCD was created
>>>
>>> +    // this follows the same pattern as x86 GCD and Page Table syncing
>>>
>>>        //
>>>
>>> -    gDS->SetMemorySpaceAttributes (
>>>
>>> -           RegionStart,
>>>
>>> -           RegionLength,
>>>
>>> -           (MemorySpaceMap[Index].Attributes & ~EFI_MEMORY_CACHETYPE_MASK) | (MemorySpaceMap[Index].Capabilities & Attributes)
>>>
>>> -           );
>>>
>>> +    Status = gDS->SetMemorySpaceCapabilities (
>>>
>>> +                    RegionStart,
>>>
>>> +                    RegionLength,
>>>
>>> +                    Capabilities
>>>
>>> +                    );
>>>
>>> +
>>>
>>> +    if (EFI_ERROR (Status)) {
>>>
>>> +      DEBUG ((
>>>
>>> +        DEBUG_ERROR,
>>>
>>> +        "%a - failed to update GCD capabilities: 0x%llx on memory region: 0x%llx length: 0x%llx Status: %r\n",
>>>
>>> +        __func__,
>>>
>>> +        Capabilities,
>>>
>>> +        RegionStart,
>>>
>>> +        RegionLength,
>>>
>>> +        Status
>>>
>>> +        ));
>>>
>>> +      ASSERT_EFI_ERROR (Status);
>>>
>>> +      continue;
>>>
>>> +    }
>>>
>>> +
>>>
>>> +    //
>>>
>>> +    // Set memory attributes according to the page table attribute and the original attribute of descriptor
>>>
>>> +    //
>>>
>>> +    Status = gDS->SetMemorySpaceAttributes (
>>>
>>> +                    RegionStart,
>>>
>>> +                    RegionLength,
>>>
>>> +                    (MemorySpaceMap[Index].Attributes & ~EFI_MEMORY_CACHETYPE_MASK) | (Attributes & Capabilities)
>>>
>>> +                    );
>>>
>>> +
>>>
>>> +    if (EFI_ERROR (Status)) {
>>>
>>> +      DEBUG ((
>>>
>>> +        DEBUG_ERROR,
>>>
>>> +        "%a - failed to update GCD attributes: 0x%llx on memory region: 0x%llx length: 0x%llx Status: %r\n",
>>>
>>> +        __func__,
>>>
>>> +        Attributes,
>>>
>>> +        RegionStart,
>>>
>>> +        RegionLength,
>>>
>>> +        Status
>>>
>>> +        ));
>>>
>>> +      ASSERT_EFI_ERROR (Status);
>>>
>>> +      continue;
>>>
>>> +    }
>>>
>>>      }
>>>
>>>
>>>
>>>      return EFI_SUCCESS;
>>>
> 
> 
> 
> 

^ permalink raw reply	[flat|nested] 26+ messages in thread

* Re: [edk2-devel][PATCH v1 1/1] ArmPkg: CpuDxe: Sync GCD Capabilities With Page Table Attributes
       [not found]     ` <176672827230FBF7.32008@groups.io>
@ 2023-07-07 20:13       ` Oliver Smith-Denny
  0 siblings, 0 replies; 26+ messages in thread
From: Oliver Smith-Denny @ 2023-07-07 20:13 UTC (permalink / raw)
  To: devel, ardb
  Cc: Leif Lindholm, Ard Biesheuvel, Sami Mujawar, Michael Kubacki,
	Sean Brogan

On 6/7/2023 11:03 AM, Oliver Smith-Denny wrote:
> On 6/7/2023 10:31 AM, Ard Biesheuvel wrote:
>> On Wed, 7 Jun 2023 at 18:10, Oliver Smith-Denny
>> <osde@linux.microsoft.com> wrote:
>>>
>>> Per the discussion in the memory protections design meeting
>>> this morning, I am kicking this patch back to the top of
>>> the inbox for review. If folks would like me to resend this
>>> patchset since the thread got bogged down with scheduling
>>> meetings, just let me know.
>>>
>>> I'll also pull up the BZ link for when the equivalent
>>> change went into the x86 CpuDxe driver in 2017:
>>>
>>> https://bugzilla.tianocore.org/show_bug.cgi?id=753
>>>
>>> This contains lots of information about why the change went
>>> in on the x86 side (some dead mail links, but they can be
>>> retrieved through some digging). AFAICT, this change wasn't
>>> applied to ARM at the time due to an oversight, not a general
>>> design decision.
>>>
>>
>> Thanks for the background, this is useful.
>>
>> So I agree that for all system memory regions, we should be setting
>> the RP, RO and XP capabilities. But what I don't understand is why
>> these are not set to begin with.
>>
>> IOW, the resource descriptor HOBs that the initial regions are based
>> on should have these capabilities set already, and then, we wouldn't
>> have to do anything to at this point. If there is anything missing
>> from the generic plumbing to make sure this transformation happens
>> correctly, we should fix that first, and fix the existing ARM
>> platforms to set the correct resource attributes.
>>
>> For example, ArmVirtQemu uses
>>
>>    ResourceAttributes = (
>>                          EFI_RESOURCE_ATTRIBUTE_PRESENT |
>>                          EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
>>                          EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE |
>>                          EFI_RESOURCE_ATTRIBUTE_TESTED
>>                          );
>>
>> for the resource descriptor HOBs, and afaict, this should include
>>
>> EFI_RESOURCE_ATTRIBUTE_WRITE_PROTECTABLE
>> EFI_RESOURCE_ATTRIBUTE_EXECUTION_PROTECTABLE
>> EFI_RESOURCE_ATTRIBUTE_READ_ONLY_PROTECTABLE
>>
>> to accurately describe the region's capabilities.
>>
>> WIth that out of the way, I wonder if we still need this patch at all.
>>
>> Thanks,
>> Ard.
>>
> 
> I definitely agree this should be set at GCD initialization. Looking
> at the code path you present, I think this could work. My initial
> concern was that the resource descriptor HOB was passing attributes
> not capabilities, but I see that it actually passes both in a field
> called attributes :).
> 
> On ARM, as you point out, this looks like we would intercept at
> MemoryInitPeiLib when it builds the HOBs. This would be a separate
> method from what x86 does, but I can take a look at aligning x86
> to initializing the capabilities through the resource descriptor
> HOBs.
> 
> I'll take a crack at this and see how it shapes up. Seems reasonable
> to me, though. I'll need to look into adding memory ranges, we would
> want new ranges to have the capabilities, too.
> 

Hi Ard,

I'm returning to this after a couple of weeks of vacation, hopefully
with fresh eyes :). The path you describe of resource descriptor HOBs
including the RO/RP/XP capabilities does looks like it would work and
I do like that it moves these capabilities earlier.

That being said, the downside of this approach to me is that it has
the core code rely on the platform doing the right thing, which is
far from guaranteed. I would prefer to have the core code control
the memory protections as much as possible with platform
configurability. Platforms have already had the opportunity to
set these capabilities in resource descriptor HOBs, but are not.

This leads into another related concept, what is the default state
of free memory (is it XP, RO, RP, none of them, some combination,
etc.). This is also something that should be enforced at the core
level, I believe. I will explore this further in a different patch
set.

For this patchset, I think the right approach would be to set the
RP/RO/XP capabilities by default when constructing the GCD. This
would also allow the Intel side to not have the workaround they have,
where they apply these capabilities when syncing the page table and
the GCD after CpuDxe comes up (as I did in this patchset for ARM64).
I can spin off a new version with that once I do so some testing.

Thanks,
Oliver

> 
>>
>>
>>>
>>> On 4/25/2023 5:09 PM, Oliver Smith-Denny wrote:
>>>> When ArmPkg's CpuDxe driver initializes, it attempts to sync the
>>>>
>>>> GCD with the page table. However, unlike when the UefiCpuPkg's
>>>>
>>>> CpuDxe initializes, the Arm version does not update the GCD
>>>>
>>>> capabilities with EFI_MEMORY_[RO|RP|XP] (this could also set
>>>>
>>>> the capabilities to be the existing page table attributes for
>>>>
>>>> this range, but the UefiCpuPkg CpuDxe sets the above attributes
>>>>
>>>> as they are software constructs, possible to set for any memory
>>>>
>>>> hardware).
>>>>
>>>>
>>>>
>>>> As a result, when the GCD attributes are attempted to be set
>>>>
>>>> against the old GCD capabilities, attributes that are set in the
>>>>
>>>> page table can get lost because the new attributes are not in the
>>>>
>>>> old GCD capabilities (and yet they are already set in the page
>>>>
>>>> table) meaning that the attempted sync between the GCD and the
>>>>
>>>> page table was a failure and drivers querying one vs the other
>>>>
>>>> will see different state. This can lead to RWX memory regions
>>>>
>>>> even with the no-execute policy set, because core drivers (such
>>>>
>>>> as NonDiscoverablePciDeviceIo, to be fixed up in a later patchset)
>>>>
>>>> allocate pages, query the GCD attributes, attempt to set a new
>>>>
>>>> cache attribute and end up clearing the XP bit in the page table
>>>>
>>>> because the GCD attributes do not have XP set.
>>>>
>>>>
>>>>
>>>> This patch follows the UefiCpuPkg pattern and adds
>>>>
>>>> EFI_MEMORY_[RO|RP|XP] to the GCD capabilities during CpuDxe
>>>>
>>>> initialization. This ensures that memory regions which already have
>>>>
>>>> these attributes set get them set in the GCD attributes, properly
>>>>
>>>> syncing between the GCD and the page table.
>>>>
>>>>
>>>>
>>>> This mitigates the issue seen, however, additional investigations
>>>>
>>>> into setting the GCD attributes earlier and maintaining a better
>>>>
>>>> sync between the GCD and the page table are being done.
>>>>
>>>>
>>>>
>>>> Feedback on this proposal is greatly appreciated, particularly
>>>>
>>>> any pitfalls or more architectural solutions to issues seen
>>>>
>>>> with syncing the GCD and the page table.
>>>>
>>>>
>>>>
>>>> PR: https://github.com/tianocore/edk2/pull/4311
>>>>
>>>> Personal branch: 
>>>> https://github.com/os-d/edk2/tree/osde/sync_aarch64_gcd_capabilities_v1
>>>>
>>>>
>>>>
>>>> Cc: Leif Lindholm <quic_llindhol@quicinc.com>
>>>>
>>>> Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
>>>>
>>>> Cc: Sami Mujawar <sami.mujawar@arm.com>
>>>>
>>>> Cc: Michael Kubacki <mikuback@linux.microsoft.com>
>>>>
>>>> Cc: Sean Brogan <sean.brogan@microsoft.com>
>>>>
>>>>
>>>>
>>>> Signed-off-by: Oliver Smith-Denny <osde@linux.microsoft.com>
>>>>
>>>> ---
>>>>
>>>>    ArmPkg/Drivers/CpuDxe/CpuMmuCommon.c | 55 +++++++++++++++++---
>>>>
>>>>    1 file changed, 49 insertions(+), 6 deletions(-)
>>>>
>>>>
>>>>
>>>> diff --git a/ArmPkg/Drivers/CpuDxe/CpuMmuCommon.c 
>>>> b/ArmPkg/Drivers/CpuDxe/CpuMmuCommon.c
>>>>
>>>> index 2e73719dce04..3ef0380e084f 100644
>>>>
>>>> --- a/ArmPkg/Drivers/CpuDxe/CpuMmuCommon.c
>>>>
>>>> +++ b/ArmPkg/Drivers/CpuDxe/CpuMmuCommon.c
>>>>
>>>> @@ -90,6 +90,7 @@ SetGcdMemorySpaceAttributes (
>>>>
>>>>      UINTN                 EndIndex;
>>>>
>>>>      EFI_PHYSICAL_ADDRESS  RegionStart;
>>>>
>>>>      UINT64                RegionLength;
>>>>
>>>> +  UINT64                Capabilities;
>>>>
>>>>
>>>>
>>>>      DEBUG ((
>>>>
>>>>        DEBUG_GCD,
>>>>
>>>> @@ -146,14 +147,56 @@ SetGcdMemorySpaceAttributes (
>>>>
>>>>          RegionLength = MemorySpaceMap[Index].BaseAddress + 
>>>> MemorySpaceMap[Index].Length - RegionStart;
>>>>
>>>>        }
>>>>
>>>>
>>>>
>>>> +    // Always add RO, RP, and XP as all memory is capable of 
>>>> supporting these types (they are software
>>>>
>>>> +    // constructs, not hardware features) and they are critical to 
>>>> maintaining a security boundary
>>>>
>>>> +    Capabilities = MemorySpaceMap[Index].Capabilities | 
>>>> EFI_MEMORY_RO | EFI_MEMORY_RP | EFI_MEMORY_XP;
>>>>
>>>> +
>>>>
>>>>        //
>>>>
>>>> -    // Set memory attributes according to MTRR attribute and the 
>>>> original attribute of descriptor
>>>>
>>>> +    // Update GCD capabilities as these may have changed in the 
>>>> page table since the GCD was created
>>>>
>>>> +    // this follows the same pattern as x86 GCD and Page Table syncing
>>>>
>>>>        //
>>>>
>>>> -    gDS->SetMemorySpaceAttributes (
>>>>
>>>> -           RegionStart,
>>>>
>>>> -           RegionLength,
>>>>
>>>> -           (MemorySpaceMap[Index].Attributes & 
>>>> ~EFI_MEMORY_CACHETYPE_MASK) | (MemorySpaceMap[Index].Capabilities & 
>>>> Attributes)
>>>>
>>>> -           );
>>>>
>>>> +    Status = gDS->SetMemorySpaceCapabilities (
>>>>
>>>> +                    RegionStart,
>>>>
>>>> +                    RegionLength,
>>>>
>>>> +                    Capabilities
>>>>
>>>> +                    );
>>>>
>>>> +
>>>>
>>>> +    if (EFI_ERROR (Status)) {
>>>>
>>>> +      DEBUG ((
>>>>
>>>> +        DEBUG_ERROR,
>>>>
>>>> +        "%a - failed to update GCD capabilities: 0x%llx on memory 
>>>> region: 0x%llx length: 0x%llx Status: %r\n",
>>>>
>>>> +        __func__,
>>>>
>>>> +        Capabilities,
>>>>
>>>> +        RegionStart,
>>>>
>>>> +        RegionLength,
>>>>
>>>> +        Status
>>>>
>>>> +        ));
>>>>
>>>> +      ASSERT_EFI_ERROR (Status);
>>>>
>>>> +      continue;
>>>>
>>>> +    }
>>>>
>>>> +
>>>>
>>>> +    //
>>>>
>>>> +    // Set memory attributes according to the page table attribute 
>>>> and the original attribute of descriptor
>>>>
>>>> +    //
>>>>
>>>> +    Status = gDS->SetMemorySpaceAttributes (
>>>>
>>>> +                    RegionStart,
>>>>
>>>> +                    RegionLength,
>>>>
>>>> +                    (MemorySpaceMap[Index].Attributes & 
>>>> ~EFI_MEMORY_CACHETYPE_MASK) | (Attributes & Capabilities)
>>>>
>>>> +                    );
>>>>
>>>> +
>>>>
>>>> +    if (EFI_ERROR (Status)) {
>>>>
>>>> +      DEBUG ((
>>>>
>>>> +        DEBUG_ERROR,
>>>>
>>>> +        "%a - failed to update GCD attributes: 0x%llx on memory 
>>>> region: 0x%llx length: 0x%llx Status: %r\n",
>>>>
>>>> +        __func__,
>>>>
>>>> +        Attributes,
>>>>
>>>> +        RegionStart,
>>>>
>>>> +        RegionLength,
>>>>
>>>> +        Status
>>>>
>>>> +        ));
>>>>
>>>> +      ASSERT_EFI_ERROR (Status);
>>>>
>>>> +      continue;
>>>>
>>>> +    }
>>>>
>>>>      }
>>>>
>>>>
>>>>
>>>>      return EFI_SUCCESS;
>>>>
>>
>>
>>
>>
> 
> 
> 
> 

^ permalink raw reply	[flat|nested] 26+ messages in thread

end of thread, other threads:[~2023-07-07 20:13 UTC | newest]

Thread overview: 26+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
     [not found] <1759538694580A69.7408@groups.io>
2023-06-07 16:10 ` [edk2-devel][PATCH v1 1/1] ArmPkg: CpuDxe: Sync GCD Capabilities With Page Table Attributes Oliver Smith-Denny
2023-06-07 17:31   ` Ard Biesheuvel
2023-06-07 18:03     ` Oliver Smith-Denny
     [not found]     ` <176672827230FBF7.32008@groups.io>
2023-07-07 20:13       ` Oliver Smith-Denny
2023-04-26  0:09 Oliver Smith-Denny
2023-05-01 13:02 ` Ard Biesheuvel
2023-05-01 17:03   ` Oliver Smith-Denny
2023-05-01 17:49     ` [edk2-devel] [PATCH " Michael D Kinney
2023-05-01 17:50       ` Ard Biesheuvel
2023-05-01 17:53         ` Oliver Smith-Denny
2023-05-01 17:59           ` Michael D Kinney
2023-05-09  1:35             ` Ni, Ray
2023-05-09  2:03               ` Oliver Smith-Denny
2023-05-09  2:04                 ` Michael D Kinney
2023-05-09  6:59                   ` Ard Biesheuvel
2023-05-09 14:59                     ` Oliver Smith-Denny
2023-05-10 16:10                       ` Taylor Beebe
2023-05-16  2:53                         ` Ni, Ray
2023-05-16 17:11                           ` Oliver Smith-Denny
2023-05-17  7:14                             ` Ni, Ray
2023-06-02  2:24                               ` Michael Kubacki
2023-06-02  2:42                                 ` Ni, Ray
2023-06-02  3:09                                   ` Michael Kubacki
2023-06-02  9:31                                     ` Ard Biesheuvel
2023-06-06  2:13                                     ` Michael Kubacki
2023-06-06  3:00                                       ` Ni, Ray

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