From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by spool.mail.gandi.net (Postfix) with ESMTPS id 635A8740048 for ; Wed, 20 Dec 2023 09:54:42 +0000 (UTC) DKIM-Signature: a=rsa-sha256; bh=gUEQbXi5onSUZ7JmfOYG+tCZF0YAmEtKd2clLILW1Og=; c=relaxed/simple; d=groups.io; h=MIME-Version:References:In-Reply-To:From:Date:Message-ID:Subject:To:Cc:Precedence:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Reply-To:List-Unsubscribe-Post:List-Unsubscribe:Content-Type; s=20140610; t=1703066081; v=1; b=Xll902NMxXbydjy7aWntgUXyocXG4lfB+yTxfdFTEHotNF2COXl5qPnd083pFR1nWG1G1xtH ju3/HabJU//0ipiYxvgOcC0z9ZO83Iyt70qJxcymAZGmIae1gkQSj+bgE4DsRK9+01lEZ6F06DT WqcbREzBqyNW+/YKE6O+ytKQ= X-Received: by 127.0.0.2 with SMTP id PVJ7YY7687511x3P4hy3VDZU; Wed, 20 Dec 2023 01:54:41 -0800 X-Received: from sin.source.kernel.org (sin.source.kernel.org [145.40.73.55]) by mx.groups.io with SMTP id smtpd.web11.18384.1703066079928966841 for ; Wed, 20 Dec 2023 01:54:40 -0800 X-Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by sin.source.kernel.org (Postfix) with ESMTP id 58A14CE1C17 for ; Wed, 20 Dec 2023 09:54:36 +0000 (UTC) X-Received: by smtp.kernel.org (Postfix) with ESMTPSA id 52BD5C433C9 for ; Wed, 20 Dec 2023 09:54:35 +0000 (UTC) X-Received: by mail-lj1-f172.google.com with SMTP id 38308e7fff4ca-2cc690a3712so45512951fa.3 for ; Wed, 20 Dec 2023 01:54:35 -0800 (PST) X-Gm-Message-State: Y9eI0TANwb8qgSvGZXpScS3Dx7686176AA= X-Google-Smtp-Source: AGHT+IGUUU7SgOC8COAKVb3TX+sEp0v9NtfXTvNy6ifeT9ilsQ6cPhlhAypS9yvC1YUFRfVKc4Xiy0QU/aggqLX9TH8= X-Received: by 2002:a2e:90c9:0:b0:2cc:9389:c9e with SMTP id o9-20020a2e90c9000000b002cc93890c9emr218532ljg.41.1703066073461; Wed, 20 Dec 2023 01:54:33 -0800 (PST) MIME-Version: 1.0 References: <20231212130932.2467028-1-lichao@loongson.cn> <17A017C201FEB90D.32321@groups.io> <9014a7b3-095c-42b1-a9ef-5a388818385d@loongson.cn> In-Reply-To: From: "Ard Biesheuvel" Date: Wed, 20 Dec 2023 10:54:22 +0100 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [edk2-devel] [PATCH v4 19/37] UefiCpuPkg: Add MMIO method in CpuIo2Dxe To: "Ni, Ray" Cc: "devel@edk2.groups.io" , "lichao@loongson.cn" , "Kumar, Rahul R" , Gerd Hoffmann , Leif Lindholm , Ard Biesheuvel , Sami Mujawar Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,ardb@kernel.org List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: Content-Type: text/plain; charset="UTF-8" X-GND-Status: LEGIT Authentication-Results: spool.mail.gandi.net; dkim=pass header.d=groups.io header.s=20140610 header.b=Xll902NM; dmarc=fail reason="SPF not aligned (relaxed), DKIM not aligned (relaxed)" header.from=kernel.org (policy=none); spf=pass (spool.mail.gandi.net: domain of bounce@groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce@groups.io On Wed, 20 Dec 2023 at 10:44, Ni, Ray wrote: > > Ard, > Let me try to understand: > > 1. CPU does not support IO instructions to access IO ports. > 2. PCI devices contain IO space. > 3. A special PCI host bridge can be configured to map a range of MMIO space from CPU side to another range of IO space to PCI device side. > Correct. > If above is right, I can imagine what problem Chao is trying to solve. > There are following facts: > 4. MdeModulePkg/PciHostBridge driver produces PciRootBridgeIo->Io() service which directly calls to CpuIo->Io() > > I guess Chao are using MdeModulePkg/PciHostBridge driver. > Yes. This driver is widely used on ARM and RISC-V systems. > I agree with Ard that the proper place to change/hook the IO access is inside PciHostBridge driver instead of CpuIo2Dxe if the only IO access is from PCI device driver. > That is not what I said :-) I implemented CpuIo2Dxe like this in the past for ARM, and now it appears we need to generalize this solution for other architectures as well. > Then PciHostBridgeDxe driver could be enhanced to honor the MMIO-to-IO mapping and only translate the IO request to MMIO which belongs to the IO window. > The problem is that PI/UEFI has a dedicated global coherency domain (GCD) for port I/O, so I don't think we can completely hide it in the PCI driver. But the situation is very different from x86, which has many well-known port I/O numbers that could either be backed by the chipset directly or by devices on the PCI bus. ACPI can already describe this arrangement, e.g., see below, where the DWordIO window has TypeTranslation, and the range is in the port I/O domain, but translate and length are in the memory domain. Non-x86 OSes can deal with this natively. Given that CpuIo2 already exists, and provides a suitable abstraction (i.e., C functions to perform port I/O where the CPU may not have native instructions to do so), I think retaining this protocol is fine, we just need a better way to link it into the existing PCI infrastructure. // Root complex resources Method (_CRS, 0, Serialized) { Name (RBUF, ResourceTemplate () { WordBusNumber ( // Bus numbers assigned to this root ResourceProducer, MinFixed, MaxFixed, PosDecode, 0, // AddressGranularity SYNQUACER_PCI_SEG0_BUSNUM_MIN, // Minimum Bus Number SYNQUACER_PCI_SEG0_BUSNUM_MAX, // Maximum Bus Number 0, // AddressTranslation SYNQUACER_PCI_SEG0_BUSNUM_RANGE // RangeLength - # of Busses ) QWordMemory ( // 32-bit BAR Windows ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, 0x00000000, // Granularity SYNQUACER_PCI_SEG0_MMIO32_MIN, // Min Base Address SYNQUACER_PCI_SEG0_MMIO32_MAX, // Max Base Address SYNQUACER_PCI_SEG0_MMIO32_XLATE, // Translate SYNQUACER_PCI_SEG0_MMIO32_SIZE // Length ) QWordMemory ( // 64-bit BAR Windows ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, 0x00000000, // Granularity SYNQUACER_PCI_SEG0_MMIO64_MIN, // Min Base Address SYNQUACER_PCI_SEG0_MMIO64_MAX, // Max Base Address 0x00000000, // Translate SYNQUACER_PCI_SEG0_MMIO64_SIZE // Length ) DWordIo ( // IO window ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, 0x00000000, // Granularity SYNQUACER_PCI_SEG0_PORTIO_MIN, // Min Base Address SYNQUACER_PCI_SEG0_PORTIO_MAX, // Max Base Address SYNQUACER_PCI_SEG0_PORTIO_MEMBASE, // Translate SYNQUACER_PCI_SEG0_PORTIO_MEMSIZE, // Length , , , TypeTranslation ) }) // Name (RBUF) -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. 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