From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by spool.mail.gandi.net (Postfix) with ESMTPS id 7B377941B44 for ; Wed, 22 Nov 2023 15:41:28 +0000 (UTC) DKIM-Signature: a=rsa-sha256; bh=NNYhVXqSnFNgdzAptUgCe3O5KSmWqkltO7ERIvQIsLw=; c=relaxed/simple; d=groups.io; h=MIME-Version:References:In-Reply-To:From:Date:Message-ID:Subject:To:Cc:Precedence:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Reply-To:List-Unsubscribe-Post:List-Unsubscribe:Content-Type; s=20140610; t=1700667687; v=1; b=PW1GD3yGUsjeIqXHkHpob0L7x2+xVgpCDYM793dJWNdcEsNekulT8GrAoICXqvsr+sVFOJaM iKLe+VwG6du/1Ko/Mj9CaVYJPSLsyiRcfcf+XTRCmJr01yazzVJUF4X4UfrOcdZ0T7Suj7RAVC8 BHV/wtVfOLcpqWZXHCHeFQCs= X-Received: by 127.0.0.2 with SMTP id ZuKpYY7687511xFlP3I1M0EL; Wed, 22 Nov 2023 07:41:27 -0800 X-Received: from ams.source.kernel.org (ams.source.kernel.org [145.40.68.75]) by mx.groups.io with SMTP id smtpd.web10.22794.1700667685947446186 for ; Wed, 22 Nov 2023 07:41:26 -0800 X-Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by ams.source.kernel.org (Postfix) with ESMTP id C5F00B8264D for ; Wed, 22 Nov 2023 15:41:23 +0000 (UTC) X-Received: by smtp.kernel.org (Postfix) with ESMTPSA id 2CDC4C433CB for ; Wed, 22 Nov 2023 15:41:23 +0000 (UTC) X-Received: by mail-lj1-f176.google.com with SMTP id 38308e7fff4ca-2c87adce180so49408101fa.0 for ; Wed, 22 Nov 2023 07:41:23 -0800 (PST) X-Gm-Message-State: LCjho1U3rWLAO6IoLshnd3TOx7686176AA= X-Google-Smtp-Source: AGHT+IFDEhfF7bbMwgKdNCWuNgrGYFqz4O04/99FikQPwfj7MsWHIaz1m6a1cF2aKjgYUOiv8Q2SiC1dk2B0GnEiV+4= X-Received: by 2002:a05:651c:205:b0:2c6:eea4:3cfb with SMTP id y5-20020a05651c020500b002c6eea43cfbmr1864085ljn.50.1700667681398; Wed, 22 Nov 2023 07:41:21 -0800 (PST) MIME-Version: 1.0 References: <20231103025131.1643-1-yuinyee.chew@starfivetech.com> <20231103025131.1643-2-yuinyee.chew@starfivetech.com> In-Reply-To: <20231103025131.1643-2-yuinyee.chew@starfivetech.com> From: "Ard Biesheuvel" Date: Wed, 22 Nov 2023 16:41:10 +0100 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [edk2-devel] [PATCH v3 1/5] DesignWare/DwEmmcDxe: Enabled Internal IDMAC interrupt RX/TX register To: devel@edk2.groups.io, yuinyee.chew@starfivetech.com Cc: mindachen1987 , Sunil V L , Leif Lindholm , Michael D Kinney , Ard Biesheuvel , Li Yong Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,ardb@kernel.org List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: Content-Type: text/plain; charset="UTF-8" X-GND-Status: LEGIT Authentication-Results: spool.mail.gandi.net; dkim=pass header.d=groups.io header.s=20140610 header.b=PW1GD3yG; dmarc=fail reason="SPF not aligned (relaxed), DKIM not aligned (relaxed)" header.from=kernel.org (policy=none); spf=pass (spool.mail.gandi.net: domain of bounce@groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce@groups.io On Fri, 3 Nov 2023 at 03:52, John Chew wrote: > > From: mindachen1987 > > Remove DMA enable in CTRL register > Added DMA polling handling for RX/TX > This describes what the patch does, but not why. Please elaborate on what the problem is and why the changes in the patch are a suitable solution. > Cc: Sunil V L > Cc: Leif Lindholm > Cc: Michael D Kinney > Cc: Ard Biesheuvel > Cc: Li Yong > Co-authored-by: John Chew > Signed-off-by: mindachen1987 > --- > Silicon/Synopsys/DesignWare/Drivers/DwEmmcDxe/DwEmmc.h | 6 +++ > Silicon/Synopsys/DesignWare/Drivers/DwEmmcDxe/DwEmmcDxe.c | 52 ++++++++++++++++++-- > 2 files changed, 55 insertions(+), 3 deletions(-) > > diff --git a/Silicon/Synopsys/DesignWare/Drivers/DwEmmcDxe/DwEmmc.h b/Silicon/Synopsys/DesignWare/Drivers/DwEmmcDxe/DwEmmc.h > index 09ad9b8428c4..3347418006c7 100644 > --- a/Silicon/Synopsys/DesignWare/Drivers/DwEmmcDxe/DwEmmc.h > +++ b/Silicon/Synopsys/DesignWare/Drivers/DwEmmcDxe/DwEmmc.h > @@ -129,4 +129,10 @@ > > #define DWEMMC_GET_HDATA_WIDTH(x) (((x) >> 7) & 0x7) > > +/* Internal IDMAC interrupt defines */ > +#define DWMCI_IDINTEN_RI (1 << 1) > +#define DWMCI_IDINTEN_TI (1 << 0) > + > +#define DWMCI_IDINTEN_MASK (DWMCI_IDINTEN_RI | DWMCI_IDINTEN_TI) > + > #endif // __DWEMMC_H__ > diff --git a/Silicon/Synopsys/DesignWare/Drivers/DwEmmcDxe/DwEmmcDxe.c b/Silicon/Synopsys/DesignWare/Drivers/DwEmmcDxe/DwEmmcDxe.c > index 39b1ea4346dc..7ac286c5f361 100644 > --- a/Silicon/Synopsys/DesignWare/Drivers/DwEmmcDxe/DwEmmcDxe.c > +++ b/Silicon/Synopsys/DesignWare/Drivers/DwEmmcDxe/DwEmmcDxe.c > @@ -215,6 +215,7 @@ DwEmmcNotifyState ( > do { > Data = MmioRead32 (DWEMMC_BMOD); > } while (Data & DWEMMC_IDMAC_SWRESET); > + MmioWrite32 (DWEMMC_IDINTEN, 0x3); > break; > case MmcIdleState: > break; > @@ -463,6 +464,14 @@ PrepareDmaData ( > ) > { > UINTN Cnt, Blks, Idx, LastIdx; > + UINT32 Data; /* flag, cnt */ > + > + MmioWrite32 (DWEMMC_CTRL, DWEMMC_CTRL_FIFO_RESET); > + do { > + /* Wait until reset operation finished */ > + Data = MmioRead32 (DWEMMC_CTRL); > + } while (Data & DWEMMC_CTRL_RESET_ALL); > + MmioWrite32 (DWEMMC_IDSTS, 0xffffffff); > > Cnt = (Length + DWEMMC_DMA_BUF_SIZE - 1) / DWEMMC_DMA_BUF_SIZE; > Blks = (Length + DWEMMC_BLOCK_SIZE - 1) / DWEMMC_BLOCK_SIZE; > @@ -487,9 +496,7 @@ PrepareDmaData ( > (IdmacDesc + LastIdx)->Des1 = DWEMMC_IDMAC_DES1_BS1(Length - > (LastIdx * DWEMMC_DMA_BUF_SIZE)); > /* Set the Next field of Last Descriptor */ > - (IdmacDesc + LastIdx)->Des3 = 0; > MmioWrite32 (DWEMMC_DBADDR, (UINT32)((UINTN)IdmacDesc)); > - > return EFI_SUCCESS; > } > > @@ -501,7 +508,7 @@ StartDma ( > UINT32 Data; > > Data = MmioRead32 (DWEMMC_CTRL); > - Data |= DWEMMC_CTRL_INT_EN | DWEMMC_CTRL_DMA_EN | DWEMMC_CTRL_IDMAC_EN; > + Data |= DWEMMC_CTRL_DMA_EN | DWEMMC_CTRL_IDMAC_EN; > MmioWrite32 (DWEMMC_CTRL, Data); > Data = MmioRead32 (DWEMMC_BMOD); > Data |= DWEMMC_IDMAC_ENABLE | DWEMMC_IDMAC_FB; > @@ -511,6 +518,41 @@ StartDma ( > MmioWrite32 (DWEMMC_BYTCNT, Length); > } > > +STATIC > +EFI_STATUS > +DwEmmcWaitDmaComplete ( > + IN EFI_MMC_HOST_PROTOCOL *This, > + IN UINT32 Read > + ) > +{ > + UINT32 Mask, Ctrl, Timeout = 1000000; > + EFI_STATUS Status = EFI_SUCCESS; > + > + Mask = (Read) ? DWMCI_IDINTEN_RI : DWMCI_IDINTEN_TI; > + > + do { > + Ctrl = MmioRead32 (DWEMMC_IDSTS); > + if (Ctrl & Mask) { > + break; > + } > + Timeout--; > + gBS->Stall(1); > + } while (Timeout); > + > + if (!Timeout) { > + DEBUG ((DEBUG_INFO, "%a, DMA waiting timeout...\n", __func__)); > + Status = EFI_DEVICE_ERROR; > + } > + MmioWrite32 (DWEMMC_IDSTS, DWMCI_IDINTEN_MASK); > + Ctrl = MmioRead32(DWEMMC_CTRL); > + Ctrl &= ~(DWEMMC_CTRL_DMA_EN); > + Ctrl = MmioWrite32(DWEMMC_CTRL, Ctrl); > + > + gBS->Stall(100); > + > + return Status; > +} > + > EFI_STATUS > DwEmmcReadBlockData ( > IN EFI_MMC_HOST_PROTOCOL *This, > @@ -544,6 +586,8 @@ DwEmmcReadBlockData ( > DEBUG ((DEBUG_ERROR, "Failed to read data, mDwEmmcCommand:%x, mDwEmmcArgument:%x, Status:%r\n", mDwEmmcCommand, mDwEmmcArgument, Status)); > goto out; > } > + Status = DwEmmcWaitDmaComplete(This, 1); > + > out: > // Restore Tpl > gBS->RestoreTPL (Tpl); > @@ -583,6 +627,8 @@ DwEmmcWriteBlockData ( > DEBUG ((DEBUG_ERROR, "Failed to write data, mDwEmmcCommand:%x, mDwEmmcArgument:%x, Status:%r\n", mDwEmmcCommand, mDwEmmcArgument, Status)); > goto out; > } > + Status = DwEmmcWaitDmaComplete(This, 0); > + > out: > // Restore Tpl > gBS->RestoreTPL (Tpl); > -- > 2.34.1 > > > > > > -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#111608): https://edk2.groups.io/g/devel/message/111608 Mute This Topic: https://groups.io/mt/102357268/7686176 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [rebecca@openfw.io] -=-=-=-=-=-=-=-=-=-=-=-