From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by mx.groups.io with SMTP id smtpd.web11.10053.1629639448501605660 for ; Sun, 22 Aug 2021 06:37:28 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=vBseDA4W; spf=pass (domain: kernel.org, ip: 198.145.29.99, mailfrom: ardb@kernel.org) Received: by mail.kernel.org (Postfix) with ESMTPSA id A6C8B61262 for ; Sun, 22 Aug 2021 13:37:27 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1629639447; bh=6tP1JzjvED3yl51JxZus3KPscXCOemwnqgae4o/F3Iw=; h=References:In-Reply-To:From:Date:Subject:To:Cc:From; b=vBseDA4W0xiIdzxv/Xlw88q5pzYb68LcGC4ae7b6jCuUeHHt2gFr0Cmc8YupxRbl1 uaXH62PPy2nOZ1TxsWAhxn4HWG0MD65BaRsCGQWJBHRVJOEueprzDV25lz/lXKu8ue eSaYnmZeKviFEVbtlm6EJtI4TU95pSBDGM8vVT9qlF8yjFE6JYs9E2SgSNtl5Nj7Cw 0XDCitbqNQFJvbaHQSsDpBTwy+Re36Uvbgfa2YHsralD1LfncgE7/YlHDfJRjWeEnt 2Oz0I14JguOWIOglmdE4DIO/zCVxXphbSxwgjjGHvJTVRuFVGX4as3ugpuMMlcOJen ijzEmFodxpcDQ== Received: by mail-oo1-f44.google.com with SMTP id t2-20020a4ae9a2000000b0028c7144f106so3454030ood.6 for ; Sun, 22 Aug 2021 06:37:27 -0700 (PDT) X-Gm-Message-State: AOAM5326acNr4ZPT7AjUlndpzsBnz067hZKqsoENaQ9V/Hmmce1qar/2 CeOghLLolOGyCWszfouymMxGnin7fG8vjV3/r6s= X-Google-Smtp-Source: ABdhPJyocsJkRSM5n/JC2C22AYw6dB9Uza+ICWabU+G3WSo15Yggof9m69y3WIdFYIfWqO7pL4YqEu4GmRCMyaihN1I= X-Received: by 2002:a4a:dfac:: with SMTP id k12mr22763198ook.41.1629639447055; Sun, 22 Aug 2021 06:37:27 -0700 (PDT) MIME-Version: 1.0 References: <20210820041619.87248-1-jeremy.linton@arm.com> <20210820041619.87248-6-jeremy.linton@arm.com> In-Reply-To: <20210820041619.87248-6-jeremy.linton@arm.com> From: "Ard Biesheuvel" Date: Sun, 22 Aug 2021 15:37:15 +0200 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH v3 5/7] Silicon/Broadcom/Bcm27xx: Move linkup check into the cfg accessor To: Jeremy Linton Cc: edk2-devel-groups-io , Peter Batard , Ard Biesheuvel , Andrei Warkentin , Sunny Wang , Samer El-Haj-Mahmoud Content-Type: text/plain; charset="UTF-8" On Fri, 20 Aug 2021 at 06:16, Jeremy Linton wrote: > > The existing code fails to create/finish configuring the > pcie subsystem if it fails to get a linkup. This is reasonable > on the RPi4 because it generally won't happen, and the OS > could not see the root port. Now that the OS can see the > root port, its a bit odd if it only shows up when > something is plugged into the first slot. Lets move the > link up check into the config accessor where it will be used > to restrict sending CFG TLP's out the port when nothing is > plugged in. Thus avoiding a SERROR during probe. > > Signed-off-by: Jeremy Linton How will this work when the PCIE/XHCI switch is in 'platform device' mode? > --- > .../Bcm2711PciHostBridgeLib/Bcm2711PciHostBridgeLibConstructor.c | 5 ----- > .../Broadcom/Bcm27xx/Library/Bcm2711PciSegmentLib/PciSegmentLib.c | 7 +++++++ > 2 files changed, 7 insertions(+), 5 deletions(-) > > diff --git a/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciHostBridgeLib/Bcm2711PciHostBridgeLibConstructor.c b/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciHostBridgeLib/Bcm2711PciHostBridgeLibConstructor.c > index 8587d2d36d..4d4c584726 100644 > --- a/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciHostBridgeLib/Bcm2711PciHostBridgeLibConstructor.c > +++ b/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciHostBridgeLib/Bcm2711PciHostBridgeLibConstructor.c > @@ -204,11 +204,6 @@ Bcm2711PciHostBridgeLibConstructor ( > } while (((Data & 0x30) != 0x030) && (Timeout)); > DEBUG ((DEBUG_VERBOSE, "PCIe link ready (status=%x) Timeout=%d\n", Data, Timeout)); > > - if ((Data & 0x30) != 0x30) { > - DEBUG ((DEBUG_ERROR, "PCIe link not ready (status=%x)\n", Data)); > - return EFI_DEVICE_ERROR; > - } > - > if ((Data & 0x80) != 0x80) { > DEBUG ((DEBUG_ERROR, "PCIe link not in RC mode (status=%x)\n", Data)); > return EFI_UNSUPPORTED; > diff --git a/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciSegmentLib/PciSegmentLib.c b/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciSegmentLib/PciSegmentLib.c > index 6d15e82fa2..b627e5730b 100644 > --- a/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciSegmentLib/PciSegmentLib.c > +++ b/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciSegmentLib/PciSegmentLib.c > @@ -105,6 +105,13 @@ PciSegmentLibGetConfigBase ( > return 0xFFFFFFFF; > } > > + /* Don't probe slots if the link is down */ > + Data = MmioRead32 (PCIE_REG_BASE + PCIE_MISC_PCIE_STATUS); > + if ((Data & 0x30) != 0x30) { > + DEBUG ((DEBUG_ERROR, "PCIe link not ready (status=%x)\n", Data)); > + return 0xFFFFFFFF; > + } > + > MmioWrite32 (PCIE_REG_BASE + PCIE_EXT_CFG_INDEX, Address); > mPciSegmentLastAccess = Address; > } > -- > 2.13.7 >