Re: [edk2-devel] uefi VM and IO window overlap issue

["Ard Biesheuvel" <ardb@kernel.org>]

On Tue, 20 Jun 2023 at 16:27, Gerd Hoffmann <kraxel@redhat.com> wrote:
>
> On Mon, Jun 12, 2023 at 07:27:37PM +0000, Kallol Biswas [C] wrote:
> > Hi,
> >     We have been observing an issue that IO BARs can't be claimed due to resource
> > conflict.
> >
> > [    0.457693] pci 0000:00:1d.0: can't claim BAR 4 [io  0x92a0-0x92bf]: address conflict with PCI Bus 0000:01 [io  0x9000-0x9fff]
> > [    0.457705] pci 0000:00:1d.1: can't claim BAR 4 [io  0x9280-0x929f]: address conflict with PCI Bus 0000:01 [io  0x9000-0x9fff]
> > [    0.457715] pci 0000:00:1d.2: can't claim BAR 4 [io  0x9260-0x927f]: address conflict with PCI Bus 0000:01 [io  0x9000-0x9fff]
> > [    0.457743] pci 0000:00:1f.2: can't claim BAR 4 [io  0x9240-0x925f]: address conflict with PCI Bus 0000:01 [io  0x9000-0x9fff]
> > [    0.457754] pci 0000:00:1f.3: can't claim BAR 4 [io  0x9200-0x923f]: address conflict with PCI Bus 0000:01 [io  0x9000-0x9fff]
> >
> >
> > Please see the discussion thread:
> >
> > https://www.spinics.net/lists/linux-pci/msg133740.html
> >
> > The root of the problem is that OVMF does not take into account the limit register's granularity (limit) of a bridge,
> > and programs EPs with overlapping IO ranges in a different bus.
> >
> > Should we fix the issue in the OVMF?
>
> IMHO yes.
>
> https://edk2.groups.io/g/devel/message/96645
>
> Jiewen suggested to fix it somewhere in PCI code instead.
> No response from the PCI maintainers on that comment.
>
> Jiewen, Ard?
> How move forward with that?
>

But this issue is not limited to hotplug enabled platforms, right?
AIUI, the I/O resource configuration is simply incorrect.

Looking at the report:

>    Base = 0x8000;       Length = 0x200; Alignment = 0xFFF;      Owner = PPB [00|02|00:**]
>    Base = 0x8200;       Length = 0x40;  Alignment = 0x3F;       Owner = PCI [00|1F|03:20]
>    Base = 0x8240;       Length = 0x20;  Alignment = 0x1F;       Owner = PCI [00|1F|02:20]
>    Base = 0x8260;       Length = 0x20;  Alignment = 0x1F;       Owner = PCI [00|1D|02:20]

This seems to suggest that the range 0x8200 and up is assigned to
other endpoints on bus 0x0 while it is also being decoded by the
bridge. So that looks like something that needs to be fixed in the
shared PCI resource allocation code.