From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by mx.groups.io with SMTP id smtpd.web12.4851.1628257391402924632 for ; Fri, 06 Aug 2021 06:43:11 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=Vg6zzVMU; spf=pass (domain: kernel.org, ip: 198.145.29.99, mailfrom: ardb@kernel.org) Received: by mail.kernel.org (Postfix) with ESMTPSA id 6A24C6115C for ; Fri, 6 Aug 2021 13:43:10 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1628257390; bh=Cdhdq1cXPPEMPFGsOEWuO6Q6BEzEKfjLRF9vrq9Rv9o=; h=References:In-Reply-To:From:Date:Subject:To:Cc:From; b=Vg6zzVMUi9WqbXo825ZlncI2OkrG/jN4OaMZqtCDWRaOqe2AEEe7p89lpMPilCLPo TmQG3wka/iqxRYY7iC8mi6Cgo6+N6w6R9iXe9qz0O6yTZE+47Ve8uLX29D+F/DkQTb rPLw4+u1uHO0TxHtBaZwpFVn4UloEIy2KEOuYOi807XBhidjW2VCYaXBkbaVerOEFJ a+yFAVAHTBdqRutkc/+JhyL3Jr46NimY8Snp39JAN1/2PAWytlTJ+6u0YcAFebLWU3 fLm5W0wfPZlnNy5xcQWwvic9ykXCLOaylkQQAa/NEeGHmmFU0wb/PeAO5i+6AvGrkA dyUCGWqv/xL5A== Received: by mail-oo1-f41.google.com with SMTP id w2-20020a4a9e420000b02902859adadf0fso1371396ook.1 for ; Fri, 06 Aug 2021 06:43:10 -0700 (PDT) X-Gm-Message-State: AOAM532JG3Nq6GxEAaqNdjIPkprZGNJo8+trNyDYKbkvAQjEeI79m9V2 ED9LMqDngA957YX0ol1zF0u266JdxnV9PHNnnAI= X-Google-Smtp-Source: ABdhPJznw1MelG8y9MSrqPkbM2+xyUjfC+bzSnIRDTjtjaPgFD9omvtitzMcDiDBTHYUhk6zZtNL/l4wo9Z8Kr6Bvnw= X-Received: by 2002:a4a:e750:: with SMTP id n16mr4953752oov.13.1628257389795; Fri, 06 Aug 2021 06:43:09 -0700 (PDT) MIME-Version: 1.0 References: <20210805163551.488035-1-jeremy.linton@arm.com> <20210805163551.488035-5-jeremy.linton@arm.com> In-Reply-To: <20210805163551.488035-5-jeremy.linton@arm.com> From: "Ard Biesheuvel" Date: Fri, 6 Aug 2021 15:42:59 +0200 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH 4/5] Silicon/Broadcom/Bcm27xx: Tweak PCIe for CM4 To: Jeremy Linton Cc: edk2-devel-groups-io , Peter Batard , Ard Biesheuvel , Andrei Warkentin , Sunny Wang , Samer El-Haj-Mahmoud , =?UTF-8?Q?Ren=C3=A9_Treffer?= Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Thu, 5 Aug 2021 at 18:36, Jeremy Linton wrote: > > The CM4 has an actual pcie slot, so we need to move the linkup > check to the configuration probe logic. Further the device > restriction logic needs to be relaxed to support downstream > PCIe switches. > > Suggested-by: Ren=C3=A9 Treffer > Signed-off-by: Jeremy Linton Please split this into two patches. > --- > .../Bcm2711PciHostBridgeLibConstructor.c | 5 ----- > .../Library/Bcm2711PciSegmentLib/PciSegmentLib.c | 24 +++++++++++++++-= ------ > 2 files changed, 17 insertions(+), 12 deletions(-) > > diff --git a/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciHostBridgeLib/Bcm= 2711PciHostBridgeLibConstructor.c b/Silicon/Broadcom/Bcm27xx/Library/Bcm271= 1PciHostBridgeLib/Bcm2711PciHostBridgeLibConstructor.c > index 8587d2d36d..4d4c584726 100644 > --- a/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciHostBridgeLib/Bcm2711Pci= HostBridgeLibConstructor.c > +++ b/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciHostBridgeLib/Bcm2711Pci= HostBridgeLibConstructor.c > @@ -204,11 +204,6 @@ Bcm2711PciHostBridgeLibConstructor ( > } while (((Data & 0x30) !=3D 0x030) && (Timeout)); > DEBUG ((DEBUG_VERBOSE, "PCIe link ready (status=3D%x) Timeout=3D%d\n",= Data, Timeout)); > > - if ((Data & 0x30) !=3D 0x30) { > - DEBUG ((DEBUG_ERROR, "PCIe link not ready (status=3D%x)\n", Data)); > - return EFI_DEVICE_ERROR; > - } > - > if ((Data & 0x80) !=3D 0x80) { > DEBUG ((DEBUG_ERROR, "PCIe link not in RC mode (status=3D%x)\n", Dat= a)); > return EFI_UNSUPPORTED; > diff --git a/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciSegmentLib/PciSeg= mentLib.c b/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciSegmentLib/PciSegmen= tLib.c > index 44ce3b4b99..3ccc131eab 100644 > --- a/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciSegmentLib/PciSegmentLib= .c > +++ b/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciSegmentLib/PciSegmentLib= .c > @@ -78,6 +78,8 @@ PciSegmentLibGetConfigBase ( > UINT64 Base; > UINT64 Offset; > UINT32 Dev; > + UINT32 Bus; > + UINT32 Data; > > Base =3D PCIE_REG_BASE; > Offset =3D Address & 0xFFF; /* Pick off the 4k register offset= */ > @@ -89,17 +91,25 @@ PciSegmentLibGetConfigBase ( > Base +=3D PCIE_EXT_CFG_DATA; > if (mPciSegmentLastAccess !=3D Address) { > Dev =3D EFI_PCI_ADDR_DEV (Address); > + Bus =3D EFI_PCI_ADDR_BUS (Address); > + > /* > - * Scan things out directly rather than translating the "bus" to a= device, etc.. > - * only we need to limit each bus to a single device. > + * There can only be a single device on bus 1 (downstream of root)= . > + * Subsequent busses (behind a PCIe switch) can have more. > */ > - if (Dev < 1) { > - MmioWrite32 (PCIE_REG_BASE + PCIE_EXT_CFG_INDEX, Address); > - mPciSegmentLastAccess =3D Address; > - } else { > - mPciSegmentLastAccess =3D 0; > + if (Dev > 0 && (Bus < 2)) { > return 0xFFFFFFFF; > } > + > + /* Don't probe slots if the link is down */ > + Data =3D MmioRead32 (PCIE_REG_BASE + PCIE_MISC_PCIE_STATUS); > + if ((Data & 0x30) !=3D 0x30) { > + DEBUG ((DEBUG_ERROR, "PCIe link not ready (status=3D%x)\n", Da= ta)); > + return 0xFFFFFFFF; > + } > + > + MmioWrite32 (PCIE_REG_BASE + PCIE_EXT_CFG_INDEX, Address); > + mPciSegmentLastAccess =3D Address; > } > } > return Base + Offset; > -- > 2.13.7 >