From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by spool.mail.gandi.net (Postfix) with ESMTPS id 8FF0B740057 for ; Thu, 14 Mar 2024 15:15:13 +0000 (UTC) DKIM-Signature: a=rsa-sha256; bh=0iUFUINvP+PEUa5LwmnHjW43bFlagczcqYIZAkUkxYc=; c=relaxed/simple; d=groups.io; h=MIME-Version:References:In-Reply-To:From:Date:Message-ID:Subject:To:Cc:Precedence:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Resent-Date:Reply-To:List-Unsubscribe-Post:List-Unsubscribe:Content-Type; s=20240206; t=1710429312; v=1; b=vBcF/8eTi54QqokyyBTRxr+Ea1ahBV33K5NH7LJH3dK+2IRalhn9+uWDvUMMD5Stop2hHzIr vURpPBR28GJ5TTQ3icFaY0dMacrTnXY7/myaUCmgerevYGDWei0noSEeqBiUqSrFbPEha0gRFpD yCvVodR3F8LCylq1FQfGzUR2N4/lE3XDr2qYQDTOqUlaltLgOD223yA20W9GvZEesUlR2HB28zp tQcRqDi12pRbIgOugbMjP5c2RKn4o3VT2fwFR+5EG6E23EqzshlnvjyNWVKjJqVaHrvJMJW4Trm UDBE34oKrmrXJc+CpgLNSFw2pP27Cbs2/wnDraynrfDuA== X-Received: by 127.0.0.2 with SMTP id McjxYY7687511xwe1an2Ij5R; Thu, 14 Mar 2024 08:15:12 -0700 X-Received: from sin.source.kernel.org (sin.source.kernel.org [145.40.73.55]) by mx.groups.io with SMTP id smtpd.web10.15394.1710429311203244557 for ; Thu, 14 Mar 2024 08:15:11 -0700 X-Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by sin.source.kernel.org (Postfix) with ESMTP id B97FFCE1BCC for ; Thu, 14 Mar 2024 15:15:07 +0000 (UTC) X-Received: by smtp.kernel.org (Postfix) with ESMTPSA id E5582C433A6 for ; Thu, 14 Mar 2024 15:15:06 +0000 (UTC) X-Received: by mail-lf1-f43.google.com with SMTP id 2adb3069b0e04-513d609a889so75058e87.1 for ; Thu, 14 Mar 2024 08:15:06 -0700 (PDT) X-Gm-Message-State: BLPTIjmxYMn5TZ3tAftDMdugx7686176AA= X-Google-Smtp-Source: AGHT+IFglASIZOHr31zUZOuC10ToKzdl9DY5emHEok7JIsOiK/L7qzSREAvZXT70l2I2ci1nrf0admcQxM3uXUH9lF4= X-Received: by 2002:a05:6512:3288:b0:513:a2d0:28c7 with SMTP id p8-20020a056512328800b00513a2d028c7mr904659lfe.16.1710429305078; Thu, 14 Mar 2024 08:15:05 -0700 (PDT) MIME-Version: 1.0 References: <20240306-no-dt-for-cpu-v6-0-acd8727a1b59@linaro.org> <20240306-no-dt-for-cpu-v6-1-acd8727a1b59@linaro.org> In-Reply-To: From: "Ard Biesheuvel" Date: Thu, 14 Mar 2024 16:14:54 +0100 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [edk2-devel] [PATCH edk2-platforms v6 1/7] Platform/SbsaQemu: add SbsaQemuHardwareInfoLib To: devel@edk2.groups.io, marcin.juszkiewicz@linaro.org Cc: Leif Lindholm , Ard Biesheuvel , Graeme Gregory , Xiong Yining , Chen Baozi Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Resent-Date: Thu, 14 Mar 2024 08:15:11 -0700 Reply-To: devel@edk2.groups.io,ardb@kernel.org List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: Content-Type: text/plain; charset="UTF-8" X-GND-Status: LEGIT Authentication-Results: spool.mail.gandi.net; dkim=pass header.d=groups.io header.s=20240206 header.b="vBcF/8eT"; dmarc=fail reason="SPF not aligned (relaxed), DKIM not aligned (relaxed)" header.from=kernel.org (policy=none); spf=pass (spool.mail.gandi.net: domain of bounce@groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce@groups.io On Thu, 14 Mar 2024 at 16:09, Ard Biesheuvel wrote: > > On Wed, 6 Mar 2024 at 12:42, Marcin Juszkiewicz > wrote: > > > > This library provides functions to check for hardware information. > > For now it covers CPU ones: > > > > - amount of cpu cores > > - MPIDR value for cpu core > > - NUMA node id for cpu core > > > > Values are read from TF-A using platform specific SMC calls. > > > > Signed-off-by: Marcin Juszkiewicz > > --- > > Platform/Qemu/SbsaQemu/SbsaQemu.dsc | 3 +- > > .../SbsaQemuHardwareInfoLib.inf | 32 +++++++ > > .../SbsaQemu/Include/IndustryStandard/SbsaQemuSmc.h | 15 ++- > > .../Include/Library/SbsaQemuHardwareInfoLib.h | 45 +++++++++ > > .../SbsaQemuHardwareInfoLib.c | 98 ++++++++++++++++++++ > > 5 files changed, 189 insertions(+), 4 deletions(-) > > > > diff --git a/Platform/Qemu/SbsaQemu/SbsaQemu.dsc b/Platform/Qemu/SbsaQemu/SbsaQemu.dsc > > index 378600050df9..07cb3490f4cf 100644 > > --- a/Platform/Qemu/SbsaQemu/SbsaQemu.dsc > > +++ b/Platform/Qemu/SbsaQemu/SbsaQemu.dsc > > @@ -1,6 +1,6 @@ > > # > > # Copyright (c) 2021, NUVIA Inc. All rights reserved. > > -# Copyright (c) 2019, Linaro Limited. All rights reserved. > > +# Copyright (c) 2019-2024, Linaro Ltd. All rights reserved. > > # > > # SPDX-License-Identifier: BSD-2-Clause-Patent > > # > > @@ -128,6 +128,7 @@ [LibraryClasses.common] > > > > FdtHelperLib|Silicon/Qemu/SbsaQemu/Library/FdtHelperLib/FdtHelperLib.inf > > OemMiscLib|Platform/Qemu/SbsaQemu/OemMiscLib/OemMiscLib.inf > > + SbsaQemuHardwareInfoLib|Silicon/Qemu/SbsaQemu/Library/SbsaQemuHardwareInfoLib/SbsaQemuHardwareInfoLib.inf > > > > # Debug Support > > PeCoffExtraActionLib|ArmPkg/Library/DebugPeCoffExtraActionLib/DebugPeCoffExtraActionLib.inf > > diff --git a/Silicon/Qemu/SbsaQemu/Library/SbsaQemuHardwareInfoLib/SbsaQemuHardwareInfoLib.inf b/Silicon/Qemu/SbsaQemu/Library/SbsaQemuHardwareInfoLib/SbsaQemuHardwareInfoLib.inf > > new file mode 100644 > > index 000000000000..8c2def1878e6 > > --- /dev/null > > +++ b/Silicon/Qemu/SbsaQemu/Library/SbsaQemuHardwareInfoLib/SbsaQemuHardwareInfoLib.inf > > @@ -0,0 +1,32 @@ > > +#/* @file > > +# > > +# Copyright (c) Linaro Ltd. All rights reserved. > > +# > > +# SPDX-License-Identifier: BSD-2-Clause-Patent > > +# > > +#*/ > > + > > +[Defines] > > + INF_VERSION = 0x0001001c > > + BASE_NAME = SbsaQemuHardwareInfoLib > > + FILE_GUID = 6454006f-6502-46e2-9be4-4bba8d4b29fb > > + MODULE_TYPE = BASE > > + VERSION_STRING = 1.0 > > + LIBRARY_CLASS = ArmPlatformLib > > + > > This is a new library class, so you should name it and define it in > the associated .DEC file (which does not exist yet) > > You can look at Platform/Qemu/QemuOpenBoardPkg/QemuOpenBoardPkg.dec > for inspiration (but please use 1.27 and not 0x00010005 for the > version) > Just noticed there is already a .DEC in Silicon/Qemu/SbsaQemu/ so better to put it there. > > > +[Sources] > > + SbsaQemuHardwareInfoLib.c > > + > > +[Packages] > > + ArmPkg/ArmPkg.dec > > + EmbeddedPkg/EmbeddedPkg.dec > > + MdePkg/MdePkg.dec > > + Silicon/Qemu/SbsaQemu/SbsaQemu.dec > > + > > +[LibraryClasses] > > + ArmSmcLib > > + BaseMemoryLib > > + DebugLib > > + > > + [Pcd] > > + gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdCoreCount > > diff --git a/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuSmc.h b/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuSmc.h > > index 7934875e4aba..d9faee7fa5b2 100644 > > --- a/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuSmc.h > > +++ b/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuSmc.h > > @@ -11,8 +11,17 @@ > > > > #include > > > > -#define SIP_SVC_VERSION SMC_SIP_FUNCTION_ID(1) > > -#define SIP_SVC_GET_GIC SMC_SIP_FUNCTION_ID(100) > > -#define SIP_SVC_GET_GIC_ITS SMC_SIP_FUNCTION_ID(101) > > +#define SIP_SVC_VERSION SMC_SIP_FUNCTION_ID(1) > > +#define SIP_SVC_GET_GIC SMC_SIP_FUNCTION_ID(100) > > +#define SIP_SVC_GET_GIC_ITS SMC_SIP_FUNCTION_ID(101) > > +#define SIP_SVC_GET_CPU_COUNT SMC_SIP_FUNCTION_ID(200) > > +#define SIP_SVC_GET_CPU_NODE SMC_SIP_FUNCTION_ID(201) > > + > > +/* > > + * SMCC does not define return codes for SiP functions. > > + * We use Architecture ones then. > > + */ > > + > > +#define SMC_SIP_CALL_SUCCESS SMC_ARCH_CALL_SUCCESS > > > > #endif /* SBSA_QEMU_SMC_H_ */ > > diff --git a/Silicon/Qemu/SbsaQemu/Include/Library/SbsaQemuHardwareInfoLib.h b/Silicon/Qemu/SbsaQemu/Include/Library/SbsaQemuHardwareInfoLib.h > > new file mode 100644 > > index 000000000000..ca52c6b27093 > > --- /dev/null > > +++ b/Silicon/Qemu/SbsaQemu/Include/Library/SbsaQemuHardwareInfoLib.h > > @@ -0,0 +1,45 @@ > > +/** @file > > +* > > +* Copyright (c) Linaro Ltd. All rights reserved. > > +* > > +* SPDX-License-Identifier: BSD-2-Clause-Patent > > +* > > +**/ > > + > > +#ifndef SBSA_QEMU_HARDWARE_INFO_ > > +#define SBSA_QEMU_HARDWARE_INFO_ > > + > > +/** > > + Get CPU count from information passed by Qemu. > > + > > +**/ > > +VOID > > +SbsaQemuGetCpuCount ( > > + VOID > > + ); > > + > > +/** > > + Get MPIDR for a given cpu from device tree passed by Qemu. > > + > > + @param [in] CpuId Index of cpu to retrieve MPIDR value for. > > + > > + @retval MPIDR value of CPU at index > > +**/ > > +UINT64 > > +SbsaQemuGetMpidr ( > > + IN UINTN CpuId > > + ); > > + > > +/** > > + Get NUMA node id for a given cpu from device tree passed by Qemu. > > + > > + @param [in] CpuId Index of cpu to retrieve NUMA node id for. > > + > > + @retval NUMA node id for CPU at index > > +**/ > > +UINT64 > > +SbsaQemuGetCpuNumaNode ( > > + IN UINTN CpuId > > + ); > > + > > +#endif /* SBSA_QEMU_HARDWARE_INFO_ */ > > diff --git a/Silicon/Qemu/SbsaQemu/Library/SbsaQemuHardwareInfoLib/SbsaQemuHardwareInfoLib.c b/Silicon/Qemu/SbsaQemu/Library/SbsaQemuHardwareInfoLib/SbsaQemuHardwareInfoLib.c > > new file mode 100644 > > index 000000000000..134fe73a5284 > > --- /dev/null > > +++ b/Silicon/Qemu/SbsaQemu/Library/SbsaQemuHardwareInfoLib/SbsaQemuHardwareInfoLib.c > > @@ -0,0 +1,98 @@ > > +/** @file > > +* > > +* Copyright (c) 2021, NUVIA Inc. All rights reserved. > > +* Copyright (c) Linaro Ltd. All rights reserved. > > +* > > +* SPDX-License-Identifier: BSD-2-Clause-Patent > > +* > > +**/ > > + > > +#include > > +#include > > +#include > > +#include > > +#include > > + > > +/** > > + Get CPU count from information passed by Qemu. > > + > > +**/ > > +VOID > > +SbsaQemuGetCpuCount ( > > + VOID > > + ) > > +{ > > + UINTN Arg0; > > + UINTN SmcResult; > > + RETURN_STATUS Result; > > + > > + SmcResult = ArmCallSmc0 (SIP_SVC_GET_CPU_COUNT, &Arg0, NULL, NULL); > > + if (SmcResult != SMC_SIP_CALL_SUCCESS) { > > + DEBUG ((DEBUG_INFO, "SIP_SVC_GET_CPU_COUNT call failed. We have to get cpu info from DT.\n")); > > + Arg0 = FdtHelperCountCpus (); > > I don't think the fallbacks are needed here. SbsaQemu is tightly > coupled between secure and non-secure in terms of firmware, and this > is supposed to be a reference, so having legacy cruft in here does not > make sense. > > > + } > > + > > + Result = PcdSet32S (PcdCoreCount, Arg0); > > + ASSERT_RETURN_ERROR (Result); > > + > > + DEBUG ((DEBUG_INFO, "We have %d cpus.\n", Arg0)); > > +} > > + > > +/** > > + Get MPIDR for a given cpu from device tree passed by Qemu. > > + > > + @param [in] CpuId Index of cpu to retrieve MPIDR value for. > > + > > + @retval MPIDR value of CPU at index > > +**/ > > +UINT64 > > +SbsaQemuGetMpidr ( > > + IN UINTN CpuId > > + ) > > +{ > > + UINTN SmcResult; > > + UINTN Arg0; > > + UINTN Arg1; > > + > > + Arg0 = CpuId; > > + > > + SmcResult = ArmCallSmc0 (SIP_SVC_GET_CPU_NODE, &Arg0, &Arg1, NULL); > > + if (SmcResult != SMC_SIP_CALL_SUCCESS) { > > + DEBUG ((DEBUG_INFO, "SIP_SVC_GET_CPU_NODE call failed. We have to get cpu info from DT.\n")); > > + Arg1 = FdtHelperGetMpidr (CpuId); > > + } > > + > > + DEBUG ((DEBUG_ERROR, "MPIDR for CPU:%d = %d\n", CpuId, Arg1)); > > + > > Don't use DEBUG_ERROR for something that is not an error. > > > + return Arg1; > > +} > > + > > +/** > > + Get NUMA node id for a given cpu from device tree passed by Qemu. > > + > > + @param [in] CpuId Index of cpu to retrieve NUMA node id for. > > + > > + @retval NUMA node id for CPU at index > > +**/ > > +UINT64 > > +SbsaQemuGetCpuNumaNode ( > > + IN UINTN CpuId > > + ) > > +{ > > + UINTN SmcResult; > > + UINTN Arg0; > > + UINTN Arg1; > > + > > + Arg0 = CpuId; > > + > > + SmcResult = ArmCallSmc0 (SIP_SVC_GET_CPU_NODE, &Arg0, &Arg1, NULL); > > + if (SmcResult != SMC_SIP_CALL_SUCCESS) { > > + /* No fallback to DeviceTree as we did not had that info earlier. */ > > + DEBUG ((DEBUG_ERROR, "SIP_SVC_GET_CPU_NODE call failed. Couldn't find information for CPU:%d\n", CpuId)); > > + return 0; > > + } > > + > > + DEBUG ((DEBUG_ERROR, "NUMA node for CPU:%d = %d\n", CpuId, Arg0)); > > + > > + return Arg0; > > +} > > > > -- > > 2.44.0 > > > > > > > > > > > > -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#116767): https://edk2.groups.io/g/devel/message/116767 Mute This Topic: https://groups.io/mt/104763762/7686176 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [rebecca@openfw.io] -=-=-=-=-=-=-=-=-=-=-=-