From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by mx.groups.io with SMTP id smtpd.web11.8609.1663777906074447630 for ; Wed, 21 Sep 2022 09:31:46 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=J9UI0aM+; spf=pass (domain: kernel.org, ip: 139.178.84.217, mailfrom: ardb@kernel.org) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 5051163207 for ; Wed, 21 Sep 2022 16:31:45 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id B56B9C43470 for ; Wed, 21 Sep 2022 16:31:44 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1663777904; bh=znz6VuDQQexgxaYuiCAhplQGzrHcia5MeZEwRFu5QPM=; h=References:In-Reply-To:From:Date:Subject:To:Cc:From; b=J9UI0aM+bmfsDzSSDR/80psIksUoqOcyH3DXWOwucoXclNo8YXDCu0ctUbMxt9npa q5fh+/Ir6yGouX0fQJ3sHoEMVg8oIQ2dIilCM8MrhH8z38x2MPzC9ZaIDDtRgqdzD2 Mra2Uo9jas31b27TuqVtaDWe9rbscucYjgwFLXTu0oE6XORiEJRT0ry6LNLCAWUMna Uk9IcDzgjfyezJdVRgMrLycvGYcQ1PzFlOV6926d93tARQzYre2PxawadikTmp9erd h4eXg0y5hka4ZCndr49TZGN9d+31YCAiaaJNHl4W2e6A94hN6kLjnv+898wQh16EBc E3Fd3PL7KHZVg== Received: by mail-lf1-f46.google.com with SMTP id i26so10081417lfp.11 for ; Wed, 21 Sep 2022 09:31:44 -0700 (PDT) X-Gm-Message-State: ACrzQf1vD9gKjiGRgJvcHwnPDC/sFl6VS23UWthNJbJXWecgDJPegs7m rjDO6Vd2hYOzJXzeSYzGbVNA2FI2urBYArvzBTA= X-Google-Smtp-Source: AMsMyM4U+6qVZgEz7DeK5yvSuTm8o4qfHUZ8MF8M2oMVHqpVlriMJueRQjuWZTncBkh7b0wHFEmne5uEufEcEEexVbo= X-Received: by 2002:a05:6512:ba1:b0:498:9890:1bb4 with SMTP id b33-20020a0565120ba100b0049898901bb4mr9830135lfv.122.1663777902654; Wed, 21 Sep 2022 09:31:42 -0700 (PDT) MIME-Version: 1.0 References: In-Reply-To: From: "Ard Biesheuvel" Date: Wed, 21 Sep 2022 18:31:31 +0200 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [edk2-devel] [PATCH v2] MdeModulePkg/NonDiscoverablePciDeviceDxe: Allow partial FreeBuffer To: devel@edk2.groups.io, jbrasen@nvidia.com Cc: "hao.a.wu@intel.com" , "ray.ni@intel.com" , "quic_llindhol@quicinc.com" , "ardb+tianocore@kernel.org" Content-Type: text/plain; charset="UTF-8" On Wed, 21 Sept 2022 at 18:27, Jeff Brasen via groups.io wrote: > > Anything else needed to get this merged? > That is up to the MdeModulePkg maintainers. > > -----Original Message----- > > From: Ard Biesheuvel > > Sent: Thursday, September 8, 2022 9:55 AM > > To: Jeff Brasen > > Cc: devel@edk2.groups.io; hao.a.wu@intel.com; ray.ni@intel.com; > > quic_llindhol@quicinc.com; ardb+tianocore@kernel.org > > Subject: Re: [edk2-devel] [PATCH v2] > > MdeModulePkg/NonDiscoverablePciDeviceDxe: Allow partial FreeBuffer > > > > External email: Use caution opening links or attachments > > > > > > On Thu, 8 Sept 2022 at 17:39, Jeff Brasen wrote: > > > > > > > > > > > > > -----Original Message----- > > > > From: Ard Biesheuvel > > > > Sent: Monday, August 15, 2022 8:42 AM > > > > To: devel@edk2.groups.io; Jeff Brasen > > > > Cc: hao.a.wu@intel.com; ray.ni@intel.com; quic_llindhol@quicinc.com; > > > > ardb+tianocore@kernel.org > > > > Subject: Re: [edk2-devel] [PATCH v2] > > > > MdeModulePkg/NonDiscoverablePciDeviceDxe: Allow partial FreeBuffer > > > > > > > > External email: Use caution opening links or attachments > > > > > > > > > > > > On Fri, 5 Aug 2022 at 18:56, Jeff Brasen via groups.io > > > > wrote: > > > > > > > > > > > > > > > > > > > > > -----Original Message----- > > > > > > From: Ard Biesheuvel > > > > > > Sent: Tuesday, August 2, 2022 10:51 AM > > > > > > To: Jeff Brasen > > > > > > Cc: devel@edk2.groups.io; hao.a.wu@intel.com; ray.ni@intel.com; > > > > > > quic_llindhol@quicinc.com; ardb+tianocore@kernel.org > > > > > > Subject: Re: [PATCH v2] MdeModulePkg/NonDiscoverablePciDeviceDxe: > > > > > > Allow partial FreeBuffer > > > > > > > > > > > > External email: Use caution opening links or attachments > > > > > > > > > > > > > > > > > > On Tue, 2 Aug 2022 at 17:32, Jeff Brasen wrote: > > > > > > > > > > > > > > > > > > > > > > > > > > > > > -----Original Message----- > > > > > > > > From: Ard Biesheuvel > > > > > > > > Sent: Friday, July 29, 2022 9:48 AM > > > > > > > > To: Jeff Brasen > > > > > > > > Cc: devel@edk2.groups.io; hao.a.wu@intel.com; > > > > > > > > ray.ni@intel.com; quic_llindhol@quicinc.com; > > > > > > > > ardb+tianocore@kernel.org > > > > > > > > Subject: Re: [PATCH v2] > > MdeModulePkg/NonDiscoverablePciDeviceDxe: > > > > > > > > Allow partial FreeBuffer > > > > > > > > > > > > > > > > External email: Use caution opening links or attachments > > > > > > > > > > > > > > > > > > > > > > > > On Thu, 28 Jul 2022 at 13:25, Jeff Brasen > > wrote: > > > > > > > > > > > > > > > > > > > > > > > > > > > Adding Leif/Ard to CC incase they have any comments on this patch. > > > > > > > > > > > > > > > > > > > > > > > > > This generally looks ok to me. I just wonder if it wouldn't > > > > > > > > be simpler to reuse the existing allocation descriptor if it > > > > > > > > is not being freed entirely. Given the [presumably] the most > > > > > > > > common case is to allocate and then free some pages at the > > > > > > > > end, lowering the page count on the existing descriptor > > > > > > > > would cover most cases, and we'd only need to allocate new > > > > > > > > ones if pages are being freed at the start or in > > > > > > the middle. > > > > > > > > > > > > > > There is often freeing at the beginning as well as this is > > > > > > > being used to create > > > > > > a 64K aligned section of memory in the case. So it over > > > > > > allocates and the free's some at the beginning and the end. I > > > > > > could probably make it detect and use that but figured this code > > > > > > would support all cases and required less case specific detection. > > > > > > > > > > > > > > > > > > > Ah interesting. Would it help if the allocate routine aligned > > > > > > allocations to their size? > > > > > > > > > > The PciIo->AllocateBuffer function doesn't support passing the > > > > > request in so > > > > we would need to know that info beforehand. The current calling in > > > > the XHCI driver does a free at the beginning and then the end of the > > > > buffer so we could the existing allocation tracker but figured it > > > > would be better to correct the function just in case someone called it to free > > in the middle. > > > > > > > > > > > > > What I was wondering is whether such allocations are themselves > > > > multiples of 64k. This is perhaps orthogonal to the issue this patch > > > > addresses, as we'' still need to deal with partial free calls > > > > regardless. But I was curious whether XHCI in particular, and > > > > perhaps more generally, we could streamline this by aligning all allocations > > to a log2 upper bound of their sizes. > > > > > > Xhci code > > (https://github.com/tianocore/edk2/blob/master/MdeModulePkg/Bus/Pci/Xhci > > Dxe/UsbHcMem.c#L604) in allocation requested is greater the EFI_PAGE_SIZE > > allocates number of requested pages plus pages for the alignment and then > > frees pages at the beginning and end of the allocation. I am not sure we really > > could change this without adding an alignment field to the PciIo protocol. > > > > > > Is there anything else you would like to change on this patch? > > > > > > > No. Thanks for the clarification. > > > > Reviewed-by: Ard Biesheuvel > > > > >