From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from ams.source.kernel.org (ams.source.kernel.org [145.40.68.75]) by mx.groups.io with SMTP id smtpd.web11.6391.1664362183830780430 for ; Wed, 28 Sep 2022 03:49:44 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=mXU5fMRu; spf=pass (domain: kernel.org, ip: 145.40.68.75, mailfrom: ardb@kernel.org) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id 679FCB81D56 for ; Wed, 28 Sep 2022 10:49:42 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 33962C433B5 for ; Wed, 28 Sep 2022 10:49:41 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1664362181; bh=i0ly0/hk2L8PXdroPVPzRebo8EVE91mTXTQmdY+9h50=; h=References:In-Reply-To:From:Date:Subject:To:Cc:From; b=mXU5fMRuq/rTGiYnAMl3sph4i8qZDCtgIIUSPaFu74Q9xQ9+OIUwsd+GWoatVD5FV JXT0D8+Uhp4g41i6rm3jEvk9IgnX4oU14p74cIalMNbLVRe/QT81ZqLG5B73fmbaDU 9E1kSo3xikQUGbhf0tbMszn6bf01xJqDJEhsKrmTEBCpEDFQtxOtxj5ZhjCHxrjt4Y yRkkZ7Ej7raPyp+nK/RKy5d7OuJjEw5qC8SMAO10m3SdwLr9ALQEKIUweG7UWMdD5d 0fgMUK72FNgSwI70b4GtZwkjtQGB4j1uwFNFXLvweHzDsLxKUeanNCGugmIaw1llUS 769JDvCS/7n2g== Received: by mail-lj1-f175.google.com with SMTP id t16so9875176ljh.3 for ; Wed, 28 Sep 2022 03:49:41 -0700 (PDT) X-Gm-Message-State: ACrzQf2Ngnt9eNL8vvkY8xCsyIRHOoO9aIkwcx4r7SNIXnAZDyc/5uZm PTY3KCDQDFnAqdLez3Izkw57kyQ/KZ71WF4rUYQ= X-Google-Smtp-Source: AMsMyM4TMNqq2phuLssH0dDGh9bGBUBbGRW5WNyg5S9yFROgpFHAcd1UUqrL6HmlfOFoMmsuYBsy0zs+EmlPpmNtRms= X-Received: by 2002:a05:651c:b13:b0:26c:679f:ea66 with SMTP id b19-20020a05651c0b1300b0026c679fea66mr12092015ljr.516.1664362179201; Wed, 28 Sep 2022 03:49:39 -0700 (PDT) MIME-Version: 1.0 References: <20220922055530.574066-1-kraxel@redhat.com> In-Reply-To: <20220922055530.574066-1-kraxel@redhat.com> From: "Ard Biesheuvel" Date: Wed, 28 Sep 2022 12:49:27 +0200 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH v2 1/1] OvmfPkg/PlatformInitLib: q35 mtrr setup fix To: Gerd Hoffmann Cc: devel@edk2.groups.io, Jiewen Yao , Pawel Polawski , Jordan Justen , Oliver Steffen Content-Type: text/plain; charset="UTF-8" On Thu, 22 Sept 2022 at 07:55, Gerd Hoffmann wrote: > > Traditional q35 memory layout is 2.75 GB of low memory, leaving room > for the pcie mmconfig at 0xb0000000 and the 32-bit pci mmio window at > 0xc0000000. Because of that OVMF tags the memory range above > 0xb0000000 as uncachable via mtrr. > > A while ago qemu started to gigabyte-align memory by default (to make > huge pages more effective) and q35 uses only 2G of low memory in that > case. Which effectively makes the 32-bit pci mmio window start at > 0x80000000. > > This patch updates the mtrr setup code accordingly. > > Signed-off-by: Gerd Hoffmann Reviewed-by: Ard Biesheuvel Merged as #3425 > --- > OvmfPkg/Library/PlatformInitLib/MemDetect.c | 26 ++++++++++++++------- > 1 file changed, 18 insertions(+), 8 deletions(-) > > diff --git a/OvmfPkg/Library/PlatformInitLib/MemDetect.c b/OvmfPkg/Library/PlatformInitLib/MemDetect.c > index 942eaf89cfcf..d1a4f4b20791 100644 > --- a/OvmfPkg/Library/PlatformInitLib/MemDetect.c > +++ b/OvmfPkg/Library/PlatformInitLib/MemDetect.c > @@ -55,15 +55,25 @@ PlatformQemuUc32BaseInitialization ( > } > > if (PlatformInfoHob->HostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) { > - // > - // On q35, the 32-bit area that we'll mark as UC, through variable MTRRs, > - // starts at PcdPciExpressBaseAddress. The platform DSC is responsible for > - // setting PcdPciExpressBaseAddress such that describing the > - // [PcdPciExpressBaseAddress, 4GB) range require a very small number of > - // variable MTRRs (preferably 1 or 2). > - // > + LowerMemorySize = PlatformGetSystemMemorySizeBelow4gb (PlatformInfoHob); > ASSERT (PcdGet64 (PcdPciExpressBaseAddress) <= MAX_UINT32); > - PlatformInfoHob->Uc32Base = (UINT32)PcdGet64 (PcdPciExpressBaseAddress); > + ASSERT (PcdGet64 (PcdPciExpressBaseAddress) >= LowerMemorySize); > + > + if (LowerMemorySize <= BASE_2GB) { > + // Newer qemu with gigabyte aligned memory, > + // 32-bit pci mmio window is 2G -> 4G then. > + PlatformInfoHob->Uc32Base = BASE_2GB; > + } else { > + // > + // On q35, the 32-bit area that we'll mark as UC, through variable MTRRs, > + // starts at PcdPciExpressBaseAddress. The platform DSC is responsible for > + // setting PcdPciExpressBaseAddress such that describing the > + // [PcdPciExpressBaseAddress, 4GB) range require a very small number of > + // variable MTRRs (preferably 1 or 2). > + // > + PlatformInfoHob->Uc32Base = (UINT32)PcdGet64 (PcdPciExpressBaseAddress); > + } > + > return; > } > > -- > 2.37.3 >