From: "Ard Biesheuvel" <ardb@kernel.org>
To: Marcin Wojtas <mw@semihalf.com>
Cc: edk2-devel-groups-io <devel@edk2.groups.io>,
Leif Lindholm <leif@nuviainc.com>,
Ard Biesheuvel <ardb+tianocore@kernel.org>,
Grzegorz Jaszczyk <jaz@semihalf.com>,
Grzegorz Bernacki <gjb@semihalf.com>,
upstream@semihalf.com,
Samer El-Haj-Mahmoud <Samer.El-Haj-Mahmoud@arm.com>,
Jon Nettleton <jon@solid-run.com>
Subject: Re: [edk2-platforms PATCH 3/6] Marvell: Armada7k8kPciHostBridgeLib: Remove ECAM base limitation
Date: Mon, 2 Aug 2021 10:43:17 +0200 [thread overview]
Message-ID: <CAMj1kXHOEKwhWF23Hp8R4TX35tuOqWVLXzc_BkeQV_DQUxxBEA@mail.gmail.com> (raw)
In-Reply-To: <20210802050051.2831716-4-mw@semihalf.com>
On Mon, 2 Aug 2021 at 07:01, Marcin Wojtas <mw@semihalf.com> wrote:
>
> On CN913x-based platforms it is possible to have up to 9 PCIE
> root complexes. In such case it may be necessary to configure
> more configuration spaces with smaller bus count, so that
> to fit the memory layout constraints. For that purpose remove
> forcing ECAM base to be divisible by SIZE_256MB.
>
There is one subtlety here that we need to take into account: IIUC,
PCIe requires that the ECAM start address of bus N equals N MB modulo
256 MB. In other words, if your ECAM range lives at 1 GB + 128 MB, the
bus range has to start at bus 128.
I think OSes are usually quite lax about this, but it is something to
double check regardless, even for existing platforms
> Signed-off-by: Marcin Wojtas <mw@semihalf.com>
> ---
> Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciHostBridgeLib/PciHostBridgeLibConstructor.c | 1 -
> 1 file changed, 1 deletion(-)
>
> diff --git a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciHostBridgeLib/PciHostBridgeLibConstructor.c b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciHostBridgeLib/PciHostBridgeLibConstructor.c
> index 067e57a2dc..87e57aeae3 100644
> --- a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciHostBridgeLib/PciHostBridgeLibConstructor.c
> +++ b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciHostBridgeLib/PciHostBridgeLibConstructor.c
> @@ -219,7 +219,6 @@ Armada7k8kPciHostBridgeLibConstructor (
> PcieController = &(BoardPcieDescription->PcieControllers[Index]);
>
> ASSERT (PcieController->PcieBusMin == 0);
> - ASSERT (PcieController->ConfigSpaceAddress % SIZE_256MB == 0);
>
> if (PcieController->HaveResetGpio == TRUE) {
> /* Reset PCIE slot */
> --
> 2.29.0
>
next prev parent reply other threads:[~2021-08-02 8:43 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-08-02 5:00 [edk2-platforms PATCH 0/6] Marvell multiple PCIE support Marcin Wojtas
2021-08-02 5:00 ` [edk2-platforms PATCH 1/6] Marvell: Armada7k8k/OcteonTx: Allow memory mapping for more config spaces Marcin Wojtas
2021-08-02 5:00 ` [edk2-platforms PATCH 2/6] Marvell: Armada7k8k/OcteonTx: Allow tuning PCIE config space size Marcin Wojtas
2021-08-02 5:00 ` [edk2-platforms PATCH 3/6] Marvell: Armada7k8kPciHostBridgeLib: Remove ECAM base limitation Marcin Wojtas
2021-08-02 8:43 ` Ard Biesheuvel [this message]
2021-08-02 17:00 ` Marcin Wojtas
2021-08-03 6:53 ` Ard Biesheuvel
2021-08-03 7:29 ` Marcin Wojtas
2021-08-02 5:00 ` [edk2-platforms PATCH 4/6] Marvell: Armada7k8k/OcteonTx: Add multiple PCIE ports support Marcin Wojtas
2021-08-02 5:00 ` [edk2-platforms PATCH 5/6] Marvell: Armada7k8k/OcteonTX: Enable additional board configuration Marcin Wojtas
2021-08-02 5:00 ` [edk2-platforms PATCH 6/6] Marvell: IcuLib: Rework default interrupt map Marcin Wojtas
2021-08-03 7:13 ` [edk2-platforms PATCH 0/6] Marvell multiple PCIE support Ard Biesheuvel
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