From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by mx.groups.io with SMTP id smtpd.web10.17395.1627893808615286395 for ; Mon, 02 Aug 2021 01:43:28 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=WEpbKjxp; spf=pass (domain: kernel.org, ip: 198.145.29.99, mailfrom: ardb@kernel.org) Received: by mail.kernel.org (Postfix) with ESMTPSA id BF672610CC for ; Mon, 2 Aug 2021 08:43:27 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1627893807; bh=kYTV7hRJIP9lOleaO53HuSEA6Tss+XjFXVlJMx06rtY=; h=References:In-Reply-To:From:Date:Subject:To:Cc:From; b=WEpbKjxpUyAqgiIemStbH+Y2TusV1PHJnXLq9ishKtQo1QeSxxshjSBiSDrxZtnL7 oHM09+MvpMCDDgGr0qrpIMuQ5Ii02ZcKQXI5wEl2v6DjzpfCMfYj2oQ1CpzUXoP7Ca gk53SB8akuysKQtKcCD6DlW7040zfRldtTkAoNAyngwF7VfPi8DIJ4qWnqtDhml5Op pqA2NkJZyqT4cMfr4hYv+3FNKV99o5OKpoelaj6FcpWRD43nv7aPsMnJEup6fvoMpX TZiNyBc8TdSJWJSxwrBw4XP5ytm1JZ4AiS4hQnra3Yukkk7hdqU5HJvwdRiLLfjm7M DhAKTgdq+meSg== Received: by mail-oi1-f177.google.com with SMTP id w6so23309966oiv.11 for ; Mon, 02 Aug 2021 01:43:27 -0700 (PDT) X-Gm-Message-State: AOAM533x2RVkKsvsR/Lq7HkS5MHqJFnjmsnXpTdhsHMzIgrL9D3mOEV2 JCqzXEf6TwdymW0ujVznm+p0j35e8Lc4zP238sU= X-Google-Smtp-Source: ABdhPJxhZZjlPTD+K9LO8RU8NWD/DvUzj88wJSGUUXnSCxHUi0etb/1pAN0WOcquJR5ESIJkNqYPnZyTHCovR2Pd6GU= X-Received: by 2002:aca:d64d:: with SMTP id n74mr10015185oig.47.1627893807127; Mon, 02 Aug 2021 01:43:27 -0700 (PDT) MIME-Version: 1.0 References: <20210802050051.2831716-1-mw@semihalf.com> <20210802050051.2831716-4-mw@semihalf.com> In-Reply-To: <20210802050051.2831716-4-mw@semihalf.com> From: "Ard Biesheuvel" Date: Mon, 2 Aug 2021 10:43:17 +0200 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [edk2-platforms PATCH 3/6] Marvell: Armada7k8kPciHostBridgeLib: Remove ECAM base limitation To: Marcin Wojtas Cc: edk2-devel-groups-io , Leif Lindholm , Ard Biesheuvel , Grzegorz Jaszczyk , Grzegorz Bernacki , upstream@semihalf.com, Samer El-Haj-Mahmoud , Jon Nettleton Content-Type: text/plain; charset="UTF-8" On Mon, 2 Aug 2021 at 07:01, Marcin Wojtas wrote: > > On CN913x-based platforms it is possible to have up to 9 PCIE > root complexes. In such case it may be necessary to configure > more configuration spaces with smaller bus count, so that > to fit the memory layout constraints. For that purpose remove > forcing ECAM base to be divisible by SIZE_256MB. > There is one subtlety here that we need to take into account: IIUC, PCIe requires that the ECAM start address of bus N equals N MB modulo 256 MB. In other words, if your ECAM range lives at 1 GB + 128 MB, the bus range has to start at bus 128. I think OSes are usually quite lax about this, but it is something to double check regardless, even for existing platforms > Signed-off-by: Marcin Wojtas > --- > Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciHostBridgeLib/PciHostBridgeLibConstructor.c | 1 - > 1 file changed, 1 deletion(-) > > diff --git a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciHostBridgeLib/PciHostBridgeLibConstructor.c b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciHostBridgeLib/PciHostBridgeLibConstructor.c > index 067e57a2dc..87e57aeae3 100644 > --- a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciHostBridgeLib/PciHostBridgeLibConstructor.c > +++ b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciHostBridgeLib/PciHostBridgeLibConstructor.c > @@ -219,7 +219,6 @@ Armada7k8kPciHostBridgeLibConstructor ( > PcieController = &(BoardPcieDescription->PcieControllers[Index]); > > ASSERT (PcieController->PcieBusMin == 0); > - ASSERT (PcieController->ConfigSpaceAddress % SIZE_256MB == 0); > > if (PcieController->HaveResetGpio == TRUE) { > /* Reset PCIE slot */ > -- > 2.29.0 >