From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by mx.groups.io with SMTP id smtpd.web11.5073.1650440122504335256 for ; Wed, 20 Apr 2022 00:35:22 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=JlRQrWP4; spf=pass (domain: kernel.org, ip: 139.178.84.217, mailfrom: ardb@kernel.org) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 86AE66186D for ; Wed, 20 Apr 2022 07:35:21 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id C312DC385A8 for ; Wed, 20 Apr 2022 07:35:20 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1650440120; bh=/pDH+I4VRWN1vwc2FpucZdArzDxgzcfcy1pFFRHVNe4=; h=References:In-Reply-To:From:Date:Subject:To:Cc:From; b=JlRQrWP4EZhh0Hj/HGXIgn9G2jSDMIluP+VCiHi8E8JNmAKJxH/ucFGnlRm0Qp4Q0 om9QujY0YPyKERMStqxidLsQNyZqS/OxL4B16OBNylJfXgDyBQCeYNti3SYouft1/o E7XjHQXhbdqMBDUrjFdtUYoKBp269p6J1IhEenUxdAwhXd+XsHnTX9T0LlTnFEgDgs BRt51i7an8CJkCYOFA7Ux9wM14YbdoqH/wCxWAwfgGoNkhpAqm6YzvOt5IP6UWdsul 1UZenlk9N9Qzw1L8BvirY51QmbLhWIAT4Ul3BvtkhdpR2rPUBOgDuBamWNHudpByVI WL08Mich39HSQ== Received: by mail-oi1-f175.google.com with SMTP id s16so1200141oie.0 for ; Wed, 20 Apr 2022 00:35:20 -0700 (PDT) X-Gm-Message-State: AOAM532MaR156sr3vbjwmLUuQxkSe/bc4AmV2OYkmC2765F+jntqlo/G 8/LrN16kurNDqif0ald3TPge4GAXMGXVfV/YBNM= X-Google-Smtp-Source: ABdhPJzgpHx5XuHLAzt8d9uKpcUorBoja391kjyUmiEpfAght7BcjcRUsNYVvXSRfFAlDK3I+rz9jiFuf/30AXh5rDM= X-Received: by 2002:a05:6808:e8d:b0:322:bac0:2943 with SMTP id k13-20020a0568080e8d00b00322bac02943mr1108430oil.126.1650440119719; Wed, 20 Apr 2022 00:35:19 -0700 (PDT) MIME-Version: 1.0 References: <20220418081403.2324-1-pranav.madhu@arm.com> In-Reply-To: <20220418081403.2324-1-pranav.madhu@arm.com> From: "Ard Biesheuvel" Date: Wed, 20 Apr 2022 09:35:08 +0200 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [edk2-platforms][PATCH V1 1/1] Platform/Sgi: Remove SLC entry from PPTT table To: Pranav Madhu Cc: edk2-devel-groups-io , Ard Biesheuvel , Sami Mujawar Content-Type: text/plain; charset="UTF-8" On Mon, 18 Apr 2022 at 10:14, Pranav Madhu wrote: > > Remove system level cache (SLC) entry from ACPI PPTT table. SLC on the > Neoverse reference design platforms is the memory side cache and so it > is removed from PPTT table. > Could you elaborate? Why does the former justify/imply the latter? > Signed-off-by: Pranav Madhu > --- > Platform/ARM/SgiPkg/Include/SgiAcpiHeader.h | 4 +--- > Platform/ARM/SgiPkg/AcpiTables/RdE1Edge/Pptt.aslc | 24 +++----------------- > Platform/ARM/SgiPkg/AcpiTables/RdN1Edge/Pptt.aslc | 20 +++------------- > Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Pptt.aslc | 23 +++---------------- > Platform/ARM/SgiPkg/AcpiTables/RdN2/Pptt.aslc | 21 ++++------------- > Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1/Pptt.aslc | 21 ++++------------- > Platform/ARM/SgiPkg/AcpiTables/RdV1/Pptt.aslc | 21 ++++------------- > Platform/ARM/SgiPkg/AcpiTables/RdV1Mc/Pptt.aslc | 23 ++++--------------- > 8 files changed, 26 insertions(+), 131 deletions(-) > > Link to github branch for this patch - > https://github.com/Pranav-Madhu/edk2-platforms/tree/topics/remove_slc_from_pptt > > diff --git a/Platform/ARM/SgiPkg/Include/SgiAcpiHeader.h b/Platform/ARM/SgiPkg/Include/SgiAcpiHeader.h > index d75d54055436..e9b6923cb035 100644 > --- a/Platform/ARM/SgiPkg/Include/SgiAcpiHeader.h > +++ b/Platform/ARM/SgiPkg/Include/SgiAcpiHeader.h > @@ -68,10 +68,8 @@ typedef struct { > // PPTT processor package structure > typedef struct { > EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Package; > - UINT32 ResourceOffset; > - EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE Slc; > RD_PPTT_MINIMAL_CLUSTER Cluster[CLUSTER_COUNT]; > -} RD_PPTT_SLC_PACKAGE; > +} RD_PPTT_PACKAGE; > #pragma pack () > > // > diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdE1Edge/Pptt.aslc b/Platform/ARM/SgiPkg/AcpiTables/RdE1Edge/Pptt.aslc > index 3615a11d75b0..0ef9607c0732 100644 > --- a/Platform/ARM/SgiPkg/AcpiTables/RdE1Edge/Pptt.aslc > +++ b/Platform/ARM/SgiPkg/AcpiTables/RdE1Edge/Pptt.aslc > @@ -8,7 +8,7 @@ > * Each cluster includes a 2MB L3 cache. The platform also includes a system > * level cache of 8MB. > * > -* Copyright (c) 2021, ARM Limited. All rights reserved. > +* Copyright (c) 2021 - 2022, Arm Limited. All rights reserved. > * > * SPDX-License-Identifier: BSD-2-Clause-Patent > * > @@ -168,28 +168,12 @@ > #define PPTT_PACKAGE_INIT(PackageId) \ > { \ > EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( \ > - OFFSET_OF (RDE1EDGE_PPTT_PACKAGE, Slc), \ > + OFFSET_OF (RDE1EDGE_PPTT_PACKAGE, Cluster[0]), \ > PPTT_PROCESSOR_PACKAGE_FLAGS, \ > 0, \ > 0, \ > - 1 \ > + 0 \ > ), \ > - \ > - /* Offsets of the private resources */ \ > - OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \ > - Package.Slc), \ > - \ > - /* SLC parameters */ \ > - EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( \ > - PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ \ > - 0, /* Next level of cache */ \ > - SIZE_8MB, /* Size */ \ > - 8192, /* Num of sets */ \ > - 16, /* Associativity */ \ > - PPTT_UNIFIED_CACHE_ATTR, /* Attributes */ \ > - 64 /* Line size */ \ > - ), \ > - \ > { \ > PPTT_CLUSTER_INIT (PackageId, 0), \ > PPTT_CLUSTER_INIT (PackageId, 1), \ > @@ -219,8 +203,6 @@ typedef struct { > > typedef struct { > EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Package; > - UINT32 Offset; > - EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE Slc; > RDE1EDGE_PPTT_CLUSTER Cluster[CLUSTER_COUNT]; > } RDE1EDGE_PPTT_PACKAGE; > > diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN1Edge/Pptt.aslc b/Platform/ARM/SgiPkg/AcpiTables/RdN1Edge/Pptt.aslc > index 63056939a868..923ee9014970 100644 > --- a/Platform/ARM/SgiPkg/AcpiTables/RdN1Edge/Pptt.aslc > +++ b/Platform/ARM/SgiPkg/AcpiTables/RdN1Edge/Pptt.aslc > @@ -8,7 +8,7 @@ > * cache. Each cluster includes a 2MB L3 cache. The platform also includes a > * system level cache of 8MB. > * > -* Copyright (c) 2021, ARM Limited. All rights reserved. > +* Copyright (c) 2021 - 2022, Arm Limited. All rights reserved. > * > * SPDX-License-Identifier: BSD-2-Clause-Patent > * > @@ -132,8 +132,6 @@ > #pragma pack(1) > typedef struct { > EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Package; > - UINT32 Offset; > - EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE Slc; > RD_PPTT_CLUSTER Cluster[CLUSTER_COUNT]; > } RDN1EDGE_PPTT_PACKAGE ; > > @@ -157,21 +155,9 @@ STATIC EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE Pptt = { > > { > EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( > - OFFSET_OF (RDN1EDGE_PPTT_PACKAGE , Slc), > - PPTT_PROCESSOR_PACKAGE_FLAGS, 0, 0, 1), > + OFFSET_OF (RDN1EDGE_PPTT_PACKAGE , Cluster[0]), > + PPTT_PROCESSOR_PACKAGE_FLAGS, 0, 0, 0), > > - OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, > - Package.Slc), > - > - EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( > - PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ > - 0, /* Next level of cache */ > - SIZE_8MB, /* Size */ > - 8192, /* Num of sets */ > - 16, /* Associativity */ > - PPTT_UNIFIED_CACHE_ATTR, /* Attributes */ > - 64 /* Line size */ > - ), > { > PPTT_CLUSTER_INIT (0, 0), > PPTT_CLUSTER_INIT (0, 1), > diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Pptt.aslc b/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Pptt.aslc > index fa80544b61aa..d78afb00c3b0 100644 > --- a/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Pptt.aslc > +++ b/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Pptt.aslc > @@ -10,7 +10,7 @@ > * cluster includes a 2MB L3 cache. Each instance of the chip includes a system > * level cache of 8MB. > * > -* Copyright (c) 2021, ARM Limited. All rights reserved. > +* Copyright (c) 2021 - 2022, Arm Limited. All rights reserved. > * > * SPDX-License-Identifier: BSD-2-Clause-Patent > * > @@ -140,26 +140,11 @@ > #define PPTT_PACKAGE_INIT(PackageId) \ > { \ > EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( \ > - OFFSET_OF (RDN1EDGEX2_PPTT_PACKAGE , Slc), /* Length */ \ > + OFFSET_OF (RDN1EDGEX2_PPTT_PACKAGE , Cluster[0]), /* Length */ \ > PPTT_PROCESSOR_PACKAGE_FLAGS, /* Flag */ \ > 0, /* Parent */ \ > 0, /* ACPI Id */ \ > - 1 /* Num of private resource */ \ > - ), \ > - \ > - /* Offsets of the private resources */ \ > - OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \ > - Package[PackageId].Slc), \ > - \ > - /* SLC parameters */ \ > - EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( \ > - PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ \ > - 0, /* Next level of cache */ \ > - SIZE_8MB, /* Size */ \ > - 8192, /* Num of sets */ \ > - 16, /* Associativity */ \ > - PPTT_UNIFIED_CACHE_ATTR, /* Attributes */ \ > - 64 /* Line size */ \ > + 0 /* Num of private resource */ \ > ), \ > \ > { \ > @@ -171,8 +156,6 @@ > #pragma pack(1) > typedef struct { > EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Package; > - UINT32 Offset; > - EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE Slc; > RD_PPTT_CLUSTER Cluster[CLUSTER_COUNT]; > } RDN1EDGEX2_PPTT_PACKAGE; > > diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN2/Pptt.aslc b/Platform/ARM/SgiPkg/AcpiTables/RdN2/Pptt.aslc > index b70d583ba90c..2ee566145382 100644 > --- a/Platform/ARM/SgiPkg/AcpiTables/RdN2/Pptt.aslc > +++ b/Platform/ARM/SgiPkg/AcpiTables/RdN2/Pptt.aslc > @@ -7,7 +7,7 @@ > * cache, 64KB L1 Instruction cache and 1MB L2 cache. The platform also includes > * system level cache of 32MB. > * > -* Copyright (c) 2021, ARM Limited. All rights reserved. > +* Copyright (c) 2021 - 2022, Arm Limited. All rights reserved. > * > * SPDX-License-Identifier: BSD-2-Clause-Patent > * > @@ -116,7 +116,7 @@ > */ > typedef struct { > EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_HEADER Header; > - RD_PPTT_SLC_PACKAGE Package; > + RD_PPTT_PACKAGE Package; > } EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE; > #pragma pack () > > @@ -131,21 +131,8 @@ STATIC EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE Pptt = { > > { > EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( > - OFFSET_OF (RD_PPTT_SLC_PACKAGE, Slc), > - PPTT_PROCESSOR_PACKAGE_FLAGS, 0, 0, 1), > - > - OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, > - Package.Slc), > - > - EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( > - PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ > - 0, /* Next level of cache */ > - SIZE_32MB, /* Size */ > - 32768, /* Num of sets */ > - 16, /* Associativity */ > - PPTT_UNIFIED_CACHE_ATTR, /* Attributes */ > - 64 /* Line size */ > - ), > + OFFSET_OF (RD_PPTT_PACKAGE, Cluster[0]), > + PPTT_PROCESSOR_PACKAGE_FLAGS, 0, 0, 0), > > { > PPTT_CLUSTER_INIT (0, 0), > diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1/Pptt.aslc b/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1/Pptt.aslc > index 5890544c0b92..54eb6d6c41b3 100644 > --- a/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1/Pptt.aslc > +++ b/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1/Pptt.aslc > @@ -7,7 +7,7 @@ > * L1 Data cache, 64KB L1 Instruction cache and 1MB L2 cache. The platform also > * includes system level cache of 8MB. > * > -* Copyright (c) 2021, ARM Limited. All rights reserved. > +* Copyright (c) 2021 - 2022, Arm Limited. All rights reserved. > * SPDX-License-Identifier: BSD-2-Clause-Patent > * > * @par Specification Reference: > @@ -115,7 +115,7 @@ > */ > typedef struct { > EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_HEADER Header; > - RD_PPTT_SLC_PACKAGE Package; > + RD_PPTT_PACKAGE Package; > } EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE; > #pragma pack () > > @@ -130,21 +130,8 @@ STATIC EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE Pptt = { > > { > EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( > - OFFSET_OF (RD_PPTT_SLC_PACKAGE, Slc), > - PPTT_PROCESSOR_PACKAGE_FLAGS, 0, 0, 1), > - > - OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, > - Package.Slc), > - > - EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( > - PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ > - 0, /* Next level of cache */ > - SIZE_8MB, /* Size */ > - 8192, /* Num of sets */ > - 16, /* Associativity */ > - PPTT_UNIFIED_CACHE_ATTR, /* Attributes */ > - 64 /* Line size */ > - ), > + OFFSET_OF (RD_PPTT_PACKAGE, Cluster[0]), > + PPTT_PROCESSOR_PACKAGE_FLAGS, 0, 0, 0), > > { > PPTT_CLUSTER_INIT (0, 0), > diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdV1/Pptt.aslc b/Platform/ARM/SgiPkg/AcpiTables/RdV1/Pptt.aslc > index 06f059810fb2..d8b73c804898 100644 > --- a/Platform/ARM/SgiPkg/AcpiTables/RdV1/Pptt.aslc > +++ b/Platform/ARM/SgiPkg/AcpiTables/RdV1/Pptt.aslc > @@ -7,7 +7,7 @@ > * CPUs include 64KB L1 Data cache, 64KB L1 Instruction cache and 1MB L2 cache. > * The platform also includes a system level cache of 16MB. > * > -* Copyright (c) 2021, ARM Limited. All rights reserved. > +* Copyright (c) 2021 - 2022, Arm Limited. All rights reserved. > * > * SPDX-License-Identifier: BSD-2-Clause-Patent > * > @@ -116,7 +116,7 @@ > */ > typedef struct { > EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_HEADER Header; > - RD_PPTT_SLC_PACKAGE Package; > + RD_PPTT_PACKAGE Package; > } EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE; > #pragma pack () > > @@ -131,21 +131,8 @@ STATIC EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE Pptt = { > > { > EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( > - OFFSET_OF (RD_PPTT_SLC_PACKAGE, Slc), > - PPTT_PROCESSOR_PACKAGE_FLAGS, 0, 0, 1), > - > - OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, > - Package.Slc), > - > - EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( > - PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ > - 0, /* Next level of cache */ > - SIZE_16MB, /* Size */ > - 16384, /* Num of sets */ > - 16, /* Associativity */ > - PPTT_UNIFIED_CACHE_ATTR, /* Attributes */ > - 64 /* Line size */ > - ), > + OFFSET_OF (RD_PPTT_PACKAGE, Cluster[0]), > + PPTT_PROCESSOR_PACKAGE_FLAGS, 0, 0, 0), > > { > PPTT_CLUSTER_INIT (0, 0), > diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdV1Mc/Pptt.aslc b/Platform/ARM/SgiPkg/AcpiTables/RdV1Mc/Pptt.aslc > index 607a9eac9dc0..82124ca2ab65 100644 > --- a/Platform/ARM/SgiPkg/AcpiTables/RdV1Mc/Pptt.aslc > +++ b/Platform/ARM/SgiPkg/AcpiTables/RdV1Mc/Pptt.aslc > @@ -9,7 +9,7 @@ > * cache and 1MB L2 cache. The platform also includes a system level cache of > * 16MB per chip. > * > -* Copyright (c) 2021, ARM Limited. All rights reserved. > +* Copyright (c) 2021 - 2022, Arm Limited. All rights reserved. > * > * SPDX-License-Identifier: BSD-2-Clause-Patent > * > @@ -121,27 +121,12 @@ > #define PPTT_PACKAGE_INIT(PackageId) \ > { \ > EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( \ > - OFFSET_OF (RD_PPTT_SLC_PACKAGE, Slc), /* Length */ \ > + OFFSET_OF (RD_PPTT_PACKAGE, Cluster[0]), /* Length */ \ > PPTT_PROCESSOR_PACKAGE_FLAGS, /* Flag */ \ > 0, /* Parent */ \ > 0, /* ACPI Id */ \ > - 1 /* Num of private resource */ \ > + 0 /* Num of private resource */ \ > ), \ > - \ > - /* Offsets of the private resources */ \ > - OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \ > - Package[PackageId].Slc), \ > - \ > - EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( \ > - PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ \ > - 0, /* Next level of cache */ \ > - SIZE_16MB, /* Size */ \ > - 16384, /* Num of sets */ \ > - 16, /* Associativity */ \ > - PPTT_UNIFIED_CACHE_ATTR, /* Attributes */ \ > - 64 /* Line size */ \ > - ), \ > - \ > { \ > PPTT_CLUSTER_INIT (PackageId, 0), \ > PPTT_CLUSTER_INIT (PackageId, 1), \ > @@ -156,7 +141,7 @@ > */ > typedef struct { > EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_HEADER Header; > - RD_PPTT_SLC_PACKAGE Package[CHIP_COUNT]; > + RD_PPTT_PACKAGE Package[CHIP_COUNT]; > } EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE; > #pragma pack () > > -- > 2.17.1 >