* [edk2-non-osi: PATCH] SolidRun/Cn913xCEx7Eval: Add missing switch CPU port mode description
@ 2022-12-27 1:15 Marcin Wojtas
2023-01-03 10:29 ` Ard Biesheuvel
0 siblings, 1 reply; 2+ messages in thread
From: Marcin Wojtas @ 2022-12-27 1:15 UTC (permalink / raw)
To: devel; +Cc: quic_llindhol, ardb+tianocore, mw, jaz
The DSA device tree binding requires setting the
CPU port mode explicitly and it was missing in the CN913x CEx7
Evaluation Board swtich description. Fix that.
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
---
Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9130-cex7.dts | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9130-cex7.dts b/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9130-cex7.dts
index 50e6d69..d42911c 100644
--- a/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9130-cex7.dts
+++ b/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9130-cex7.dts
@@ -285,6 +285,11 @@
reg = <5>;
label = "cpu";
ethernet = <&cp0_eth2>;
+ phy-mode = "2500base-x";
+ fixed-link {
+ speed = <2500>;
+ full-duplex;
+ };
};
};
--
2.29.0
^ permalink raw reply related [flat|nested] 2+ messages in thread
* Re: [edk2-non-osi: PATCH] SolidRun/Cn913xCEx7Eval: Add missing switch CPU port mode description
2022-12-27 1:15 [edk2-non-osi: PATCH] SolidRun/Cn913xCEx7Eval: Add missing switch CPU port mode description Marcin Wojtas
@ 2023-01-03 10:29 ` Ard Biesheuvel
0 siblings, 0 replies; 2+ messages in thread
From: Ard Biesheuvel @ 2023-01-03 10:29 UTC (permalink / raw)
To: Marcin Wojtas; +Cc: devel, quic_llindhol, ardb+tianocore, jaz
On Tue, 27 Dec 2022 at 02:17, Marcin Wojtas <mw@semihalf.com> wrote:
>
> The DSA device tree binding requires setting the
> CPU port mode explicitly and it was missing in the CN913x CEx7
> Evaluation Board swtich description. Fix that.
>
> Signed-off-by: Marcin Wojtas <mw@semihalf.com>
> ---
> Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9130-cex7.dts | 5 +++++
> 1 file changed, 5 insertions(+)
>
> diff --git a/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9130-cex7.dts b/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9130-cex7.dts
> index 50e6d69..d42911c 100644
> --- a/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9130-cex7.dts
> +++ b/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9130-cex7.dts
> @@ -285,6 +285,11 @@
> reg = <5>;
> label = "cpu";
> ethernet = <&cp0_eth2>;
> + phy-mode = "2500base-x";
> + fixed-link {
> + speed = <2500>;
> + full-duplex;
> + };
> };
> };
>
Pushed as 61662e8596dd9a64..9a5511ca917a27e4
Thanks,
^ permalink raw reply [flat|nested] 2+ messages in thread
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2022-12-27 1:15 [edk2-non-osi: PATCH] SolidRun/Cn913xCEx7Eval: Add missing switch CPU port mode description Marcin Wojtas
2023-01-03 10:29 ` Ard Biesheuvel
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