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References: <20221227011521.812930-1-mw@semihalf.com>
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From: "Ard Biesheuvel" <ardb@kernel.org>
Date: Tue, 3 Jan 2023 11:29:26 +0100
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Subject: Re: [edk2-non-osi: PATCH] SolidRun/Cn913xCEx7Eval: Add missing switch CPU port mode description
To: Marcin Wojtas <mw@semihalf.com>
Cc: devel@edk2.groups.io, quic_llindhol@quicinc.com, ardb+tianocore@kernel.org, 
	jaz@semihalf.com
Content-Type: text/plain; charset="UTF-8"

On Tue, 27 Dec 2022 at 02:17, Marcin Wojtas <mw@semihalf.com> wrote:
>
> The DSA device tree binding requires setting the
> CPU port mode explicitly and it was missing in the CN913x CEx7
> Evaluation Board swtich description. Fix that.
>
> Signed-off-by: Marcin Wojtas <mw@semihalf.com>
> ---
>  Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9130-cex7.dts | 5 +++++
>  1 file changed, 5 insertions(+)
>
> diff --git a/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9130-cex7.dts b/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9130-cex7.dts
> index 50e6d69..d42911c 100644
> --- a/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9130-cex7.dts
> +++ b/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9130-cex7.dts
> @@ -285,6 +285,11 @@
>                                  reg = <5>;
>                                  label = "cpu";
>                                  ethernet = <&cp0_eth2>;
> +                                phy-mode = "2500base-x";
> +                                fixed-link {
> +                                        speed = <2500>;
> +                                        full-duplex;
> +                                };
>                          };
>                  };
>

Pushed as 61662e8596dd9a64..9a5511ca917a27e4

Thanks,