From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by mx.groups.io with SMTP id smtpd.web10.10269.1629640091523214869 for ; Sun, 22 Aug 2021 06:48:11 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=Nt4uJZRw; spf=pass (domain: kernel.org, ip: 198.145.29.99, mailfrom: ardb@kernel.org) Received: by mail.kernel.org (Postfix) with ESMTPSA id 33ACE61354 for ; Sun, 22 Aug 2021 13:48:10 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1629640090; bh=sYoxDnrfTT5iqKsks6F/exfPieefcSeCA27sO7mk/qM=; h=References:In-Reply-To:From:Date:Subject:To:Cc:From; b=Nt4uJZRwBKG+72nhuiCdbjIq/q2NnOcPUunoU2XFYKaRzto6hQyqSLT3veq8U8VI8 EcUV3GKjzWmjAFSYzzrts7yHE08bI2uW8YymCpbaS3KR/+ZbkrjVHnr8fFjqtqtY7O 7k/Hd3K/q0+LOsqiclRT//ZSLhnJ+CpgWbVRJ6ETQiJJddfUzrtADyYHINHo6o39ha 9d3nyjoubyDuKFvS2JaKfKZbKDqgZZ0f8AZ4hyu5kJ5AqHTrkekPv8LxlwlupDbQfT akkNTtdgcjj4A1ZBL+S0i9ryHX8BCaOj4MLadAvvtepx5pF/EvZ48L5dl0LMK6Zj3Y NK1E+1TYurMgw== Received: by mail-ot1-f44.google.com with SMTP id y14-20020a0568302a0e00b0051acbdb2869so21715415otu.2 for ; Sun, 22 Aug 2021 06:48:10 -0700 (PDT) X-Gm-Message-State: AOAM533BmjHJh+aBc5bngp1dIMvG4tY4HANInMcRjykJ/8TATyDpwgkJ nxU5ySccw5ArXGcO80nRDTa6+LrKey/l924pNn8= X-Google-Smtp-Source: ABdhPJxjC33DEfXWeRjVKbPl5F9q3rvdLGpDtzgUyHOeNJ+QGoBV1Pd+dGau/F/DoGVMjqgmBYkti79O95oe2oPtsNE= X-Received: by 2002:a9d:5cb:: with SMTP id 69mr24947292otd.90.1629640089565; Sun, 22 Aug 2021 06:48:09 -0700 (PDT) MIME-Version: 1.0 References: <20210820041619.87248-1-jeremy.linton@arm.com> <20210820041619.87248-6-jeremy.linton@arm.com> In-Reply-To: From: "Ard Biesheuvel" Date: Sun, 22 Aug 2021 15:47:58 +0200 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH v3 5/7] Silicon/Broadcom/Bcm27xx: Move linkup check into the cfg accessor To: Jeremy Linton Cc: edk2-devel-groups-io , Peter Batard , Ard Biesheuvel , Andrei Warkentin , Sunny Wang , Samer El-Haj-Mahmoud Content-Type: text/plain; charset="UTF-8" On Sun, 22 Aug 2021 at 15:37, Ard Biesheuvel wrote: > > On Fri, 20 Aug 2021 at 06:16, Jeremy Linton wrote: > > > > The existing code fails to create/finish configuring the > > pcie subsystem if it fails to get a linkup. This is reasonable > > on the RPi4 because it generally won't happen, and the OS > > could not see the root port. Now that the OS can see the > > root port, its a bit odd if it only shows up when > > something is plugged into the first slot. Lets move the > > link up check into the config accessor where it will be used > > to restrict sending CFG TLP's out the port when nothing is > > plugged in. Thus avoiding a SERROR during probe. > > > > Signed-off-by: Jeremy Linton > > How will this work when the PCIE/XHCI switch is in 'platform device' mode? > Never mind, that only affects the OS whereas this affects UEFI itself only. > > --- > > .../Bcm2711PciHostBridgeLib/Bcm2711PciHostBridgeLibConstructor.c | 5 ----- > > .../Broadcom/Bcm27xx/Library/Bcm2711PciSegmentLib/PciSegmentLib.c | 7 +++++++ > > 2 files changed, 7 insertions(+), 5 deletions(-) > > > > diff --git a/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciHostBridgeLib/Bcm2711PciHostBridgeLibConstructor.c b/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciHostBridgeLib/Bcm2711PciHostBridgeLibConstructor.c > > index 8587d2d36d..4d4c584726 100644 > > --- a/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciHostBridgeLib/Bcm2711PciHostBridgeLibConstructor.c > > +++ b/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciHostBridgeLib/Bcm2711PciHostBridgeLibConstructor.c > > @@ -204,11 +204,6 @@ Bcm2711PciHostBridgeLibConstructor ( > > } while (((Data & 0x30) != 0x030) && (Timeout)); > > DEBUG ((DEBUG_VERBOSE, "PCIe link ready (status=%x) Timeout=%d\n", Data, Timeout)); > > > > - if ((Data & 0x30) != 0x30) { > > - DEBUG ((DEBUG_ERROR, "PCIe link not ready (status=%x)\n", Data)); > > - return EFI_DEVICE_ERROR; > > - } > > - > > if ((Data & 0x80) != 0x80) { > > DEBUG ((DEBUG_ERROR, "PCIe link not in RC mode (status=%x)\n", Data)); > > return EFI_UNSUPPORTED; > > diff --git a/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciSegmentLib/PciSegmentLib.c b/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciSegmentLib/PciSegmentLib.c > > index 6d15e82fa2..b627e5730b 100644 > > --- a/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciSegmentLib/PciSegmentLib.c > > +++ b/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciSegmentLib/PciSegmentLib.c > > @@ -105,6 +105,13 @@ PciSegmentLibGetConfigBase ( > > return 0xFFFFFFFF; > > } > > > > + /* Don't probe slots if the link is down */ > > + Data = MmioRead32 (PCIE_REG_BASE + PCIE_MISC_PCIE_STATUS); > > + if ((Data & 0x30) != 0x30) { > > + DEBUG ((DEBUG_ERROR, "PCIe link not ready (status=%x)\n", Data)); > > + return 0xFFFFFFFF; > > + } > > + > > MmioWrite32 (PCIE_REG_BASE + PCIE_EXT_CFG_INDEX, Address); > > mPciSegmentLastAccess = Address; > > } > > -- > > 2.13.7 > >