From: "Ard Biesheuvel" <ardb@kernel.org>
To: Marcin Wojtas <mw@semihalf.com>
Cc: edk2-devel-groups-io <devel@edk2.groups.io>,
Leif Lindholm <leif@nuviainc.com>,
Ard Biesheuvel <ardb+tianocore@kernel.org>,
Grzegorz Jaszczyk <jaz@semihalf.com>,
Grzegorz Bernacki <gjb@semihalf.com>,
Samer El-Haj-Mahmoud <Samer.El-Haj-Mahmoud@arm.com>,
Jon Nettleton <jon@solid-run.com>,
alon.rotman@solid-run.com
Subject: Re: [edk2-platforms PATCH v2 0/4] SolidRun CEx7 Evaluation Board support
Date: Tue, 17 Aug 2021 17:56:05 +0200 [thread overview]
Message-ID: <CAMj1kXHuRqzykgFP8t=3mba9hjXVqLay5L5NCDP2k19yKhcjhg@mail.gmail.com> (raw)
In-Reply-To: <20210807193641.3355697-1-mw@semihalf.com>
On Sat, 7 Aug 2021 at 21:37, Marcin Wojtas <mw@semihalf.com> wrote:
>
> Hi,
>
> The second version comes with a minor improvement, which
> is a result of the TF-A support update and changes around the
> default IO windows configuration.
>
> The patches are also available on public branches:
> https://github.com/semihalf-wojtas-marcin/edk2-platforms/commits/cex7-r20210807
> https://github.com/semihalf-wojtas-marcin/edk2-non-osi/commits/cex7-r20210806
>
> I would appreciate any comments or remarks.
>
> Best regards,
> Marcin
>
> Changelog:
> v1->v2:
> * 3/4: update IO windows reconfiguration, in order to align to
> the TF-A changes.
>
> Marcin Wojtas (3):
> edk2-platforms:
> Marvell: Armada7k8k/OcteonTx: Select ACPI description as a default
> SolidRun/Cn913xCEx7Eval: Add ACPI support
> SolidRun/Cn913xCEx7Eval: Add platform support
>
Pushed as f24aa7708d9b..43259c414370
Thanks,
> edk2-non-osi:
> SolidRun/Cn913xCEx7Eval: Add DeviceTree
>
> Platform/SolidRun/Cn913xCEx7Eval/Cn9130Eval.dsc.inc | 54 ++
> Platform/SolidRun/Cn913xCEx7Eval/Cn9131Eval.dsc.inc | 64 +++
> Platform/SolidRun/Cn913xCEx7Eval/Cn9132Eval.dsc.inc | 64 +++
> Platform/SolidRun/Cn913xCEx7Eval/Cn913xCEx7.dsc.inc | 68 +++
> Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc | 7 +
> Platform/SolidRun/Cn913xCEx7Eval/Cn913xCEx7Eval.dsc | 57 +++
> Platform/SolidRun/Cn913xCEx7Eval/BoardDescriptionLib/BoardDescriptionLib.inf | 30 ++
> Platform/SolidRun/Cn913xCEx7Eval/NonDiscoverableInitLib/NonDiscoverableInitLib.inf | 38 ++
> Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval.inf | 61 +++
> Platform/SolidRun/Cn913xCEx7Eval/BoardDescriptionLib/BoardDescriptionLib.h | 31 ++
> Platform/SolidRun/Cn913xCEx7Eval/NonDiscoverableInitLib/NonDiscoverableInitLib.h | 13 +
> Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Dbg2.h | 9 +
> Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Pcie.h | 114 +++++
> Platform/SolidRun/Cn913xCEx7Eval/BoardDescriptionLib/BoardDescriptionLib.c | 294 +++++++++++
> Platform/SolidRun/Cn913xCEx7Eval/NonDiscoverableInitLib/NonDiscoverableInitLib.c | 89 ++++
> Platform/SolidRun/Cn913xCEx7Eval/Cn913xCEx7Eval.fdf.inc | 17 +
> Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Cn9130EvalSsdt.asl | 383 +++++++++++++++
> Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Cn9131EvalSsdt.asl | 493 +++++++++++++++++++
> Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Cn9132EvalSsdt.asl | 515 ++++++++++++++++++++
> Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Cn913xCEx7Dsdt.asl | 120 +++++
> Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Dbg2.aslc | 74 +++
> Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Mcfg.aslc | 87 ++++
> 22 files changed, 2682 insertions(+)
> create mode 100644 Platform/SolidRun/Cn913xCEx7Eval/Cn9130Eval.dsc.inc
> create mode 100644 Platform/SolidRun/Cn913xCEx7Eval/Cn9131Eval.dsc.inc
> create mode 100644 Platform/SolidRun/Cn913xCEx7Eval/Cn9132Eval.dsc.inc
> create mode 100644 Platform/SolidRun/Cn913xCEx7Eval/Cn913xCEx7.dsc.inc
> create mode 100644 Platform/SolidRun/Cn913xCEx7Eval/Cn913xCEx7Eval.dsc
> create mode 100644 Platform/SolidRun/Cn913xCEx7Eval/BoardDescriptionLib/BoardDescriptionLib.inf
> create mode 100644 Platform/SolidRun/Cn913xCEx7Eval/NonDiscoverableInitLib/NonDiscoverableInitLib.inf
> create mode 100644 Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval.inf
> create mode 100644 Platform/SolidRun/Cn913xCEx7Eval/BoardDescriptionLib/BoardDescriptionLib.h
> create mode 100644 Platform/SolidRun/Cn913xCEx7Eval/NonDiscoverableInitLib/NonDiscoverableInitLib.h
> create mode 100644 Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Dbg2.h
> create mode 100644 Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Pcie.h
> create mode 100644 Platform/SolidRun/Cn913xCEx7Eval/BoardDescriptionLib/BoardDescriptionLib.c
> create mode 100644 Platform/SolidRun/Cn913xCEx7Eval/NonDiscoverableInitLib/NonDiscoverableInitLib.c
> create mode 100644 Platform/SolidRun/Cn913xCEx7Eval/Cn913xCEx7Eval.fdf.inc
> create mode 100644 Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Cn9130EvalSsdt.asl
> create mode 100644 Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Cn9131EvalSsdt.asl
> create mode 100644 Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Cn9132EvalSsdt.asl
> create mode 100644 Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Cn913xCEx7Dsdt.asl
> create mode 100644 Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Dbg2.aslc
> create mode 100644 Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Mcfg.aslc
>
> --
> 2.29.0
>
prev parent reply other threads:[~2021-08-17 15:56 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-08-07 19:36 [edk2-platforms PATCH v2 0/4] SolidRun CEx7 Evaluation Board support Marcin Wojtas
2021-08-07 19:36 ` [edk2-platforms PATCH v2 1/3] Marvell: Armada7k8k/OcteonTx: Select ACPI description as a default Marcin Wojtas
2021-08-07 19:36 ` [edk2-platforms PATCH v2 2/3] SolidRun/Cn913xCEx7Eval: Add ACPI support Marcin Wojtas
2021-08-07 19:36 ` [edk2-platforms PATCH v2 3/3] SolidRun/Cn913xCEx7Eval: Add platform support Marcin Wojtas
2021-08-07 19:36 ` [edk2-non-osi PATCH] SolidRun/Cn913xCEx7Eval: Add DeviceTree Marcin Wojtas
2021-08-17 15:52 ` Ard Biesheuvel
2021-08-17 15:56 ` Ard Biesheuvel [this message]
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