From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-ej1-f54.google.com (mail-ej1-f54.google.com [209.85.218.54]) by mx.groups.io with SMTP id smtpd.web10.15638.1621236915911239820 for ; Mon, 17 May 2021 00:35:16 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@linaro.org header.s=google header.b=iQ6tNq7H; spf=pass (domain: linaro.org, ip: 209.85.218.54, mailfrom: etienne.carriere@linaro.org) Received: by mail-ej1-f54.google.com with SMTP id lg14so7654097ejb.9 for ; Mon, 17 May 2021 00:35:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc:content-transfer-encoding; bh=nGL35ecNfHkbBhSp2TvEsBV/dzI0+rEjqPiVnxm+m/8=; b=iQ6tNq7H4X6t/tc1Lxkw2e8GM4icCMeP3GI6EN2nWi0JybgrPbjljAvybxWcFhkWFE 1S75Sc3vT1w6uVxMLV/2K7fmgJ6w6XFvGoE9gBf9BATUads0zgilpmT9r+BwDs6m4s+m SODnWXvj7l+2UN3OcU/38gaxgXuq606pwSVbNRSpvSY0IGgCW2rZx+2pCrb4i1zMXK6s zgH9IpjnofgOQCTNuy9RIsd5McHRCvaMYusDwC7Bjh9utYIKwFHdIFS0ngINjW7FtWCP 4XoakDPycjnbT7n2R1HwZipPZIVzZyM9mvl8wMPdej7aVaP9hK3tEE0DU9Tbf7y1P0DH o0YQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc:content-transfer-encoding; bh=nGL35ecNfHkbBhSp2TvEsBV/dzI0+rEjqPiVnxm+m/8=; b=fsNOsIcR3yMwplhoWZ0XhO5PZrW+GJ4oXPYR72bIIZ6T2RRJXTi3bD6RKAE1SLrX92 itCuYN+6bDrg1yThIqfpdk7orEmyNgMByQ8umw8FBQVnEm4c/EJi/poBtUVURjV3GUd/ k1vgj/qSL61MqfT0sBf2pLzr8VpV0VzsksM6CgoLVLL1bbY3OMpntlgqdfHE+32dOckH v4WVjqsuyjFcPqmEbGAhYspoR+jhQ9we0atxcV+l1VMQbgCymQCChg+FHpJN3j0Aqlbi cRT6TcLKOwbtLiy/Dtia+vRSTEjcU/cCxwpojiwz3Pl/iZGh6mjzuIOYIOI5XmfN3HPX 7bdg== X-Gm-Message-State: AOAM531z3uHn3i1pshjpNTmvY4S87qY6oQK1rZV01olxZj/TefwdNNns y8oaalj9ZRaBWAbOPtCns3nhCUqrrh0ZwRi4+IU7kw== X-Google-Smtp-Source: ABdhPJxpjuGKmH/ZUllNYdmmTWZABwTMSKPqzYWeR06tSYKRgWdcYW85hApi43/MJy7Nx74ohAG48RgEhUKnmzI6fKI= X-Received: by 2002:a17:906:3544:: with SMTP id s4mr62174706eja.73.1621236914269; Mon, 17 May 2021 00:35:14 -0700 (PDT) MIME-Version: 1.0 References: <20210517054911.30665-1-etienne.carriere@linaro.org> <20210517054911.30665-3-etienne.carriere@linaro.org> <006301d74aed$9c7a14f0$d56e3ed0$@byosoft.com.cn> In-Reply-To: <006301d74aed$9c7a14f0$d56e3ed0$@byosoft.com.cn> From: "Etienne Carriere" Date: Mon, 17 May 2021 09:35:03 +0200 Message-ID: Subject: Re: [PATCH v2 3/5] GenFv: Arm: support images entered in Thumb mode To: gaoliming Cc: devel@edk2.groups.io, Achin Gupta , Ard Biesheuvel , Jiewen Yao , Leif Lindholm , Sami Mujawar , Sughosh Ganu , Bob Feng Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Mon, 17 May 2021 at 09:24, gaoliming wrote: > > Acked-by: Liming Gao > > > -----=E9=82=AE=E4=BB=B6=E5=8E=9F=E4=BB=B6----- > > =E5=8F=91=E4=BB=B6=E4=BA=BA: Etienne Carriere > > =E5=8F=91=E9=80=81=E6=97=B6=E9=97=B4: 2021=E5=B9=B45=E6=9C=8817=E6=97= =A5 13:49 > > =E6=94=B6=E4=BB=B6=E4=BA=BA: devel@edk2.groups.io > > =E6=8A=84=E9=80=81: Achin Gupta ; Ard Biesheuvel > > ; Jiewen Yao ; Leif > > Lindholm ; Sami Mujawar ; > > Sughosh Ganu ; Etienne Carriere > > ; Bob Feng ; Liming > > Gao > > =E4=B8=BB=E9=A2=98: [PATCH v2 3/5] GenFv: Arm: support images entered i= n Thumb mode > > > > Change GenFv for Arm architecture to generate a specific jump > > instruction as image entry instruction, when the target entry label > > is assembled with Thumb instruction set. This is possible since > > SecCoreEntryAddress value fetched from the PE32 has its LSBit set when > > the entry instruction executes in Thumb mode. > > > > Cc: Bob Feng > > Cc: Liming Gao > > Cc: Achin Gupta > > Cc: Ard Biesheuvel > > Cc: Leif Lindholm > > Cc: Sughosh Ganu > > Signed-off-by: Etienne Carriere > > --- > > Changes since v1: > > - Fix typos in commit log and inline comments > > - Change if() test operand to be an explicit boolean > > --- > > BaseTools/Source/C/GenFv/GenFvInternalLib.c | 38 +++++++++++++++----- > > 1 file changed, 29 insertions(+), 9 deletions(-) > > > > diff --git a/BaseTools/Source/C/GenFv/GenFvInternalLib.c > > b/BaseTools/Source/C/GenFv/GenFvInternalLib.c > > index 6e296b8ad6..5f3fd4f808 100644 > > --- a/BaseTools/Source/C/GenFv/GenFvInternalLib.c > > +++ b/BaseTools/Source/C/GenFv/GenFvInternalLib.c > > @@ -34,9 +34,27 @@ SPDX-License-Identifier: BSD-2-Clause-Patent > > #include "FvLib.h" > > #include "PeCoffLib.h" > > > > -#define ARMT_UNCONDITIONAL_JUMP_INSTRUCTION > > 0xEB000000 > > #define ARM64_UNCONDITIONAL_JUMP_INSTRUCTION > > 0x14000000 > > > > +/* > > + * Arm instruction to jump to Fv entry instruction in Arm or Thumb mod= e. > > + * From ARM Arch Ref Manual versions b/c/d, section A8.8.25 BL, BLX > > (immediate) > > + * BLX (encoding A2) branches to offset in Thumb instruction set mode. > > + * BL (encoding A1) branches to offset in Arm instruction set mode. > > + */ > > +#define ARM_JUMP_OFFSET_MAX 0xffffff > > +#define ARM_JUMP_TO_ARM(Offset) (0xeb000000 | ((Offset - 8) >> 2)) > > + > > +#define _ARM_JUMP_TO_THUMB(Imm32) (0xfa000000 | \ > > + (((Imm32) & (1 << 1)) << (24 - 1)) > > | \ > > + (((Imm32) >> 2) & 0x7fffff)) > > +#define ARM_JUMP_TO_THUMB(Offset) > > _ARM_JUMP_TO_THUMB((Offset) - 8) > > + > > +/* > > + * Arm instruction to retrun from exception (MOVS PC, LR) > > + */ > > +#define ARM_RETURN_FROM_EXCEPTION 0xE1B0F07E > > + > > BOOLEAN mArm =3D FALSE; > > BOOLEAN mRiscV =3D FALSE; > > STATIC UINT32 MaxFfsAlignment =3D 0; > > @@ -2203,23 +2221,25 @@ Returns: > > // if we found an SEC core entry point then generate a branch > > instruction > > // to it and populate a debugger SWI entry as well > > if (UpdateVectorSec) { > > + UINT32 EntryOffset; > > > > VerboseMsg("UpdateArmResetVectorIfNeeded updating ARM SEC > > vector"); > > > > - // B SecEntryPoint - signed_immed_24 part +/-32MB offset > > - // on ARM, the PC is always 8 ahead, so we're not really jumping > from > > the base address, but from base address + 8 > > - ResetVector[0] =3D (INT32)(SecCoreEntryAddress - > > FvInfo->BaseAddress - 8) >> 2; > > + EntryOffset =3D (INT32)(SecCoreEntryAddress - FvInfo->BaseAddres= s); > > > > - if (ResetVector[0] > 0x00FFFFFF) { > > - Error(NULL, 0, 3000, "Invalid", "SEC Entry point must be withi= n > > 32MB of the start of the FV"); > > + if (EntryOffset > ARM_JUMP_OFFSET_MAX) { > > + Error(NULL, 0, 3000, "Invalid", "SEC Entry point offset abov= e > > 1MB of the start of the FV"); > > return EFI_ABORTED; > > } > > > > - // Add opcode for an unconditional branch with no link. i.e.: " = B > > SecEntryPoint" > > - ResetVector[0] |=3D ARMT_UNCONDITIONAL_JUMP_INSTRUCTION; > > + if (SecCoreEntryAddress & 1 !=3D 0) { Sorry, I missed this one. This needs extra parantheses. I'll sent a v3. My apologies... etienne > > + ResetVector[0] =3D ARM_JUMP_TO_THUMB(EntryOffset); > > + } else { > > + ResetVector[0] =3D ARM_JUMP_TO_ARM(EntryOffset); > > + } > > > > // SWI handler movs pc,lr. Just in case a debugger uses SWI > > - ResetVector[2] =3D 0xE1B0F07E; > > + ResetVector[2] =3D ARM_RETURN_FROM_EXCEPTION; > > > > // Place holder to support a common interrupt handler from ROM. > > // Currently not supported. For this to be used the reset vector > would > > not be in this FV > > -- > > 2.17.1 > > >