* [PATCH v2 2/5] ArmPkg: prepare 32bit ARM build of StandaloneMmPkg
2021-05-17 5:49 [PATCH v2 1/5] ArmPkg/IndustryStandard: 32b/64b agnostic FF-A, Mm SVC and Std SMC IDs Etienne Carriere
@ 2021-05-17 5:49 ` Etienne Carriere
2021-05-17 5:49 ` [PATCH v2 3/5] GenFv: Arm: support images entered in Thumb mode Etienne Carriere
` (2 subsequent siblings)
3 siblings, 0 replies; 10+ messages in thread
From: Etienne Carriere @ 2021-05-17 5:49 UTC (permalink / raw)
To: devel
Cc: Achin Gupta, Ard Biesheuvel, Jiewen Yao, Leif Lindholm,
Sami Mujawar, Sughosh Ganu, Etienne Carriere
Changes in ArmPkg to prepare building StandaloneMm firmware for
32bit Arm architectures.
Adds MmCommunicationDxe driver and ArmMmuPeiLib and
ArmmmuStandaloneMmLib libraries to the list of the standard
components build for ArmPkg on when ARM architectures.
Changes path of source file AArch64/ArmMmuStandaloneMmLib.c
and compile it for both 32bit and 64bit architectures.
Cc: Achin Gupta <achin.gupta@arm.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Sughosh Ganu <sughosh.ganu@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
---
No change since v1
---
ArmPkg/ArmPkg.dec | 2 +-
ArmPkg/ArmPkg.dsc | 2 +-
ArmPkg/Drivers/MmCommunicationDxe/MmCommunication.c | 2 +-
ArmPkg/Library/StandaloneMmMmuLib/{AArch64 => }/ArmMmuStandaloneMmLib.c | 15 ++++++++-------
ArmPkg/Library/StandaloneMmMmuLib/ArmMmuStandaloneMmLib.inf | 6 +++---
5 files changed, 14 insertions(+), 13 deletions(-)
diff --git a/ArmPkg/ArmPkg.dec b/ArmPkg/ArmPkg.dec
index 214b2f5892..6ed51edd03 100644
--- a/ArmPkg/ArmPkg.dec
+++ b/ArmPkg/ArmPkg.dec
@@ -137,7 +137,7 @@
# hardware coherency (i.e., no virtualization or cache coherent DMA)
gArmTokenSpaceGuid.PcdNormalMemoryNonshareableOverride|FALSE|BOOLEAN|0x00000043
-[PcdsFeatureFlag.AARCH64]
+[PcdsFeatureFlag.AARCH64, PcdsFeatureFlag.ARM]
## Used to select method for requesting services from S-EL1.<BR><BR>
# TRUE - Selects FF-A calls for communication between S-EL0 and SPMC.<BR>
# FALSE - Selects SVC calls for communication between S-EL0 and SPMC.<BR>
diff --git a/ArmPkg/ArmPkg.dsc b/ArmPkg/ArmPkg.dsc
index 926986cf7f..4c79dadf9e 100644
--- a/ArmPkg/ArmPkg.dsc
+++ b/ArmPkg/ArmPkg.dsc
@@ -158,7 +158,7 @@
ArmPkg/Universal/Smbios/SmbiosMiscDxe/SmbiosMiscDxe.inf
ArmPkg/Universal/Smbios/OemMiscLibNull/OemMiscLibNull.inf
-[Components.AARCH64]
+[Components.AARCH64, Components.ARM]
ArmPkg/Drivers/MmCommunicationDxe/MmCommunication.inf
ArmPkg/Library/ArmMmuLib/ArmMmuPeiLib.inf
ArmPkg/Library/StandaloneMmMmuLib/ArmMmuStandaloneMmLib.inf
diff --git a/ArmPkg/Drivers/MmCommunicationDxe/MmCommunication.c b/ArmPkg/Drivers/MmCommunicationDxe/MmCommunication.c
index b1e3095809..4ae38a9f22 100644
--- a/ArmPkg/Drivers/MmCommunicationDxe/MmCommunication.c
+++ b/ArmPkg/Drivers/MmCommunicationDxe/MmCommunication.c
@@ -125,7 +125,7 @@ MmCommunication2Communicate (
}
// SMC Function ID
- CommunicateSmcArgs.Arg0 = ARM_SMC_ID_MM_COMMUNICATE_AARCH64;
+ CommunicateSmcArgs.Arg0 = ARM_SMC_ID_MM_COMMUNICATE;
// Cookie
CommunicateSmcArgs.Arg1 = 0;
diff --git a/ArmPkg/Library/StandaloneMmMmuLib/AArch64/ArmMmuStandaloneMmLib.c b/ArmPkg/Library/StandaloneMmMmuLib/ArmMmuStandaloneMmLib.c
similarity index 92%
rename from ArmPkg/Library/StandaloneMmMmuLib/AArch64/ArmMmuStandaloneMmLib.c
rename to ArmPkg/Library/StandaloneMmMmuLib/ArmMmuStandaloneMmLib.c
index dd014beec8..20f873e680 100644
--- a/ArmPkg/Library/StandaloneMmMmuLib/AArch64/ArmMmuStandaloneMmLib.c
+++ b/ArmPkg/Library/StandaloneMmMmuLib/ArmMmuStandaloneMmLib.c
@@ -2,6 +2,7 @@
File managing the MMU for ARMv8 architecture in S-EL0
Copyright (c) 2017 - 2021, Arm Limited. All rights reserved.<BR>
+ Copyright (c) 2021, Linaro Limited
SPDX-License-Identifier: BSD-2-Clause-Patent
@par Reference(s):
@@ -62,7 +63,7 @@ SendMemoryPermissionRequest (
// for other Direct Request calls which are not atomic
// We therefore check only for Direct Response by the
// callee.
- if (SvcArgs->Arg0 == ARM_SVC_ID_FFA_MSG_SEND_DIRECT_RESP_AARCH64) {
+ if (SvcArgs->Arg0 == ARM_SVC_ID_FFA_MSG_SEND_DIRECT_RESP) {
// A Direct Response means FF-A success
// Now check the payload for errors
// The callee sends back the return value
@@ -164,13 +165,13 @@ GetMemoryPermissions (
ZeroMem (&SvcArgs, sizeof (ARM_SVC_ARGS));
if (FeaturePcdGet (PcdFfaEnable)) {
// See [2], Section 10.2 FFA_MSG_SEND_DIRECT_REQ.
- SvcArgs.Arg0 = ARM_SVC_ID_FFA_MSG_SEND_DIRECT_REQ_AARCH64;
+ SvcArgs.Arg0 = ARM_SVC_ID_FFA_MSG_SEND_DIRECT_REQ;
SvcArgs.Arg1 = ARM_FFA_DESTINATION_ENDPOINT_ID;
SvcArgs.Arg2 = 0;
- SvcArgs.Arg3 = ARM_SVC_ID_SP_GET_MEM_ATTRIBUTES_AARCH64;
+ SvcArgs.Arg3 = ARM_SVC_ID_SP_GET_MEM_ATTRIBUTES;
SvcArgs.Arg4 = BaseAddress;
} else {
- SvcArgs.Arg0 = ARM_SVC_ID_SP_GET_MEM_ATTRIBUTES_AARCH64;
+ SvcArgs.Arg0 = ARM_SVC_ID_SP_GET_MEM_ATTRIBUTES;
SvcArgs.Arg1 = BaseAddress;
SvcArgs.Arg2 = 0;
SvcArgs.Arg3 = 0;
@@ -219,15 +220,15 @@ RequestMemoryPermissionChange (
ZeroMem (&SvcArgs, sizeof (ARM_SVC_ARGS));
if (FeaturePcdGet (PcdFfaEnable)) {
// See [2], Section 10.2 FFA_MSG_SEND_DIRECT_REQ.
- SvcArgs.Arg0 = ARM_SVC_ID_FFA_MSG_SEND_DIRECT_REQ_AARCH64;
+ SvcArgs.Arg0 = ARM_SVC_ID_FFA_MSG_SEND_DIRECT_REQ;
SvcArgs.Arg1 = ARM_FFA_DESTINATION_ENDPOINT_ID;
SvcArgs.Arg2 = 0;
- SvcArgs.Arg3 = ARM_SVC_ID_SP_SET_MEM_ATTRIBUTES_AARCH64;
+ SvcArgs.Arg3 = ARM_SVC_ID_SP_SET_MEM_ATTRIBUTES;
SvcArgs.Arg4 = BaseAddress;
SvcArgs.Arg5 = EFI_SIZE_TO_PAGES (Length);
SvcArgs.Arg6 = Permissions;
} else {
- SvcArgs.Arg0 = ARM_SVC_ID_SP_SET_MEM_ATTRIBUTES_AARCH64;
+ SvcArgs.Arg0 = ARM_SVC_ID_SP_SET_MEM_ATTRIBUTES;
SvcArgs.Arg1 = BaseAddress;
SvcArgs.Arg2 = EFI_SIZE_TO_PAGES (Length);
SvcArgs.Arg3 = Permissions;
diff --git a/ArmPkg/Library/StandaloneMmMmuLib/ArmMmuStandaloneMmLib.inf b/ArmPkg/Library/StandaloneMmMmuLib/ArmMmuStandaloneMmLib.inf
index 6c71fe0023..ff20e58980 100644
--- a/ArmPkg/Library/StandaloneMmMmuLib/ArmMmuStandaloneMmLib.inf
+++ b/ArmPkg/Library/StandaloneMmMmuLib/ArmMmuStandaloneMmLib.inf
@@ -16,14 +16,14 @@
LIBRARY_CLASS = StandaloneMmMmuLib
PI_SPECIFICATION_VERSION = 0x00010032
-[Sources.AARCH64]
- AArch64/ArmMmuStandaloneMmLib.c
+[Sources]
+ ArmMmuStandaloneMmLib.c
[Packages]
ArmPkg/ArmPkg.dec
MdePkg/MdePkg.dec
-[FeaturePcd.AARCH64]
+[FeaturePcd.ARM, FeaturePcd.AARCH64]
gArmTokenSpaceGuid.PcdFfaEnable
[LibraryClasses]
--
2.17.1
^ permalink raw reply related [flat|nested] 10+ messages in thread* [PATCH v2 3/5] GenFv: Arm: support images entered in Thumb mode
2021-05-17 5:49 [PATCH v2 1/5] ArmPkg/IndustryStandard: 32b/64b agnostic FF-A, Mm SVC and Std SMC IDs Etienne Carriere
2021-05-17 5:49 ` [PATCH v2 2/5] ArmPkg: prepare 32bit ARM build of StandaloneMmPkg Etienne Carriere
@ 2021-05-17 5:49 ` Etienne Carriere
2021-05-17 7:24 ` 回复: " gaoliming
2021-05-17 5:49 ` [PATCH v2 4/5] StandaloneMmPkg: fix pointer/int casts against 32bit architectures Etienne Carriere
2021-05-17 5:49 ` [PATCH v2 5/5] StandaloneMmPkg: build for 32bit arm machines Etienne Carriere
3 siblings, 1 reply; 10+ messages in thread
From: Etienne Carriere @ 2021-05-17 5:49 UTC (permalink / raw)
To: devel
Cc: Achin Gupta, Ard Biesheuvel, Jiewen Yao, Leif Lindholm,
Sami Mujawar, Sughosh Ganu, Etienne Carriere, Bob Feng,
Liming Gao
Change GenFv for Arm architecture to generate a specific jump
instruction as image entry instruction, when the target entry label
is assembled with Thumb instruction set. This is possible since
SecCoreEntryAddress value fetched from the PE32 has its LSBit set when
the entry instruction executes in Thumb mode.
Cc: Bob Feng <bob.c.feng@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Achin Gupta <achin.gupta@arm.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Sughosh Ganu <sughosh.ganu@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
---
Changes since v1:
- Fix typos in commit log and inline comments
- Change if() test operand to be an explicit boolean
---
BaseTools/Source/C/GenFv/GenFvInternalLib.c | 38 +++++++++++++++-----
1 file changed, 29 insertions(+), 9 deletions(-)
diff --git a/BaseTools/Source/C/GenFv/GenFvInternalLib.c b/BaseTools/Source/C/GenFv/GenFvInternalLib.c
index 6e296b8ad6..5f3fd4f808 100644
--- a/BaseTools/Source/C/GenFv/GenFvInternalLib.c
+++ b/BaseTools/Source/C/GenFv/GenFvInternalLib.c
@@ -34,9 +34,27 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#include "FvLib.h"
#include "PeCoffLib.h"
-#define ARMT_UNCONDITIONAL_JUMP_INSTRUCTION 0xEB000000
#define ARM64_UNCONDITIONAL_JUMP_INSTRUCTION 0x14000000
+/*
+ * Arm instruction to jump to Fv entry instruction in Arm or Thumb mode.
+ * From ARM Arch Ref Manual versions b/c/d, section A8.8.25 BL, BLX (immediate)
+ * BLX (encoding A2) branches to offset in Thumb instruction set mode.
+ * BL (encoding A1) branches to offset in Arm instruction set mode.
+ */
+#define ARM_JUMP_OFFSET_MAX 0xffffff
+#define ARM_JUMP_TO_ARM(Offset) (0xeb000000 | ((Offset - 8) >> 2))
+
+#define _ARM_JUMP_TO_THUMB(Imm32) (0xfa000000 | \
+ (((Imm32) & (1 << 1)) << (24 - 1)) | \
+ (((Imm32) >> 2) & 0x7fffff))
+#define ARM_JUMP_TO_THUMB(Offset) _ARM_JUMP_TO_THUMB((Offset) - 8)
+
+/*
+ * Arm instruction to retrun from exception (MOVS PC, LR)
+ */
+#define ARM_RETURN_FROM_EXCEPTION 0xE1B0F07E
+
BOOLEAN mArm = FALSE;
BOOLEAN mRiscV = FALSE;
STATIC UINT32 MaxFfsAlignment = 0;
@@ -2203,23 +2221,25 @@ Returns:
// if we found an SEC core entry point then generate a branch instruction
// to it and populate a debugger SWI entry as well
if (UpdateVectorSec) {
+ UINT32 EntryOffset;
VerboseMsg("UpdateArmResetVectorIfNeeded updating ARM SEC vector");
- // B SecEntryPoint - signed_immed_24 part +/-32MB offset
- // on ARM, the PC is always 8 ahead, so we're not really jumping from the base address, but from base address + 8
- ResetVector[0] = (INT32)(SecCoreEntryAddress - FvInfo->BaseAddress - 8) >> 2;
+ EntryOffset = (INT32)(SecCoreEntryAddress - FvInfo->BaseAddress);
- if (ResetVector[0] > 0x00FFFFFF) {
- Error(NULL, 0, 3000, "Invalid", "SEC Entry point must be within 32MB of the start of the FV");
+ if (EntryOffset > ARM_JUMP_OFFSET_MAX) {
+ Error(NULL, 0, 3000, "Invalid", "SEC Entry point offset above 1MB of the start of the FV");
return EFI_ABORTED;
}
- // Add opcode for an unconditional branch with no link. i.e.: " B SecEntryPoint"
- ResetVector[0] |= ARMT_UNCONDITIONAL_JUMP_INSTRUCTION;
+ if (SecCoreEntryAddress & 1 != 0) {
+ ResetVector[0] = ARM_JUMP_TO_THUMB(EntryOffset);
+ } else {
+ ResetVector[0] = ARM_JUMP_TO_ARM(EntryOffset);
+ }
// SWI handler movs pc,lr. Just in case a debugger uses SWI
- ResetVector[2] = 0xE1B0F07E;
+ ResetVector[2] = ARM_RETURN_FROM_EXCEPTION;
// Place holder to support a common interrupt handler from ROM.
// Currently not supported. For this to be used the reset vector would not be in this FV
--
2.17.1
^ permalink raw reply related [flat|nested] 10+ messages in thread* 回复: [PATCH v2 3/5] GenFv: Arm: support images entered in Thumb mode
2021-05-17 5:49 ` [PATCH v2 3/5] GenFv: Arm: support images entered in Thumb mode Etienne Carriere
@ 2021-05-17 7:24 ` gaoliming
2021-05-17 7:35 ` Etienne Carriere
0 siblings, 1 reply; 10+ messages in thread
From: gaoliming @ 2021-05-17 7:24 UTC (permalink / raw)
To: 'Etienne Carriere', devel
Cc: 'Achin Gupta', 'Ard Biesheuvel',
'Jiewen Yao', 'Leif Lindholm',
'Sami Mujawar', 'Sughosh Ganu',
'Bob Feng'
Acked-by: Liming Gao <gaoliming@byosoft.com.cn>
> -----邮件原件-----
> 发件人: Etienne Carriere <etienne.carriere@linaro.org>
> 发送时间: 2021年5月17日 13:49
> 收件人: devel@edk2.groups.io
> 抄送: Achin Gupta <achin.gupta@arm.com>; Ard Biesheuvel
> <ardb+tianocore@kernel.org>; Jiewen Yao <jiewen.yao@intel.com>; Leif
> Lindholm <leif@nuviainc.com>; Sami Mujawar <sami.mujawar@arm.com>;
> Sughosh Ganu <sughosh.ganu@linaro.org>; Etienne Carriere
> <etienne.carriere@linaro.org>; Bob Feng <bob.c.feng@intel.com>; Liming
> Gao <gaoliming@byosoft.com.cn>
> 主题: [PATCH v2 3/5] GenFv: Arm: support images entered in Thumb mode
>
> Change GenFv for Arm architecture to generate a specific jump
> instruction as image entry instruction, when the target entry label
> is assembled with Thumb instruction set. This is possible since
> SecCoreEntryAddress value fetched from the PE32 has its LSBit set when
> the entry instruction executes in Thumb mode.
>
> Cc: Bob Feng <bob.c.feng@intel.com>
> Cc: Liming Gao <gaoliming@byosoft.com.cn>
> Cc: Achin Gupta <achin.gupta@arm.com>
> Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
> Cc: Leif Lindholm <leif@nuviainc.com>
> Cc: Sughosh Ganu <sughosh.ganu@linaro.org>
> Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
> ---
> Changes since v1:
> - Fix typos in commit log and inline comments
> - Change if() test operand to be an explicit boolean
> ---
> BaseTools/Source/C/GenFv/GenFvInternalLib.c | 38 +++++++++++++++-----
> 1 file changed, 29 insertions(+), 9 deletions(-)
>
> diff --git a/BaseTools/Source/C/GenFv/GenFvInternalLib.c
> b/BaseTools/Source/C/GenFv/GenFvInternalLib.c
> index 6e296b8ad6..5f3fd4f808 100644
> --- a/BaseTools/Source/C/GenFv/GenFvInternalLib.c
> +++ b/BaseTools/Source/C/GenFv/GenFvInternalLib.c
> @@ -34,9 +34,27 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
> #include "FvLib.h"
> #include "PeCoffLib.h"
>
> -#define ARMT_UNCONDITIONAL_JUMP_INSTRUCTION
> 0xEB000000
> #define ARM64_UNCONDITIONAL_JUMP_INSTRUCTION
> 0x14000000
>
> +/*
> + * Arm instruction to jump to Fv entry instruction in Arm or Thumb mode.
> + * From ARM Arch Ref Manual versions b/c/d, section A8.8.25 BL, BLX
> (immediate)
> + * BLX (encoding A2) branches to offset in Thumb instruction set mode.
> + * BL (encoding A1) branches to offset in Arm instruction set mode.
> + */
> +#define ARM_JUMP_OFFSET_MAX 0xffffff
> +#define ARM_JUMP_TO_ARM(Offset) (0xeb000000 | ((Offset - 8) >> 2))
> +
> +#define _ARM_JUMP_TO_THUMB(Imm32) (0xfa000000 | \
> + (((Imm32) & (1 << 1)) << (24 - 1))
> | \
> + (((Imm32) >> 2) & 0x7fffff))
> +#define ARM_JUMP_TO_THUMB(Offset)
> _ARM_JUMP_TO_THUMB((Offset) - 8)
> +
> +/*
> + * Arm instruction to retrun from exception (MOVS PC, LR)
> + */
> +#define ARM_RETURN_FROM_EXCEPTION 0xE1B0F07E
> +
> BOOLEAN mArm = FALSE;
> BOOLEAN mRiscV = FALSE;
> STATIC UINT32 MaxFfsAlignment = 0;
> @@ -2203,23 +2221,25 @@ Returns:
> // if we found an SEC core entry point then generate a branch
> instruction
> // to it and populate a debugger SWI entry as well
> if (UpdateVectorSec) {
> + UINT32 EntryOffset;
>
> VerboseMsg("UpdateArmResetVectorIfNeeded updating ARM SEC
> vector");
>
> - // B SecEntryPoint - signed_immed_24 part +/-32MB offset
> - // on ARM, the PC is always 8 ahead, so we're not really jumping
from
> the base address, but from base address + 8
> - ResetVector[0] = (INT32)(SecCoreEntryAddress -
> FvInfo->BaseAddress - 8) >> 2;
> + EntryOffset = (INT32)(SecCoreEntryAddress - FvInfo->BaseAddress);
>
> - if (ResetVector[0] > 0x00FFFFFF) {
> - Error(NULL, 0, 3000, "Invalid", "SEC Entry point must be within
> 32MB of the start of the FV");
> + if (EntryOffset > ARM_JUMP_OFFSET_MAX) {
> + Error(NULL, 0, 3000, "Invalid", "SEC Entry point offset above
> 1MB of the start of the FV");
> return EFI_ABORTED;
> }
>
> - // Add opcode for an unconditional branch with no link. i.e.: " B
> SecEntryPoint"
> - ResetVector[0] |= ARMT_UNCONDITIONAL_JUMP_INSTRUCTION;
> + if (SecCoreEntryAddress & 1 != 0) {
> + ResetVector[0] = ARM_JUMP_TO_THUMB(EntryOffset);
> + } else {
> + ResetVector[0] = ARM_JUMP_TO_ARM(EntryOffset);
> + }
>
> // SWI handler movs pc,lr. Just in case a debugger uses SWI
> - ResetVector[2] = 0xE1B0F07E;
> + ResetVector[2] = ARM_RETURN_FROM_EXCEPTION;
>
> // Place holder to support a common interrupt handler from ROM.
> // Currently not supported. For this to be used the reset vector
would
> not be in this FV
> --
> 2.17.1
^ permalink raw reply [flat|nested] 10+ messages in thread* Re: [PATCH v2 3/5] GenFv: Arm: support images entered in Thumb mode
2021-05-17 7:24 ` 回复: " gaoliming
@ 2021-05-17 7:35 ` Etienne Carriere
2021-05-17 7:47 ` 回复: [edk2-devel] " gaoliming
0 siblings, 1 reply; 10+ messages in thread
From: Etienne Carriere @ 2021-05-17 7:35 UTC (permalink / raw)
To: gaoliming
Cc: devel, Achin Gupta, Ard Biesheuvel, Jiewen Yao, Leif Lindholm,
Sami Mujawar, Sughosh Ganu, Bob Feng
On Mon, 17 May 2021 at 09:24, gaoliming <gaoliming@byosoft.com.cn> wrote:
>
> Acked-by: Liming Gao <gaoliming@byosoft.com.cn>
>
> > -----邮件原件-----
> > 发件人: Etienne Carriere <etienne.carriere@linaro.org>
> > 发送时间: 2021年5月17日 13:49
> > 收件人: devel@edk2.groups.io
> > 抄送: Achin Gupta <achin.gupta@arm.com>; Ard Biesheuvel
> > <ardb+tianocore@kernel.org>; Jiewen Yao <jiewen.yao@intel.com>; Leif
> > Lindholm <leif@nuviainc.com>; Sami Mujawar <sami.mujawar@arm.com>;
> > Sughosh Ganu <sughosh.ganu@linaro.org>; Etienne Carriere
> > <etienne.carriere@linaro.org>; Bob Feng <bob.c.feng@intel.com>; Liming
> > Gao <gaoliming@byosoft.com.cn>
> > 主题: [PATCH v2 3/5] GenFv: Arm: support images entered in Thumb mode
> >
> > Change GenFv for Arm architecture to generate a specific jump
> > instruction as image entry instruction, when the target entry label
> > is assembled with Thumb instruction set. This is possible since
> > SecCoreEntryAddress value fetched from the PE32 has its LSBit set when
> > the entry instruction executes in Thumb mode.
> >
> > Cc: Bob Feng <bob.c.feng@intel.com>
> > Cc: Liming Gao <gaoliming@byosoft.com.cn>
> > Cc: Achin Gupta <achin.gupta@arm.com>
> > Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
> > Cc: Leif Lindholm <leif@nuviainc.com>
> > Cc: Sughosh Ganu <sughosh.ganu@linaro.org>
> > Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
> > ---
> > Changes since v1:
> > - Fix typos in commit log and inline comments
> > - Change if() test operand to be an explicit boolean
> > ---
> > BaseTools/Source/C/GenFv/GenFvInternalLib.c | 38 +++++++++++++++-----
> > 1 file changed, 29 insertions(+), 9 deletions(-)
> >
> > diff --git a/BaseTools/Source/C/GenFv/GenFvInternalLib.c
> > b/BaseTools/Source/C/GenFv/GenFvInternalLib.c
> > index 6e296b8ad6..5f3fd4f808 100644
> > --- a/BaseTools/Source/C/GenFv/GenFvInternalLib.c
> > +++ b/BaseTools/Source/C/GenFv/GenFvInternalLib.c
> > @@ -34,9 +34,27 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
> > #include "FvLib.h"
> > #include "PeCoffLib.h"
> >
> > -#define ARMT_UNCONDITIONAL_JUMP_INSTRUCTION
> > 0xEB000000
> > #define ARM64_UNCONDITIONAL_JUMP_INSTRUCTION
> > 0x14000000
> >
> > +/*
> > + * Arm instruction to jump to Fv entry instruction in Arm or Thumb mode.
> > + * From ARM Arch Ref Manual versions b/c/d, section A8.8.25 BL, BLX
> > (immediate)
> > + * BLX (encoding A2) branches to offset in Thumb instruction set mode.
> > + * BL (encoding A1) branches to offset in Arm instruction set mode.
> > + */
> > +#define ARM_JUMP_OFFSET_MAX 0xffffff
> > +#define ARM_JUMP_TO_ARM(Offset) (0xeb000000 | ((Offset - 8) >> 2))
> > +
> > +#define _ARM_JUMP_TO_THUMB(Imm32) (0xfa000000 | \
> > + (((Imm32) & (1 << 1)) << (24 - 1))
> > | \
> > + (((Imm32) >> 2) & 0x7fffff))
> > +#define ARM_JUMP_TO_THUMB(Offset)
> > _ARM_JUMP_TO_THUMB((Offset) - 8)
> > +
> > +/*
> > + * Arm instruction to retrun from exception (MOVS PC, LR)
> > + */
> > +#define ARM_RETURN_FROM_EXCEPTION 0xE1B0F07E
> > +
> > BOOLEAN mArm = FALSE;
> > BOOLEAN mRiscV = FALSE;
> > STATIC UINT32 MaxFfsAlignment = 0;
> > @@ -2203,23 +2221,25 @@ Returns:
> > // if we found an SEC core entry point then generate a branch
> > instruction
> > // to it and populate a debugger SWI entry as well
> > if (UpdateVectorSec) {
> > + UINT32 EntryOffset;
> >
> > VerboseMsg("UpdateArmResetVectorIfNeeded updating ARM SEC
> > vector");
> >
> > - // B SecEntryPoint - signed_immed_24 part +/-32MB offset
> > - // on ARM, the PC is always 8 ahead, so we're not really jumping
> from
> > the base address, but from base address + 8
> > - ResetVector[0] = (INT32)(SecCoreEntryAddress -
> > FvInfo->BaseAddress - 8) >> 2;
> > + EntryOffset = (INT32)(SecCoreEntryAddress - FvInfo->BaseAddress);
> >
> > - if (ResetVector[0] > 0x00FFFFFF) {
> > - Error(NULL, 0, 3000, "Invalid", "SEC Entry point must be within
> > 32MB of the start of the FV");
> > + if (EntryOffset > ARM_JUMP_OFFSET_MAX) {
> > + Error(NULL, 0, 3000, "Invalid", "SEC Entry point offset above
> > 1MB of the start of the FV");
> > return EFI_ABORTED;
> > }
> >
> > - // Add opcode for an unconditional branch with no link. i.e.: " B
> > SecEntryPoint"
> > - ResetVector[0] |= ARMT_UNCONDITIONAL_JUMP_INSTRUCTION;
> > + if (SecCoreEntryAddress & 1 != 0) {
Sorry, I missed this one.
This needs extra parantheses.
I'll sent a v3. My apologies...
etienne
> > + ResetVector[0] = ARM_JUMP_TO_THUMB(EntryOffset);
> > + } else {
> > + ResetVector[0] = ARM_JUMP_TO_ARM(EntryOffset);
> > + }
> >
> > // SWI handler movs pc,lr. Just in case a debugger uses SWI
> > - ResetVector[2] = 0xE1B0F07E;
> > + ResetVector[2] = ARM_RETURN_FROM_EXCEPTION;
> >
> > // Place holder to support a common interrupt handler from ROM.
> > // Currently not supported. For this to be used the reset vector
> would
> > not be in this FV
> > --
> > 2.17.1
>
>
>
^ permalink raw reply [flat|nested] 10+ messages in thread* 回复: [edk2-devel] [PATCH v2 3/5] GenFv: Arm: support images entered in Thumb mode
2021-05-17 7:35 ` Etienne Carriere
@ 2021-05-17 7:47 ` gaoliming
2021-05-17 8:00 ` Etienne Carriere
0 siblings, 1 reply; 10+ messages in thread
From: gaoliming @ 2021-05-17 7:47 UTC (permalink / raw)
To: devel, etienne.carriere
Cc: 'Achin Gupta', 'Ard Biesheuvel',
'Jiewen Yao', 'Leif Lindholm',
'Sami Mujawar', 'Sughosh Ganu',
'Bob Feng'
Etienne:
Thanks for your reminder. I try VS compiler and meet with the compiler error on this line.
Here, does if ((SecCoreEntryAddress & 1) != 0) mean the lowest bit of this address is 1?
Thanks
Liming
> -----邮件原件-----
> 发件人: devel@edk2.groups.io <devel@edk2.groups.io> 代表 Etienne
> Carriere
> 发送时间: 2021年5月17日 15:35
> 收件人: gaoliming <gaoliming@byosoft.com.cn>
> 抄送: devel@edk2.groups.io; Achin Gupta <achin.gupta@arm.com>; Ard
> Biesheuvel <ardb+tianocore@kernel.org>; Jiewen Yao
> <jiewen.yao@intel.com>; Leif Lindholm <leif@nuviainc.com>; Sami Mujawar
> <sami.mujawar@arm.com>; Sughosh Ganu <sughosh.ganu@linaro.org>; Bob
> Feng <bob.c.feng@intel.com>
> 主题: Re: [edk2-devel] [PATCH v2 3/5] GenFv: Arm: support images entered in
> Thumb mode
>
> On Mon, 17 May 2021 at 09:24, gaoliming <gaoliming@byosoft.com.cn>
> wrote:
> >
> > Acked-by: Liming Gao <gaoliming@byosoft.com.cn>
> >
> > > -----邮件原件-----
> > > 发件人: Etienne Carriere <etienne.carriere@linaro.org>
> > > 发送时间: 2021年5月17日 13:49
> > > 收件人: devel@edk2.groups.io
> > > 抄送: Achin Gupta <achin.gupta@arm.com>; Ard Biesheuvel
> > > <ardb+tianocore@kernel.org>; Jiewen Yao <jiewen.yao@intel.com>; Leif
> > > Lindholm <leif@nuviainc.com>; Sami Mujawar
> <sami.mujawar@arm.com>;
> > > Sughosh Ganu <sughosh.ganu@linaro.org>; Etienne Carriere
> > > <etienne.carriere@linaro.org>; Bob Feng <bob.c.feng@intel.com>; Liming
> > > Gao <gaoliming@byosoft.com.cn>
> > > 主题: [PATCH v2 3/5] GenFv: Arm: support images entered in Thumb
> mode
> > >
> > > Change GenFv for Arm architecture to generate a specific jump
> > > instruction as image entry instruction, when the target entry label
> > > is assembled with Thumb instruction set. This is possible since
> > > SecCoreEntryAddress value fetched from the PE32 has its LSBit set when
> > > the entry instruction executes in Thumb mode.
> > >
> > > Cc: Bob Feng <bob.c.feng@intel.com>
> > > Cc: Liming Gao <gaoliming@byosoft.com.cn>
> > > Cc: Achin Gupta <achin.gupta@arm.com>
> > > Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
> > > Cc: Leif Lindholm <leif@nuviainc.com>
> > > Cc: Sughosh Ganu <sughosh.ganu@linaro.org>
> > > Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
> > > ---
> > > Changes since v1:
> > > - Fix typos in commit log and inline comments
> > > - Change if() test operand to be an explicit boolean
> > > ---
> > > BaseTools/Source/C/GenFv/GenFvInternalLib.c | 38
> +++++++++++++++-----
> > > 1 file changed, 29 insertions(+), 9 deletions(-)
> > >
> > > diff --git a/BaseTools/Source/C/GenFv/GenFvInternalLib.c
> > > b/BaseTools/Source/C/GenFv/GenFvInternalLib.c
> > > index 6e296b8ad6..5f3fd4f808 100644
> > > --- a/BaseTools/Source/C/GenFv/GenFvInternalLib.c
> > > +++ b/BaseTools/Source/C/GenFv/GenFvInternalLib.c
> > > @@ -34,9 +34,27 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
> > > #include "FvLib.h"
> > > #include "PeCoffLib.h"
> > >
> > > -#define ARMT_UNCONDITIONAL_JUMP_INSTRUCTION
> > > 0xEB000000
> > > #define ARM64_UNCONDITIONAL_JUMP_INSTRUCTION
> > > 0x14000000
> > >
> > > +/*
> > > + * Arm instruction to jump to Fv entry instruction in Arm or Thumb mode.
> > > + * From ARM Arch Ref Manual versions b/c/d, section A8.8.25 BL, BLX
> > > (immediate)
> > > + * BLX (encoding A2) branches to offset in Thumb instruction set mode.
> > > + * BL (encoding A1) branches to offset in Arm instruction set mode.
> > > + */
> > > +#define ARM_JUMP_OFFSET_MAX 0xffffff
> > > +#define ARM_JUMP_TO_ARM(Offset) (0xeb000000 | ((Offset - 8) >>
> 2))
> > > +
> > > +#define _ARM_JUMP_TO_THUMB(Imm32) (0xfa000000 | \
> > > + (((Imm32) & (1 << 1)) << (24
> - 1))
> > > | \
> > > + (((Imm32) >> 2) & 0x7fffff))
> > > +#define ARM_JUMP_TO_THUMB(Offset)
> > > _ARM_JUMP_TO_THUMB((Offset) - 8)
> > > +
> > > +/*
> > > + * Arm instruction to retrun from exception (MOVS PC, LR)
> > > + */
> > > +#define ARM_RETURN_FROM_EXCEPTION 0xE1B0F07E
> > > +
> > > BOOLEAN mArm = FALSE;
> > > BOOLEAN mRiscV = FALSE;
> > > STATIC UINT32 MaxFfsAlignment = 0;
> > > @@ -2203,23 +2221,25 @@ Returns:
> > > // if we found an SEC core entry point then generate a branch
> > > instruction
> > > // to it and populate a debugger SWI entry as well
> > > if (UpdateVectorSec) {
> > > + UINT32 EntryOffset;
> > >
> > > VerboseMsg("UpdateArmResetVectorIfNeeded updating ARM
> SEC
> > > vector");
> > >
> > > - // B SecEntryPoint - signed_immed_24 part +/-32MB offset
> > > - // on ARM, the PC is always 8 ahead, so we're not really jumping
> > from
> > > the base address, but from base address + 8
> > > - ResetVector[0] = (INT32)(SecCoreEntryAddress -
> > > FvInfo->BaseAddress - 8) >> 2;
> > > + EntryOffset = (INT32)(SecCoreEntryAddress -
> FvInfo->BaseAddress);
> > >
> > > - if (ResetVector[0] > 0x00FFFFFF) {
> > > - Error(NULL, 0, 3000, "Invalid", "SEC Entry point must be within
> > > 32MB of the start of the FV");
> > > + if (EntryOffset > ARM_JUMP_OFFSET_MAX) {
> > > + Error(NULL, 0, 3000, "Invalid", "SEC Entry point offset above
> > > 1MB of the start of the FV");
> > > return EFI_ABORTED;
> > > }
> > >
> > > - // Add opcode for an unconditional branch with no link. i.e.: " B
> > > SecEntryPoint"
> > > - ResetVector[0] |=
> ARMT_UNCONDITIONAL_JUMP_INSTRUCTION;
> > > + if (SecCoreEntryAddress & 1 != 0) {
>
> Sorry, I missed this one.
> This needs extra parantheses.
>
> I'll sent a v3. My apologies...
>
> etienne
>
> > > + ResetVector[0] = ARM_JUMP_TO_THUMB(EntryOffset);
> > > + } else {
> > > + ResetVector[0] = ARM_JUMP_TO_ARM(EntryOffset);
> > > + }
> > >
> > > // SWI handler movs pc,lr. Just in case a debugger uses SWI
> > > - ResetVector[2] = 0xE1B0F07E;
> > > + ResetVector[2] = ARM_RETURN_FROM_EXCEPTION;
> > >
> > > // Place holder to support a common interrupt handler from
> ROM.
> > > // Currently not supported. For this to be used the reset vector
> > would
> > > not be in this FV
> > > --
> > > 2.17.1
> >
> >
> >
>
>
>
>
^ permalink raw reply [flat|nested] 10+ messages in thread* Re: [edk2-devel] [PATCH v2 3/5] GenFv: Arm: support images entered in Thumb mode
2021-05-17 7:47 ` 回复: [edk2-devel] " gaoliming
@ 2021-05-17 8:00 ` Etienne Carriere
0 siblings, 0 replies; 10+ messages in thread
From: Etienne Carriere @ 2021-05-17 8:00 UTC (permalink / raw)
To: gaoliming
Cc: devel, Achin Gupta, Ard Biesheuvel, Jiewen Yao, Leif Lindholm,
Sami Mujawar, Sughosh Ganu, Bob Feng
On Mon, 17 May 2021 at 09:48, gaoliming <gaoliming@byosoft.com.cn> wrote:
>
> Etienne:
> Thanks for your reminder. I try VS compiler and meet with the compiler error on this line.
>
> Here, does if ((SecCoreEntryAddress & 1) != 0) mean the lowest bit of this address is 1?
Yes it does.
>
> Thanks
> Liming
> > -----邮件原件-----
> > 发件人: devel@edk2.groups.io <devel@edk2.groups.io> 代表 Etienne
> > Carriere
> > 发送时间: 2021年5月17日 15:35
> > 收件人: gaoliming <gaoliming@byosoft.com.cn>
> > 抄送: devel@edk2.groups.io; Achin Gupta <achin.gupta@arm.com>; Ard
> > Biesheuvel <ardb+tianocore@kernel.org>; Jiewen Yao
> > <jiewen.yao@intel.com>; Leif Lindholm <leif@nuviainc.com>; Sami Mujawar
> > <sami.mujawar@arm.com>; Sughosh Ganu <sughosh.ganu@linaro.org>; Bob
> > Feng <bob.c.feng@intel.com>
> > 主题: Re: [edk2-devel] [PATCH v2 3/5] GenFv: Arm: support images entered in
> > Thumb mode
> >
> > On Mon, 17 May 2021 at 09:24, gaoliming <gaoliming@byosoft.com.cn>
> > wrote:
> > >
> > > Acked-by: Liming Gao <gaoliming@byosoft.com.cn>
> > >
> > > > -----邮件原件-----
> > > > 发件人: Etienne Carriere <etienne.carriere@linaro.org>
> > > > 发送时间: 2021年5月17日 13:49
> > > > 收件人: devel@edk2.groups.io
> > > > 抄送: Achin Gupta <achin.gupta@arm.com>; Ard Biesheuvel
> > > > <ardb+tianocore@kernel.org>; Jiewen Yao <jiewen.yao@intel.com>; Leif
> > > > Lindholm <leif@nuviainc.com>; Sami Mujawar
> > <sami.mujawar@arm.com>;
> > > > Sughosh Ganu <sughosh.ganu@linaro.org>; Etienne Carriere
> > > > <etienne.carriere@linaro.org>; Bob Feng <bob.c.feng@intel.com>; Liming
> > > > Gao <gaoliming@byosoft.com.cn>
> > > > 主题: [PATCH v2 3/5] GenFv: Arm: support images entered in Thumb
> > mode
> > > >
> > > > Change GenFv for Arm architecture to generate a specific jump
> > > > instruction as image entry instruction, when the target entry label
> > > > is assembled with Thumb instruction set. This is possible since
> > > > SecCoreEntryAddress value fetched from the PE32 has its LSBit set when
> > > > the entry instruction executes in Thumb mode.
> > > >
> > > > Cc: Bob Feng <bob.c.feng@intel.com>
> > > > Cc: Liming Gao <gaoliming@byosoft.com.cn>
> > > > Cc: Achin Gupta <achin.gupta@arm.com>
> > > > Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
> > > > Cc: Leif Lindholm <leif@nuviainc.com>
> > > > Cc: Sughosh Ganu <sughosh.ganu@linaro.org>
> > > > Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
> > > > ---
> > > > Changes since v1:
> > > > - Fix typos in commit log and inline comments
> > > > - Change if() test operand to be an explicit boolean
> > > > ---
> > > > BaseTools/Source/C/GenFv/GenFvInternalLib.c | 38
> > +++++++++++++++-----
> > > > 1 file changed, 29 insertions(+), 9 deletions(-)
> > > >
> > > > diff --git a/BaseTools/Source/C/GenFv/GenFvInternalLib.c
> > > > b/BaseTools/Source/C/GenFv/GenFvInternalLib.c
> > > > index 6e296b8ad6..5f3fd4f808 100644
> > > > --- a/BaseTools/Source/C/GenFv/GenFvInternalLib.c
> > > > +++ b/BaseTools/Source/C/GenFv/GenFvInternalLib.c
> > > > @@ -34,9 +34,27 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
> > > > #include "FvLib.h"
> > > > #include "PeCoffLib.h"
> > > >
> > > > -#define ARMT_UNCONDITIONAL_JUMP_INSTRUCTION
> > > > 0xEB000000
> > > > #define ARM64_UNCONDITIONAL_JUMP_INSTRUCTION
> > > > 0x14000000
> > > >
> > > > +/*
> > > > + * Arm instruction to jump to Fv entry instruction in Arm or Thumb mode.
> > > > + * From ARM Arch Ref Manual versions b/c/d, section A8.8.25 BL, BLX
> > > > (immediate)
> > > > + * BLX (encoding A2) branches to offset in Thumb instruction set mode.
> > > > + * BL (encoding A1) branches to offset in Arm instruction set mode.
> > > > + */
> > > > +#define ARM_JUMP_OFFSET_MAX 0xffffff
> > > > +#define ARM_JUMP_TO_ARM(Offset) (0xeb000000 | ((Offset - 8) >>
> > 2))
> > > > +
> > > > +#define _ARM_JUMP_TO_THUMB(Imm32) (0xfa000000 | \
> > > > + (((Imm32) & (1 << 1)) << (24
> > - 1))
> > > > | \
> > > > + (((Imm32) >> 2) & 0x7fffff))
> > > > +#define ARM_JUMP_TO_THUMB(Offset)
> > > > _ARM_JUMP_TO_THUMB((Offset) - 8)
> > > > +
> > > > +/*
> > > > + * Arm instruction to retrun from exception (MOVS PC, LR)
> > > > + */
> > > > +#define ARM_RETURN_FROM_EXCEPTION 0xE1B0F07E
> > > > +
> > > > BOOLEAN mArm = FALSE;
> > > > BOOLEAN mRiscV = FALSE;
> > > > STATIC UINT32 MaxFfsAlignment = 0;
> > > > @@ -2203,23 +2221,25 @@ Returns:
> > > > // if we found an SEC core entry point then generate a branch
> > > > instruction
> > > > // to it and populate a debugger SWI entry as well
> > > > if (UpdateVectorSec) {
> > > > + UINT32 EntryOffset;
> > > >
> > > > VerboseMsg("UpdateArmResetVectorIfNeeded updating ARM
> > SEC
> > > > vector");
> > > >
> > > > - // B SecEntryPoint - signed_immed_24 part +/-32MB offset
> > > > - // on ARM, the PC is always 8 ahead, so we're not really jumping
> > > from
> > > > the base address, but from base address + 8
> > > > - ResetVector[0] = (INT32)(SecCoreEntryAddress -
> > > > FvInfo->BaseAddress - 8) >> 2;
> > > > + EntryOffset = (INT32)(SecCoreEntryAddress -
> > FvInfo->BaseAddress);
> > > >
> > > > - if (ResetVector[0] > 0x00FFFFFF) {
> > > > - Error(NULL, 0, 3000, "Invalid", "SEC Entry point must be within
> > > > 32MB of the start of the FV");
> > > > + if (EntryOffset > ARM_JUMP_OFFSET_MAX) {
> > > > + Error(NULL, 0, 3000, "Invalid", "SEC Entry point offset above
> > > > 1MB of the start of the FV");
> > > > return EFI_ABORTED;
> > > > }
> > > >
> > > > - // Add opcode for an unconditional branch with no link. i.e.: " B
> > > > SecEntryPoint"
> > > > - ResetVector[0] |=
> > ARMT_UNCONDITIONAL_JUMP_INSTRUCTION;
> > > > + if (SecCoreEntryAddress & 1 != 0) {
> >
> > Sorry, I missed this one.
> > This needs extra parantheses.
> >
> > I'll sent a v3. My apologies...
> >
> > etienne
> >
> > > > + ResetVector[0] = ARM_JUMP_TO_THUMB(EntryOffset);
> > > > + } else {
> > > > + ResetVector[0] = ARM_JUMP_TO_ARM(EntryOffset);
> > > > + }
> > > >
> > > > // SWI handler movs pc,lr. Just in case a debugger uses SWI
> > > > - ResetVector[2] = 0xE1B0F07E;
> > > > + ResetVector[2] = ARM_RETURN_FROM_EXCEPTION;
> > > >
> > > > // Place holder to support a common interrupt handler from
> > ROM.
> > > > // Currently not supported. For this to be used the reset vector
> > > would
> > > > not be in this FV
> > > > --
> > > > 2.17.1
> > >
> > >
> > >
> >
> >
> >
> >
>
>
>
^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH v2 4/5] StandaloneMmPkg: fix pointer/int casts against 32bit architectures
2021-05-17 5:49 [PATCH v2 1/5] ArmPkg/IndustryStandard: 32b/64b agnostic FF-A, Mm SVC and Std SMC IDs Etienne Carriere
2021-05-17 5:49 ` [PATCH v2 2/5] ArmPkg: prepare 32bit ARM build of StandaloneMmPkg Etienne Carriere
2021-05-17 5:49 ` [PATCH v2 3/5] GenFv: Arm: support images entered in Thumb mode Etienne Carriere
@ 2021-05-17 5:49 ` Etienne Carriere
2021-05-17 5:49 ` [PATCH v2 5/5] StandaloneMmPkg: build for 32bit arm machines Etienne Carriere
3 siblings, 0 replies; 10+ messages in thread
From: Etienne Carriere @ 2021-05-17 5:49 UTC (permalink / raw)
To: devel
Cc: Achin Gupta, Ard Biesheuvel, Jiewen Yao, Leif Lindholm,
Sami Mujawar, Sughosh Ganu, Etienne Carriere
Use intermediate (UINTN) cast when casting int from/to pointer. This
is needed as UINT64 values cast from/to 32bit pointer for 32bit
architectures.
Cc: Achin Gupta <achin.gupta@arm.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Sami Mujawar <sami.mujawar@arm.com>
Cc: Sughosh Ganu <sughosh.ganu@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
---
No change since v1
---
StandaloneMmPkg/Drivers/StandaloneMmCpu/AArch64/StandaloneMmCpu.c | 8 ++++----
StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/AArch64/CreateHobList.c | 14 +++++++-------
StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/AArch64/StandaloneMmCoreEntryPoint.c | 2 +-
3 files changed, 12 insertions(+), 12 deletions(-)
diff --git a/StandaloneMmPkg/Drivers/StandaloneMmCpu/AArch64/StandaloneMmCpu.c b/StandaloneMmPkg/Drivers/StandaloneMmCpu/AArch64/StandaloneMmCpu.c
index 6884095c49..d4590bcd19 100644
--- a/StandaloneMmPkg/Drivers/StandaloneMmCpu/AArch64/StandaloneMmCpu.c
+++ b/StandaloneMmPkg/Drivers/StandaloneMmCpu/AArch64/StandaloneMmCpu.c
@@ -164,8 +164,8 @@ StandaloneMmCpuInitialize (
// Share the entry point of the CPU driver
DEBUG ((DEBUG_INFO, "Sharing Cpu Driver EP *0x%lx = 0x%lx\n",
- (UINT64) CpuDriverEntryPointDesc->ArmTfCpuDriverEpPtr,
- (UINT64) PiMmStandaloneArmTfCpuDriverEntry));
+ (UINTN) CpuDriverEntryPointDesc->ArmTfCpuDriverEpPtr,
+ (UINTN) PiMmStandaloneArmTfCpuDriverEntry));
*(CpuDriverEntryPointDesc->ArmTfCpuDriverEpPtr) = PiMmStandaloneArmTfCpuDriverEntry;
// Find the descriptor that contains the whereabouts of the buffer for
@@ -180,8 +180,8 @@ StandaloneMmCpuInitialize (
return Status;
}
- DEBUG ((DEBUG_INFO, "mNsCommBuffer.PhysicalStart - 0x%lx\n", (UINT64) NsCommBufMmramRange->PhysicalStart));
- DEBUG ((DEBUG_INFO, "mNsCommBuffer.PhysicalSize - 0x%lx\n", (UINT64) NsCommBufMmramRange->PhysicalSize));
+ DEBUG ((DEBUG_INFO, "mNsCommBuffer.PhysicalStart - 0x%lx\n", (UINTN) NsCommBufMmramRange->PhysicalStart));
+ DEBUG ((DEBUG_INFO, "mNsCommBuffer.PhysicalSize - 0x%lx\n", (UINTN) NsCommBufMmramRange->PhysicalSize));
CopyMem (&mNsCommBuffer, NsCommBufMmramRange, sizeof(EFI_MMRAM_DESCRIPTOR));
DEBUG ((DEBUG_INFO, "mNsCommBuffer: 0x%016lx - 0x%lx\n", mNsCommBuffer.CpuStart, mNsCommBuffer.PhysicalSize));
diff --git a/StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/AArch64/CreateHobList.c b/StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/AArch64/CreateHobList.c
index e8fb96bd6e..4d4cf3d5ff 100644
--- a/StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/AArch64/CreateHobList.c
+++ b/StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/AArch64/CreateHobList.c
@@ -72,14 +72,14 @@ CreateHobListFromBootInfo (
// Create a hoblist with a PHIT and EOH
HobStart = HobConstructor (
- (VOID *) PayloadBootInfo->SpMemBase,
+ (VOID *) (UINTN) PayloadBootInfo->SpMemBase,
(UINTN) PayloadBootInfo->SpMemLimit - PayloadBootInfo->SpMemBase,
- (VOID *) PayloadBootInfo->SpHeapBase,
- (VOID *) (PayloadBootInfo->SpHeapBase + PayloadBootInfo->SpHeapSize)
+ (VOID *) (UINTN) PayloadBootInfo->SpHeapBase,
+ (VOID *) (UINTN) (PayloadBootInfo->SpHeapBase + PayloadBootInfo->SpHeapSize)
);
// Check that the Hoblist starts at the bottom of the Heap
- ASSERT (HobStart == (VOID *) PayloadBootInfo->SpHeapBase);
+ ASSERT (HobStart == (VOID *) (UINTN) PayloadBootInfo->SpHeapBase);
// Build a Boot Firmware Volume HOB
BuildFvHob (PayloadBootInfo->SpImageBase, PayloadBootInfo->SpImageSize);
@@ -190,9 +190,9 @@ CreateHobListFromBootInfo (
MmramRanges[3].RegionState = EFI_CACHEABLE | EFI_ALLOCATED;
// Base and size of heap memory shared by all cpus
- MmramRanges[4].PhysicalStart = (EFI_PHYSICAL_ADDRESS) HobStart;
- MmramRanges[4].CpuStart = (EFI_PHYSICAL_ADDRESS) HobStart;
- MmramRanges[4].PhysicalSize = HobStart->EfiFreeMemoryBottom - (EFI_PHYSICAL_ADDRESS) HobStart;
+ MmramRanges[4].PhysicalStart = (EFI_PHYSICAL_ADDRESS) (UINTN) HobStart;
+ MmramRanges[4].CpuStart = (EFI_PHYSICAL_ADDRESS) (UINTN) HobStart;
+ MmramRanges[4].PhysicalSize = HobStart->EfiFreeMemoryBottom - (EFI_PHYSICAL_ADDRESS) (UINTN) HobStart;
MmramRanges[4].RegionState = EFI_CACHEABLE | EFI_ALLOCATED;
// Base and size of heap memory shared by all cpus
diff --git a/StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/AArch64/StandaloneMmCoreEntryPoint.c b/StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/AArch64/StandaloneMmCoreEntryPoint.c
index 6c50f470aa..b445d6942e 100644
--- a/StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/AArch64/StandaloneMmCoreEntryPoint.c
+++ b/StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/AArch64/StandaloneMmCoreEntryPoint.c
@@ -328,7 +328,7 @@ _ModuleEntryPoint (
// Locate PE/COFF File information for the Standalone MM core module
Status = LocateStandaloneMmCorePeCoffData (
- (EFI_FIRMWARE_VOLUME_HEADER *) PayloadBootInfo->SpImageBase,
+ (EFI_FIRMWARE_VOLUME_HEADER *) (UINTN) PayloadBootInfo->SpImageBase,
&TeData,
&TeDataSize
);
--
2.17.1
^ permalink raw reply related [flat|nested] 10+ messages in thread* [PATCH v2 5/5] StandaloneMmPkg: build for 32bit arm machines
2021-05-17 5:49 [PATCH v2 1/5] ArmPkg/IndustryStandard: 32b/64b agnostic FF-A, Mm SVC and Std SMC IDs Etienne Carriere
` (2 preceding siblings ...)
2021-05-17 5:49 ` [PATCH v2 4/5] StandaloneMmPkg: fix pointer/int casts against 32bit architectures Etienne Carriere
@ 2021-05-17 5:49 ` Etienne Carriere
2021-05-17 6:23 ` Etienne Carriere
3 siblings, 1 reply; 10+ messages in thread
From: Etienne Carriere @ 2021-05-17 5:49 UTC (permalink / raw)
To: devel
Cc: Achin Gupta, Ard Biesheuvel, Jiewen Yao, Leif Lindholm,
Sami Mujawar, Sughosh Ganu, Etienne Carriere
This change allows to build StandaloneMmPkg components for 32bit Arm
StandaloneMm firmware.
This change mainly moves AArch64/ source files to Arm/ side directory
for several components: StandaloneMmCpu, StandaloneMmCoreEntryPoint
and StandaloneMmMemLib. The source file is built for both 32b and 64b
Arm targets.
Cc: Achin Gupta <achin.gupta@arm.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Sami Mujawar <sami.mujawar@arm.com>
Cc: Sughosh Ganu <sughosh.ganu@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
---
Changes since v1:
- ARM_SMC_ID_MM_COMMUNICATE 32b/64b agnostic helper ID is defined
in ArmStdSmc.h (see 1st commit in this series) instead of being
local to EventHandle.c.
- Fix void occurrence to VOID.
- Fix path in StandaloneMmPkg/StandaloneMmPkg.dsc
---
StandaloneMmPkg/Core/StandaloneMmCore.inf | 2 +-
StandaloneMmPkg/Drivers/StandaloneMmCpu/{AArch64 => }/EventHandle.c | 5 +++--
StandaloneMmPkg/Drivers/StandaloneMmCpu/{AArch64 => }/StandaloneMmCpu.c | 2 +-
StandaloneMmPkg/Drivers/StandaloneMmCpu/{AArch64 => }/StandaloneMmCpu.h | 0
StandaloneMmPkg/Drivers/StandaloneMmCpu/{AArch64 => }/StandaloneMmCpu.inf | 0
StandaloneMmPkg/Include/Library/{AArch64 => Arm}/StandaloneMmCoreEntryPoint.h | 0
StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/{AArch64 => Arm}/CreateHobList.c | 2 +-
StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/{AArch64 => Arm}/SetPermissions.c | 2 +-
StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/{AArch64 => Arm}/StandaloneMmCoreEntryPoint.c | 16 ++++++++--------
StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/StandaloneMmCoreEntryPoint.inf | 14 +++++++-------
StandaloneMmPkg/Library/StandaloneMmCoreHobLib/{AArch64 => Arm}/StandaloneMmCoreHobLib.c | 0
StandaloneMmPkg/Library/StandaloneMmCoreHobLib/{AArch64 => Arm}/StandaloneMmCoreHobLibInternal.c | 0
StandaloneMmPkg/Library/StandaloneMmCoreHobLib/StandaloneMmCoreHobLib.inf | 8 ++++----
StandaloneMmPkg/Library/StandaloneMmMemLib/{AArch64/StandaloneMmMemLibInternal.c => ArmStandaloneMmMemLibInternal.c} | 9 ++++++++-
StandaloneMmPkg/Library/StandaloneMmMemLib/StandaloneMmMemLib.inf | 6 +++---
StandaloneMmPkg/Library/VariableMmDependency/VariableMmDependency.inf | 2 +-
StandaloneMmPkg/StandaloneMmPkg.dsc | 10 +++++-----
17 files changed, 43 insertions(+), 35 deletions(-)
diff --git a/StandaloneMmPkg/Core/StandaloneMmCore.inf b/StandaloneMmPkg/Core/StandaloneMmCore.inf
index 87bf6e9440..56042b7b39 100644
--- a/StandaloneMmPkg/Core/StandaloneMmCore.inf
+++ b/StandaloneMmPkg/Core/StandaloneMmCore.inf
@@ -17,7 +17,7 @@
PI_SPECIFICATION_VERSION = 0x00010032
ENTRY_POINT = StandaloneMmMain
-# VALID_ARCHITECTURES = IA32 X64 AARCH64
+# VALID_ARCHITECTURES = IA32 X64 AARCH64 ARM
[Sources]
StandaloneMmCore.c
diff --git a/StandaloneMmPkg/Drivers/StandaloneMmCpu/AArch64/EventHandle.c b/StandaloneMmPkg/Drivers/StandaloneMmCpu/EventHandle.c
similarity index 95%
rename from StandaloneMmPkg/Drivers/StandaloneMmCpu/AArch64/EventHandle.c
rename to StandaloneMmPkg/Drivers/StandaloneMmCpu/EventHandle.c
index 63fbe26642..165d696f99 100644
--- a/StandaloneMmPkg/Drivers/StandaloneMmCpu/AArch64/EventHandle.c
+++ b/StandaloneMmPkg/Drivers/StandaloneMmCpu/EventHandle.c
@@ -2,6 +2,7 @@
Copyright (c) 2016 HP Development Company, L.P.
Copyright (c) 2016 - 2021, Arm Limited. All rights reserved.
+ Copyright (c) 2021, Linaro Limited
SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -92,8 +93,8 @@ PiMmStandaloneArmTfCpuDriverEntry (
// receipt of a synchronous MM request. Use the Event ID to distinguish
// between synchronous and asynchronous events.
//
- if ((ARM_SMC_ID_MM_COMMUNICATE_AARCH64 != EventId) &&
- (ARM_SVC_ID_FFA_MSG_SEND_DIRECT_REQ_AARCH64 != EventId)) {
+ if ((ARM_SMC_ID_MM_COMMUNICATE != EventId) &&
+ (ARM_SVC_ID_FFA_MSG_SEND_DIRECT_REQ != EventId)) {
DEBUG ((DEBUG_INFO, "UnRecognized Event - 0x%x\n", EventId));
return EFI_INVALID_PARAMETER;
}
diff --git a/StandaloneMmPkg/Drivers/StandaloneMmCpu/AArch64/StandaloneMmCpu.c b/StandaloneMmPkg/Drivers/StandaloneMmCpu/StandaloneMmCpu.c
similarity index 96%
rename from StandaloneMmPkg/Drivers/StandaloneMmCpu/AArch64/StandaloneMmCpu.c
rename to StandaloneMmPkg/Drivers/StandaloneMmCpu/StandaloneMmCpu.c
index d4590bcd19..10097f792f 100644
--- a/StandaloneMmPkg/Drivers/StandaloneMmCpu/AArch64/StandaloneMmCpu.c
+++ b/StandaloneMmPkg/Drivers/StandaloneMmCpu/StandaloneMmCpu.c
@@ -10,7 +10,7 @@
#include <Base.h>
#include <Pi/PiMmCis.h>
-#include <Library/AArch64/StandaloneMmCoreEntryPoint.h>
+#include <Library/Arm/StandaloneMmCoreEntryPoint.h>
#include <Library/DebugLib.h>
#include <Library/ArmSvcLib.h>
#include <Library/ArmLib.h>
diff --git a/StandaloneMmPkg/Drivers/StandaloneMmCpu/AArch64/StandaloneMmCpu.h b/StandaloneMmPkg/Drivers/StandaloneMmCpu/StandaloneMmCpu.h
similarity index 100%
rename from StandaloneMmPkg/Drivers/StandaloneMmCpu/AArch64/StandaloneMmCpu.h
rename to StandaloneMmPkg/Drivers/StandaloneMmCpu/StandaloneMmCpu.h
diff --git a/StandaloneMmPkg/Drivers/StandaloneMmCpu/AArch64/StandaloneMmCpu.inf b/StandaloneMmPkg/Drivers/StandaloneMmCpu/StandaloneMmCpu.inf
similarity index 100%
rename from StandaloneMmPkg/Drivers/StandaloneMmCpu/AArch64/StandaloneMmCpu.inf
rename to StandaloneMmPkg/Drivers/StandaloneMmCpu/StandaloneMmCpu.inf
diff --git a/StandaloneMmPkg/Include/Library/AArch64/StandaloneMmCoreEntryPoint.h b/StandaloneMmPkg/Include/Library/Arm/StandaloneMmCoreEntryPoint.h
similarity index 100%
rename from StandaloneMmPkg/Include/Library/AArch64/StandaloneMmCoreEntryPoint.h
rename to StandaloneMmPkg/Include/Library/Arm/StandaloneMmCoreEntryPoint.h
diff --git a/StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/AArch64/CreateHobList.c b/StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/Arm/CreateHobList.c
similarity index 97%
rename from StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/AArch64/CreateHobList.c
rename to StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/Arm/CreateHobList.c
index 4d4cf3d5ff..85f8194687 100644
--- a/StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/AArch64/CreateHobList.c
+++ b/StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/Arm/CreateHobList.c
@@ -14,7 +14,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#include <Guid/MmramMemoryReserve.h>
#include <Guid/MpInformation.h>
-#include <Library/AArch64/StandaloneMmCoreEntryPoint.h>
+#include <Library/Arm/StandaloneMmCoreEntryPoint.h>
#include <Library/ArmMmuLib.h>
#include <Library/ArmSvcLib.h>
#include <Library/DebugLib.h>
diff --git a/StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/AArch64/SetPermissions.c b/StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/Arm/SetPermissions.c
similarity index 96%
rename from StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/AArch64/SetPermissions.c
rename to StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/Arm/SetPermissions.c
index 4a380df4a6..cd4b90823e 100644
--- a/StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/AArch64/SetPermissions.c
+++ b/StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/Arm/SetPermissions.c
@@ -14,7 +14,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#include <Guid/MmramMemoryReserve.h>
#include <Guid/MpInformation.h>
-#include <Library/AArch64/StandaloneMmCoreEntryPoint.h>
+#include <Library/Arm/StandaloneMmCoreEntryPoint.h>
#include <Library/ArmMmuLib.h>
#include <Library/ArmSvcLib.h>
#include <Library/DebugLib.h>
diff --git a/StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/AArch64/StandaloneMmCoreEntryPoint.c b/StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/Arm/StandaloneMmCoreEntryPoint.c
similarity index 94%
rename from StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/AArch64/StandaloneMmCoreEntryPoint.c
rename to StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/Arm/StandaloneMmCoreEntryPoint.c
index b445d6942e..49cf51a789 100644
--- a/StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/AArch64/StandaloneMmCoreEntryPoint.c
+++ b/StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/Arm/StandaloneMmCoreEntryPoint.c
@@ -10,7 +10,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#include <PiMm.h>
-#include <Library/AArch64/StandaloneMmCoreEntryPoint.h>
+#include <Library/Arm/StandaloneMmCoreEntryPoint.h>
#include <PiPei.h>
#include <Guid/MmramMemoryReserve.h>
@@ -182,13 +182,13 @@ DelegatedEventLoop (
}
if (FfaEnabled) {
- EventCompleteSvcArgs->Arg0 = ARM_SVC_ID_FFA_MSG_SEND_DIRECT_RESP_AARCH64;
+ EventCompleteSvcArgs->Arg0 = ARM_SVC_ID_FFA_MSG_SEND_DIRECT_RESP;
EventCompleteSvcArgs->Arg1 = 0;
EventCompleteSvcArgs->Arg2 = 0;
- EventCompleteSvcArgs->Arg3 = ARM_SVC_ID_SP_EVENT_COMPLETE_AARCH64;
+ EventCompleteSvcArgs->Arg3 = ARM_SVC_ID_SP_EVENT_COMPLETE;
EventCompleteSvcArgs->Arg4 = SvcStatus;
} else {
- EventCompleteSvcArgs->Arg0 = ARM_SVC_ID_SP_EVENT_COMPLETE_AARCH64;
+ EventCompleteSvcArgs->Arg0 = ARM_SVC_ID_SP_EVENT_COMPLETE;
EventCompleteSvcArgs->Arg1 = SvcStatus;
}
}
@@ -273,13 +273,13 @@ InitArmSvcArgs (
)
{
if (FeaturePcdGet (PcdFfaEnable)) {
- InitMmFoundationSvcArgs->Arg0 = ARM_SVC_ID_FFA_MSG_SEND_DIRECT_RESP_AARCH64;
+ InitMmFoundationSvcArgs->Arg0 = ARM_SVC_ID_FFA_MSG_SEND_DIRECT_RESP;
InitMmFoundationSvcArgs->Arg1 = 0;
InitMmFoundationSvcArgs->Arg2 = 0;
- InitMmFoundationSvcArgs->Arg3 = ARM_SVC_ID_SP_EVENT_COMPLETE_AARCH64;
+ InitMmFoundationSvcArgs->Arg3 = ARM_SVC_ID_SP_EVENT_COMPLETE;
InitMmFoundationSvcArgs->Arg4 = *Ret;
} else {
- InitMmFoundationSvcArgs->Arg0 = ARM_SVC_ID_SP_EVENT_COMPLETE_AARCH64;
+ InitMmFoundationSvcArgs->Arg0 = ARM_SVC_ID_SP_EVENT_COMPLETE;
InitMmFoundationSvcArgs->Arg1 = *Ret;
}
}
@@ -395,7 +395,7 @@ _ModuleEntryPoint (
//
ProcessModuleEntryPointList (HobStart);
- DEBUG ((DEBUG_INFO, "Shared Cpu Driver EP 0x%lx\n", (UINT64) CpuDriverEntryPoint));
+ DEBUG ((DEBUG_INFO, "Shared Cpu Driver EP %p\n", (VOID *) CpuDriverEntryPoint));
finish:
if (Status == RETURN_UNSUPPORTED) {
diff --git a/StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/StandaloneMmCoreEntryPoint.inf b/StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/StandaloneMmCoreEntryPoint.inf
index 4fa426f58e..1762586cfa 100644
--- a/StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/StandaloneMmCoreEntryPoint.inf
+++ b/StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/StandaloneMmCoreEntryPoint.inf
@@ -21,10 +21,10 @@
# VALID_ARCHITECTURES = IA32 X64 IPF EBC (EBC is for build only)
#
-[Sources.AARCH64]
- AArch64/StandaloneMmCoreEntryPoint.c
- AArch64/SetPermissions.c
- AArch64/CreateHobList.c
+[Sources.AARCH64, Sources.ARM]
+ Arm/StandaloneMmCoreEntryPoint.c
+ Arm/SetPermissions.c
+ Arm/CreateHobList.c
[Sources.X64]
X64/StandaloneMmCoreEntryPoint.c
@@ -34,14 +34,14 @@
MdeModulePkg/MdeModulePkg.dec
StandaloneMmPkg/StandaloneMmPkg.dec
-[Packages.AARCH64]
+[Packages.ARM, Packages.AARCH64]
ArmPkg/ArmPkg.dec
[LibraryClasses]
BaseLib
DebugLib
-[LibraryClasses.AARCH64]
+[LibraryClasses.ARM, LibraryClasses.AARCH64]
StandaloneMmMmuLib
ArmSvcLib
@@ -51,7 +51,7 @@
gEfiStandaloneMmNonSecureBufferGuid
gEfiArmTfCpuDriverEpDescriptorGuid
-[FeaturePcd.AARCH64]
+[FeaturePcd.ARM, FeaturePcd.AARCH64]
gArmTokenSpaceGuid.PcdFfaEnable
[BuildOptions]
diff --git a/StandaloneMmPkg/Library/StandaloneMmCoreHobLib/AArch64/StandaloneMmCoreHobLib.c b/StandaloneMmPkg/Library/StandaloneMmCoreHobLib/Arm/StandaloneMmCoreHobLib.c
similarity index 100%
rename from StandaloneMmPkg/Library/StandaloneMmCoreHobLib/AArch64/StandaloneMmCoreHobLib.c
rename to StandaloneMmPkg/Library/StandaloneMmCoreHobLib/Arm/StandaloneMmCoreHobLib.c
diff --git a/StandaloneMmPkg/Library/StandaloneMmCoreHobLib/AArch64/StandaloneMmCoreHobLibInternal.c b/StandaloneMmPkg/Library/StandaloneMmCoreHobLib/Arm/StandaloneMmCoreHobLibInternal.c
similarity index 100%
rename from StandaloneMmPkg/Library/StandaloneMmCoreHobLib/AArch64/StandaloneMmCoreHobLibInternal.c
rename to StandaloneMmPkg/Library/StandaloneMmCoreHobLib/Arm/StandaloneMmCoreHobLibInternal.c
diff --git a/StandaloneMmPkg/Library/StandaloneMmCoreHobLib/StandaloneMmCoreHobLib.inf b/StandaloneMmPkg/Library/StandaloneMmCoreHobLib/StandaloneMmCoreHobLib.inf
index a2559920e8..34ed536480 100644
--- a/StandaloneMmPkg/Library/StandaloneMmCoreHobLib/StandaloneMmCoreHobLib.inf
+++ b/StandaloneMmPkg/Library/StandaloneMmCoreHobLib/StandaloneMmCoreHobLib.inf
@@ -22,7 +22,7 @@
LIBRARY_CLASS = HobLib|MM_CORE_STANDALONE
#
-# VALID_ARCHITECTURES = X64 AARCH64
+# VALID_ARCHITECTURES = X64 AARCH64 ARM
#
[Sources.common]
Common.c
@@ -30,9 +30,9 @@
[Sources.X64]
X64/StandaloneMmCoreHobLib.c
-[Sources.AARCH64]
- AArch64/StandaloneMmCoreHobLib.c
- AArch64/StandaloneMmCoreHobLibInternal.c
+[Sources.AARCH64, Sources.ARM]
+ Arm/StandaloneMmCoreHobLib.c
+ Arm/StandaloneMmCoreHobLibInternal.c
[Packages]
MdePkg/MdePkg.dec
diff --git a/StandaloneMmPkg/Library/StandaloneMmMemLib/AArch64/StandaloneMmMemLibInternal.c b/StandaloneMmPkg/Library/StandaloneMmMemLib/ArmStandaloneMmMemLibInternal.c
similarity index 86%
rename from StandaloneMmPkg/Library/StandaloneMmMemLib/AArch64/StandaloneMmMemLibInternal.c
rename to StandaloneMmPkg/Library/StandaloneMmMemLib/ArmStandaloneMmMemLibInternal.c
index 4124959e04..fa7df46413 100644
--- a/StandaloneMmPkg/Library/StandaloneMmMemLib/AArch64/StandaloneMmMemLibInternal.c
+++ b/StandaloneMmPkg/Library/StandaloneMmMemLib/ArmStandaloneMmMemLibInternal.c
@@ -20,6 +20,13 @@
//
extern EFI_PHYSICAL_ADDRESS mMmMemLibInternalMaximumSupportAddress;
+#ifdef MDE_CPU_AARCH64
+#define ARM_PHYSICAL_ADDRESS_BITS 36
+#endif
+#ifdef MDE_CPU_ARM
+#define ARM_PHYSICAL_ADDRESS_BITS 32
+#endif
+
/**
Calculate and save the maximum support address.
@@ -31,7 +38,7 @@ MmMemLibInternalCalculateMaximumSupportAddress (
{
UINT8 PhysicalAddressBits;
- PhysicalAddressBits = 36;
+ PhysicalAddressBits = ARM_PHYSICAL_ADDRESS_BITS;
//
// Save the maximum support address in one global variable
diff --git a/StandaloneMmPkg/Library/StandaloneMmMemLib/StandaloneMmMemLib.inf b/StandaloneMmPkg/Library/StandaloneMmMemLib/StandaloneMmMemLib.inf
index 062b0d7a11..b29d97a746 100644
--- a/StandaloneMmPkg/Library/StandaloneMmMemLib/StandaloneMmMemLib.inf
+++ b/StandaloneMmPkg/Library/StandaloneMmMemLib/StandaloneMmMemLib.inf
@@ -28,7 +28,7 @@
#
# The following information is for reference only and not required by the build tools.
#
-# VALID_ARCHITECTURES = IA32 X64 AARCH64
+# VALID_ARCHITECTURES = IA32 X64 AARCH64 ARM
#
[Sources.Common]
@@ -37,8 +37,8 @@
[Sources.IA32, Sources.X64]
X86StandaloneMmMemLibInternal.c
-[Sources.AARCH64]
- AArch64/StandaloneMmMemLibInternal.c
+[Sources.AARCH64, Sources.ARM]
+ ArmStandaloneMmMemLibInternal.c
[Packages]
MdePkg/MdePkg.dec
diff --git a/StandaloneMmPkg/Library/VariableMmDependency/VariableMmDependency.inf b/StandaloneMmPkg/Library/VariableMmDependency/VariableMmDependency.inf
index a2a059c5d6..ffb2a6d083 100644
--- a/StandaloneMmPkg/Library/VariableMmDependency/VariableMmDependency.inf
+++ b/StandaloneMmPkg/Library/VariableMmDependency/VariableMmDependency.inf
@@ -20,7 +20,7 @@
#
# The following information is for reference only and not required by the build tools.
#
-# VALID_ARCHITECTURES = AARCH64
+# VALID_ARCHITECTURES = AARCH64|ARM
#
#
diff --git a/StandaloneMmPkg/StandaloneMmPkg.dsc b/StandaloneMmPkg/StandaloneMmPkg.dsc
index 0c45df95e2..772af1b72b 100644
--- a/StandaloneMmPkg/StandaloneMmPkg.dsc
+++ b/StandaloneMmPkg/StandaloneMmPkg.dsc
@@ -20,7 +20,7 @@
PLATFORM_VERSION = 1.0
DSC_SPECIFICATION = 0x00010011
OUTPUT_DIRECTORY = Build/StandaloneMm
- SUPPORTED_ARCHITECTURES = AARCH64|X64
+ SUPPORTED_ARCHITECTURES = AARCH64|X64|ARM
BUILD_TARGETS = DEBUG|RELEASE
SKUID_IDENTIFIER = DEFAULT
@@ -60,7 +60,7 @@
StandaloneMmDriverEntryPoint|MdePkg/Library/StandaloneMmDriverEntryPoint/StandaloneMmDriverEntryPoint.inf
VariableMmDependency|StandaloneMmPkg/Library/VariableMmDependency/VariableMmDependency.inf
-[LibraryClasses.AARCH64]
+[LibraryClasses.AARCH64, LibraryClasses.ARM]
ArmLib|ArmPkg/Library/ArmLib/ArmBaseLib.inf
StandaloneMmMmuLib|ArmPkg/Library/StandaloneMmMmuLib/ArmMmuStandaloneMmLib.inf
ArmSvcLib|ArmPkg/Library/ArmSvcLib/ArmSvcLib.inf
@@ -118,8 +118,8 @@
StandaloneMmPkg/Library/StandaloneMmMemoryAllocationLib/StandaloneMmMemoryAllocationLib.inf
StandaloneMmPkg/Library/VariableMmDependency/VariableMmDependency.inf
-[Components.AARCH64]
- StandaloneMmPkg/Drivers/StandaloneMmCpu/AArch64/StandaloneMmCpu.inf
+[Components.AARCH64, Components.ARM]
+ StandaloneMmPkg/Drivers/StandaloneMmCpu/StandaloneMmCpu.inf
StandaloneMmPkg/Library/StandaloneMmPeCoffExtraActionLib/StandaloneMmPeCoffExtraActionLib.inf
###################################################################################################
@@ -131,7 +131,7 @@
# module style (EDK or EDKII) specified in [Components] section.
#
###################################################################################################
-[BuildOptions.AARCH64]
+[BuildOptions.AARCH64, BuildOptions.ARM]
GCC:*_*_*_DLINK_FLAGS = -z common-page-size=0x1000 -march=armv8-a+nofp -mstrict-align
GCC:*_*_*_CC_FLAGS = -mstrict-align
--
2.17.1
^ permalink raw reply related [flat|nested] 10+ messages in thread* Re: [PATCH v2 5/5] StandaloneMmPkg: build for 32bit arm machines
2021-05-17 5:49 ` [PATCH v2 5/5] StandaloneMmPkg: build for 32bit arm machines Etienne Carriere
@ 2021-05-17 6:23 ` Etienne Carriere
0 siblings, 0 replies; 10+ messages in thread
From: Etienne Carriere @ 2021-05-17 6:23 UTC (permalink / raw)
To: devel
Cc: Achin Gupta, Ard Biesheuvel, Jiewen Yao, Leif Lindholm,
Sami Mujawar, Sughosh Ganu
Dear all,
For info, Tested on Qemu/arm and stm32mp1 (both armv7-a) and on 64bit
Qemu/AArch64.
I used OP-TEE 3.13.0 to host the StMM instance.
Regards,
Etienne
On Mon, 17 May 2021 at 07:50, Etienne Carriere
<etienne.carriere@linaro.org> wrote:
>
> This change allows to build StandaloneMmPkg components for 32bit Arm
> StandaloneMm firmware.
>
> This change mainly moves AArch64/ source files to Arm/ side directory
> for several components: StandaloneMmCpu, StandaloneMmCoreEntryPoint
> and StandaloneMmMemLib. The source file is built for both 32b and 64b
> Arm targets.
>
> Cc: Achin Gupta <achin.gupta@arm.com>
> Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
> Cc: Jiewen Yao <jiewen.yao@intel.com>
> Cc: Leif Lindholm <leif@nuviainc.com>
> Cc: Sami Mujawar <sami.mujawar@arm.com>
> Cc: Sughosh Ganu <sughosh.ganu@linaro.org>
> Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
> ---
> Changes since v1:
> - ARM_SMC_ID_MM_COMMUNICATE 32b/64b agnostic helper ID is defined
> in ArmStdSmc.h (see 1st commit in this series) instead of being
> local to EventHandle.c.
> - Fix void occurrence to VOID.
> - Fix path in StandaloneMmPkg/StandaloneMmPkg.dsc
> ---
> StandaloneMmPkg/Core/StandaloneMmCore.inf | 2 +-
> StandaloneMmPkg/Drivers/StandaloneMmCpu/{AArch64 => }/EventHandle.c | 5 +++--
> StandaloneMmPkg/Drivers/StandaloneMmCpu/{AArch64 => }/StandaloneMmCpu.c | 2 +-
> StandaloneMmPkg/Drivers/StandaloneMmCpu/{AArch64 => }/StandaloneMmCpu.h | 0
> StandaloneMmPkg/Drivers/StandaloneMmCpu/{AArch64 => }/StandaloneMmCpu.inf | 0
> StandaloneMmPkg/Include/Library/{AArch64 => Arm}/StandaloneMmCoreEntryPoint.h | 0
> StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/{AArch64 => Arm}/CreateHobList.c | 2 +-
> StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/{AArch64 => Arm}/SetPermissions.c | 2 +-
> StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/{AArch64 => Arm}/StandaloneMmCoreEntryPoint.c | 16 ++++++++--------
> StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/StandaloneMmCoreEntryPoint.inf | 14 +++++++-------
> StandaloneMmPkg/Library/StandaloneMmCoreHobLib/{AArch64 => Arm}/StandaloneMmCoreHobLib.c | 0
> StandaloneMmPkg/Library/StandaloneMmCoreHobLib/{AArch64 => Arm}/StandaloneMmCoreHobLibInternal.c | 0
> StandaloneMmPkg/Library/StandaloneMmCoreHobLib/StandaloneMmCoreHobLib.inf | 8 ++++----
> StandaloneMmPkg/Library/StandaloneMmMemLib/{AArch64/StandaloneMmMemLibInternal.c => ArmStandaloneMmMemLibInternal.c} | 9 ++++++++-
> StandaloneMmPkg/Library/StandaloneMmMemLib/StandaloneMmMemLib.inf | 6 +++---
> StandaloneMmPkg/Library/VariableMmDependency/VariableMmDependency.inf | 2 +-
> StandaloneMmPkg/StandaloneMmPkg.dsc | 10 +++++-----
> 17 files changed, 43 insertions(+), 35 deletions(-)
>
> diff --git a/StandaloneMmPkg/Core/StandaloneMmCore.inf b/StandaloneMmPkg/Core/StandaloneMmCore.inf
> index 87bf6e9440..56042b7b39 100644
> --- a/StandaloneMmPkg/Core/StandaloneMmCore.inf
> +++ b/StandaloneMmPkg/Core/StandaloneMmCore.inf
> @@ -17,7 +17,7 @@
> PI_SPECIFICATION_VERSION = 0x00010032
> ENTRY_POINT = StandaloneMmMain
>
> -# VALID_ARCHITECTURES = IA32 X64 AARCH64
> +# VALID_ARCHITECTURES = IA32 X64 AARCH64 ARM
>
> [Sources]
> StandaloneMmCore.c
> diff --git a/StandaloneMmPkg/Drivers/StandaloneMmCpu/AArch64/EventHandle.c b/StandaloneMmPkg/Drivers/StandaloneMmCpu/EventHandle.c
> similarity index 95%
> rename from StandaloneMmPkg/Drivers/StandaloneMmCpu/AArch64/EventHandle.c
> rename to StandaloneMmPkg/Drivers/StandaloneMmCpu/EventHandle.c
> index 63fbe26642..165d696f99 100644
> --- a/StandaloneMmPkg/Drivers/StandaloneMmCpu/AArch64/EventHandle.c
> +++ b/StandaloneMmPkg/Drivers/StandaloneMmCpu/EventHandle.c
> @@ -2,6 +2,7 @@
>
> Copyright (c) 2016 HP Development Company, L.P.
> Copyright (c) 2016 - 2021, Arm Limited. All rights reserved.
> + Copyright (c) 2021, Linaro Limited
>
> SPDX-License-Identifier: BSD-2-Clause-Patent
>
> @@ -92,8 +93,8 @@ PiMmStandaloneArmTfCpuDriverEntry (
> // receipt of a synchronous MM request. Use the Event ID to distinguish
> // between synchronous and asynchronous events.
> //
> - if ((ARM_SMC_ID_MM_COMMUNICATE_AARCH64 != EventId) &&
> - (ARM_SVC_ID_FFA_MSG_SEND_DIRECT_REQ_AARCH64 != EventId)) {
> + if ((ARM_SMC_ID_MM_COMMUNICATE != EventId) &&
> + (ARM_SVC_ID_FFA_MSG_SEND_DIRECT_REQ != EventId)) {
> DEBUG ((DEBUG_INFO, "UnRecognized Event - 0x%x\n", EventId));
> return EFI_INVALID_PARAMETER;
> }
> diff --git a/StandaloneMmPkg/Drivers/StandaloneMmCpu/AArch64/StandaloneMmCpu.c b/StandaloneMmPkg/Drivers/StandaloneMmCpu/StandaloneMmCpu.c
> similarity index 96%
> rename from StandaloneMmPkg/Drivers/StandaloneMmCpu/AArch64/StandaloneMmCpu.c
> rename to StandaloneMmPkg/Drivers/StandaloneMmCpu/StandaloneMmCpu.c
> index d4590bcd19..10097f792f 100644
> --- a/StandaloneMmPkg/Drivers/StandaloneMmCpu/AArch64/StandaloneMmCpu.c
> +++ b/StandaloneMmPkg/Drivers/StandaloneMmCpu/StandaloneMmCpu.c
> @@ -10,7 +10,7 @@
>
> #include <Base.h>
> #include <Pi/PiMmCis.h>
> -#include <Library/AArch64/StandaloneMmCoreEntryPoint.h>
> +#include <Library/Arm/StandaloneMmCoreEntryPoint.h>
> #include <Library/DebugLib.h>
> #include <Library/ArmSvcLib.h>
> #include <Library/ArmLib.h>
> diff --git a/StandaloneMmPkg/Drivers/StandaloneMmCpu/AArch64/StandaloneMmCpu.h b/StandaloneMmPkg/Drivers/StandaloneMmCpu/StandaloneMmCpu.h
> similarity index 100%
> rename from StandaloneMmPkg/Drivers/StandaloneMmCpu/AArch64/StandaloneMmCpu.h
> rename to StandaloneMmPkg/Drivers/StandaloneMmCpu/StandaloneMmCpu.h
> diff --git a/StandaloneMmPkg/Drivers/StandaloneMmCpu/AArch64/StandaloneMmCpu.inf b/StandaloneMmPkg/Drivers/StandaloneMmCpu/StandaloneMmCpu.inf
> similarity index 100%
> rename from StandaloneMmPkg/Drivers/StandaloneMmCpu/AArch64/StandaloneMmCpu.inf
> rename to StandaloneMmPkg/Drivers/StandaloneMmCpu/StandaloneMmCpu.inf
> diff --git a/StandaloneMmPkg/Include/Library/AArch64/StandaloneMmCoreEntryPoint.h b/StandaloneMmPkg/Include/Library/Arm/StandaloneMmCoreEntryPoint.h
> similarity index 100%
> rename from StandaloneMmPkg/Include/Library/AArch64/StandaloneMmCoreEntryPoint.h
> rename to StandaloneMmPkg/Include/Library/Arm/StandaloneMmCoreEntryPoint.h
> diff --git a/StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/AArch64/CreateHobList.c b/StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/Arm/CreateHobList.c
> similarity index 97%
> rename from StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/AArch64/CreateHobList.c
> rename to StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/Arm/CreateHobList.c
> index 4d4cf3d5ff..85f8194687 100644
> --- a/StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/AArch64/CreateHobList.c
> +++ b/StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/Arm/CreateHobList.c
> @@ -14,7 +14,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
> #include <Guid/MmramMemoryReserve.h>
> #include <Guid/MpInformation.h>
>
> -#include <Library/AArch64/StandaloneMmCoreEntryPoint.h>
> +#include <Library/Arm/StandaloneMmCoreEntryPoint.h>
> #include <Library/ArmMmuLib.h>
> #include <Library/ArmSvcLib.h>
> #include <Library/DebugLib.h>
> diff --git a/StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/AArch64/SetPermissions.c b/StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/Arm/SetPermissions.c
> similarity index 96%
> rename from StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/AArch64/SetPermissions.c
> rename to StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/Arm/SetPermissions.c
> index 4a380df4a6..cd4b90823e 100644
> --- a/StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/AArch64/SetPermissions.c
> +++ b/StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/Arm/SetPermissions.c
> @@ -14,7 +14,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
> #include <Guid/MmramMemoryReserve.h>
> #include <Guid/MpInformation.h>
>
> -#include <Library/AArch64/StandaloneMmCoreEntryPoint.h>
> +#include <Library/Arm/StandaloneMmCoreEntryPoint.h>
> #include <Library/ArmMmuLib.h>
> #include <Library/ArmSvcLib.h>
> #include <Library/DebugLib.h>
> diff --git a/StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/AArch64/StandaloneMmCoreEntryPoint.c b/StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/Arm/StandaloneMmCoreEntryPoint.c
> similarity index 94%
> rename from StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/AArch64/StandaloneMmCoreEntryPoint.c
> rename to StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/Arm/StandaloneMmCoreEntryPoint.c
> index b445d6942e..49cf51a789 100644
> --- a/StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/AArch64/StandaloneMmCoreEntryPoint.c
> +++ b/StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/Arm/StandaloneMmCoreEntryPoint.c
> @@ -10,7 +10,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
>
> #include <PiMm.h>
>
> -#include <Library/AArch64/StandaloneMmCoreEntryPoint.h>
> +#include <Library/Arm/StandaloneMmCoreEntryPoint.h>
>
> #include <PiPei.h>
> #include <Guid/MmramMemoryReserve.h>
> @@ -182,13 +182,13 @@ DelegatedEventLoop (
> }
>
> if (FfaEnabled) {
> - EventCompleteSvcArgs->Arg0 = ARM_SVC_ID_FFA_MSG_SEND_DIRECT_RESP_AARCH64;
> + EventCompleteSvcArgs->Arg0 = ARM_SVC_ID_FFA_MSG_SEND_DIRECT_RESP;
> EventCompleteSvcArgs->Arg1 = 0;
> EventCompleteSvcArgs->Arg2 = 0;
> - EventCompleteSvcArgs->Arg3 = ARM_SVC_ID_SP_EVENT_COMPLETE_AARCH64;
> + EventCompleteSvcArgs->Arg3 = ARM_SVC_ID_SP_EVENT_COMPLETE;
> EventCompleteSvcArgs->Arg4 = SvcStatus;
> } else {
> - EventCompleteSvcArgs->Arg0 = ARM_SVC_ID_SP_EVENT_COMPLETE_AARCH64;
> + EventCompleteSvcArgs->Arg0 = ARM_SVC_ID_SP_EVENT_COMPLETE;
> EventCompleteSvcArgs->Arg1 = SvcStatus;
> }
> }
> @@ -273,13 +273,13 @@ InitArmSvcArgs (
> )
> {
> if (FeaturePcdGet (PcdFfaEnable)) {
> - InitMmFoundationSvcArgs->Arg0 = ARM_SVC_ID_FFA_MSG_SEND_DIRECT_RESP_AARCH64;
> + InitMmFoundationSvcArgs->Arg0 = ARM_SVC_ID_FFA_MSG_SEND_DIRECT_RESP;
> InitMmFoundationSvcArgs->Arg1 = 0;
> InitMmFoundationSvcArgs->Arg2 = 0;
> - InitMmFoundationSvcArgs->Arg3 = ARM_SVC_ID_SP_EVENT_COMPLETE_AARCH64;
> + InitMmFoundationSvcArgs->Arg3 = ARM_SVC_ID_SP_EVENT_COMPLETE;
> InitMmFoundationSvcArgs->Arg4 = *Ret;
> } else {
> - InitMmFoundationSvcArgs->Arg0 = ARM_SVC_ID_SP_EVENT_COMPLETE_AARCH64;
> + InitMmFoundationSvcArgs->Arg0 = ARM_SVC_ID_SP_EVENT_COMPLETE;
> InitMmFoundationSvcArgs->Arg1 = *Ret;
> }
> }
> @@ -395,7 +395,7 @@ _ModuleEntryPoint (
> //
> ProcessModuleEntryPointList (HobStart);
>
> - DEBUG ((DEBUG_INFO, "Shared Cpu Driver EP 0x%lx\n", (UINT64) CpuDriverEntryPoint));
> + DEBUG ((DEBUG_INFO, "Shared Cpu Driver EP %p\n", (VOID *) CpuDriverEntryPoint));
>
> finish:
> if (Status == RETURN_UNSUPPORTED) {
> diff --git a/StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/StandaloneMmCoreEntryPoint.inf b/StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/StandaloneMmCoreEntryPoint.inf
> index 4fa426f58e..1762586cfa 100644
> --- a/StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/StandaloneMmCoreEntryPoint.inf
> +++ b/StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/StandaloneMmCoreEntryPoint.inf
> @@ -21,10 +21,10 @@
> # VALID_ARCHITECTURES = IA32 X64 IPF EBC (EBC is for build only)
> #
>
> -[Sources.AARCH64]
> - AArch64/StandaloneMmCoreEntryPoint.c
> - AArch64/SetPermissions.c
> - AArch64/CreateHobList.c
> +[Sources.AARCH64, Sources.ARM]
> + Arm/StandaloneMmCoreEntryPoint.c
> + Arm/SetPermissions.c
> + Arm/CreateHobList.c
>
> [Sources.X64]
> X64/StandaloneMmCoreEntryPoint.c
> @@ -34,14 +34,14 @@
> MdeModulePkg/MdeModulePkg.dec
> StandaloneMmPkg/StandaloneMmPkg.dec
>
> -[Packages.AARCH64]
> +[Packages.ARM, Packages.AARCH64]
> ArmPkg/ArmPkg.dec
>
> [LibraryClasses]
> BaseLib
> DebugLib
>
> -[LibraryClasses.AARCH64]
> +[LibraryClasses.ARM, LibraryClasses.AARCH64]
> StandaloneMmMmuLib
> ArmSvcLib
>
> @@ -51,7 +51,7 @@
> gEfiStandaloneMmNonSecureBufferGuid
> gEfiArmTfCpuDriverEpDescriptorGuid
>
> -[FeaturePcd.AARCH64]
> +[FeaturePcd.ARM, FeaturePcd.AARCH64]
> gArmTokenSpaceGuid.PcdFfaEnable
>
> [BuildOptions]
> diff --git a/StandaloneMmPkg/Library/StandaloneMmCoreHobLib/AArch64/StandaloneMmCoreHobLib.c b/StandaloneMmPkg/Library/StandaloneMmCoreHobLib/Arm/StandaloneMmCoreHobLib.c
> similarity index 100%
> rename from StandaloneMmPkg/Library/StandaloneMmCoreHobLib/AArch64/StandaloneMmCoreHobLib.c
> rename to StandaloneMmPkg/Library/StandaloneMmCoreHobLib/Arm/StandaloneMmCoreHobLib.c
> diff --git a/StandaloneMmPkg/Library/StandaloneMmCoreHobLib/AArch64/StandaloneMmCoreHobLibInternal.c b/StandaloneMmPkg/Library/StandaloneMmCoreHobLib/Arm/StandaloneMmCoreHobLibInternal.c
> similarity index 100%
> rename from StandaloneMmPkg/Library/StandaloneMmCoreHobLib/AArch64/StandaloneMmCoreHobLibInternal.c
> rename to StandaloneMmPkg/Library/StandaloneMmCoreHobLib/Arm/StandaloneMmCoreHobLibInternal.c
> diff --git a/StandaloneMmPkg/Library/StandaloneMmCoreHobLib/StandaloneMmCoreHobLib.inf b/StandaloneMmPkg/Library/StandaloneMmCoreHobLib/StandaloneMmCoreHobLib.inf
> index a2559920e8..34ed536480 100644
> --- a/StandaloneMmPkg/Library/StandaloneMmCoreHobLib/StandaloneMmCoreHobLib.inf
> +++ b/StandaloneMmPkg/Library/StandaloneMmCoreHobLib/StandaloneMmCoreHobLib.inf
> @@ -22,7 +22,7 @@
> LIBRARY_CLASS = HobLib|MM_CORE_STANDALONE
>
> #
> -# VALID_ARCHITECTURES = X64 AARCH64
> +# VALID_ARCHITECTURES = X64 AARCH64 ARM
> #
> [Sources.common]
> Common.c
> @@ -30,9 +30,9 @@
> [Sources.X64]
> X64/StandaloneMmCoreHobLib.c
>
> -[Sources.AARCH64]
> - AArch64/StandaloneMmCoreHobLib.c
> - AArch64/StandaloneMmCoreHobLibInternal.c
> +[Sources.AARCH64, Sources.ARM]
> + Arm/StandaloneMmCoreHobLib.c
> + Arm/StandaloneMmCoreHobLibInternal.c
>
> [Packages]
> MdePkg/MdePkg.dec
> diff --git a/StandaloneMmPkg/Library/StandaloneMmMemLib/AArch64/StandaloneMmMemLibInternal.c b/StandaloneMmPkg/Library/StandaloneMmMemLib/ArmStandaloneMmMemLibInternal.c
> similarity index 86%
> rename from StandaloneMmPkg/Library/StandaloneMmMemLib/AArch64/StandaloneMmMemLibInternal.c
> rename to StandaloneMmPkg/Library/StandaloneMmMemLib/ArmStandaloneMmMemLibInternal.c
> index 4124959e04..fa7df46413 100644
> --- a/StandaloneMmPkg/Library/StandaloneMmMemLib/AArch64/StandaloneMmMemLibInternal.c
> +++ b/StandaloneMmPkg/Library/StandaloneMmMemLib/ArmStandaloneMmMemLibInternal.c
> @@ -20,6 +20,13 @@
> //
> extern EFI_PHYSICAL_ADDRESS mMmMemLibInternalMaximumSupportAddress;
>
> +#ifdef MDE_CPU_AARCH64
> +#define ARM_PHYSICAL_ADDRESS_BITS 36
> +#endif
> +#ifdef MDE_CPU_ARM
> +#define ARM_PHYSICAL_ADDRESS_BITS 32
> +#endif
> +
> /**
> Calculate and save the maximum support address.
>
> @@ -31,7 +38,7 @@ MmMemLibInternalCalculateMaximumSupportAddress (
> {
> UINT8 PhysicalAddressBits;
>
> - PhysicalAddressBits = 36;
> + PhysicalAddressBits = ARM_PHYSICAL_ADDRESS_BITS;
>
> //
> // Save the maximum support address in one global variable
> diff --git a/StandaloneMmPkg/Library/StandaloneMmMemLib/StandaloneMmMemLib.inf b/StandaloneMmPkg/Library/StandaloneMmMemLib/StandaloneMmMemLib.inf
> index 062b0d7a11..b29d97a746 100644
> --- a/StandaloneMmPkg/Library/StandaloneMmMemLib/StandaloneMmMemLib.inf
> +++ b/StandaloneMmPkg/Library/StandaloneMmMemLib/StandaloneMmMemLib.inf
> @@ -28,7 +28,7 @@
> #
> # The following information is for reference only and not required by the build tools.
> #
> -# VALID_ARCHITECTURES = IA32 X64 AARCH64
> +# VALID_ARCHITECTURES = IA32 X64 AARCH64 ARM
> #
>
> [Sources.Common]
> @@ -37,8 +37,8 @@
> [Sources.IA32, Sources.X64]
> X86StandaloneMmMemLibInternal.c
>
> -[Sources.AARCH64]
> - AArch64/StandaloneMmMemLibInternal.c
> +[Sources.AARCH64, Sources.ARM]
> + ArmStandaloneMmMemLibInternal.c
>
> [Packages]
> MdePkg/MdePkg.dec
> diff --git a/StandaloneMmPkg/Library/VariableMmDependency/VariableMmDependency.inf b/StandaloneMmPkg/Library/VariableMmDependency/VariableMmDependency.inf
> index a2a059c5d6..ffb2a6d083 100644
> --- a/StandaloneMmPkg/Library/VariableMmDependency/VariableMmDependency.inf
> +++ b/StandaloneMmPkg/Library/VariableMmDependency/VariableMmDependency.inf
> @@ -20,7 +20,7 @@
> #
> # The following information is for reference only and not required by the build tools.
> #
> -# VALID_ARCHITECTURES = AARCH64
> +# VALID_ARCHITECTURES = AARCH64|ARM
> #
> #
>
> diff --git a/StandaloneMmPkg/StandaloneMmPkg.dsc b/StandaloneMmPkg/StandaloneMmPkg.dsc
> index 0c45df95e2..772af1b72b 100644
> --- a/StandaloneMmPkg/StandaloneMmPkg.dsc
> +++ b/StandaloneMmPkg/StandaloneMmPkg.dsc
> @@ -20,7 +20,7 @@
> PLATFORM_VERSION = 1.0
> DSC_SPECIFICATION = 0x00010011
> OUTPUT_DIRECTORY = Build/StandaloneMm
> - SUPPORTED_ARCHITECTURES = AARCH64|X64
> + SUPPORTED_ARCHITECTURES = AARCH64|X64|ARM
> BUILD_TARGETS = DEBUG|RELEASE
> SKUID_IDENTIFIER = DEFAULT
>
> @@ -60,7 +60,7 @@
> StandaloneMmDriverEntryPoint|MdePkg/Library/StandaloneMmDriverEntryPoint/StandaloneMmDriverEntryPoint.inf
> VariableMmDependency|StandaloneMmPkg/Library/VariableMmDependency/VariableMmDependency.inf
>
> -[LibraryClasses.AARCH64]
> +[LibraryClasses.AARCH64, LibraryClasses.ARM]
> ArmLib|ArmPkg/Library/ArmLib/ArmBaseLib.inf
> StandaloneMmMmuLib|ArmPkg/Library/StandaloneMmMmuLib/ArmMmuStandaloneMmLib.inf
> ArmSvcLib|ArmPkg/Library/ArmSvcLib/ArmSvcLib.inf
> @@ -118,8 +118,8 @@
> StandaloneMmPkg/Library/StandaloneMmMemoryAllocationLib/StandaloneMmMemoryAllocationLib.inf
> StandaloneMmPkg/Library/VariableMmDependency/VariableMmDependency.inf
>
> -[Components.AARCH64]
> - StandaloneMmPkg/Drivers/StandaloneMmCpu/AArch64/StandaloneMmCpu.inf
> +[Components.AARCH64, Components.ARM]
> + StandaloneMmPkg/Drivers/StandaloneMmCpu/StandaloneMmCpu.inf
> StandaloneMmPkg/Library/StandaloneMmPeCoffExtraActionLib/StandaloneMmPeCoffExtraActionLib.inf
>
> ###################################################################################################
> @@ -131,7 +131,7 @@
> # module style (EDK or EDKII) specified in [Components] section.
> #
> ###################################################################################################
> -[BuildOptions.AARCH64]
> +[BuildOptions.AARCH64, BuildOptions.ARM]
> GCC:*_*_*_DLINK_FLAGS = -z common-page-size=0x1000 -march=armv8-a+nofp -mstrict-align
> GCC:*_*_*_CC_FLAGS = -mstrict-align
>
> --
> 2.17.1
>
^ permalink raw reply [flat|nested] 10+ messages in thread