From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-wm0-x22c.google.com (mail-wm0-x22c.google.com [IPv6:2a00:1450:400c:c09::22c]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id D087B1A1E1B for ; Mon, 26 Sep 2016 00:44:44 -0700 (PDT) Received: by mail-wm0-x22c.google.com with SMTP id l132so133882035wmf.1 for ; Mon, 26 Sep 2016 00:44:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc; bh=jNjV6jbLsSxKqFUcs6SaE5ZLbGF2Gc8DIigDZ/uf3eA=; b=MlTVEUMb3CsmkO3wz6cbjP81lCLCOwmX01ZCdFyi+uZtpMT5flEIfJupyq7ynfslv7 dEOc1w921oyD8h+OZreL/+X8vscR3KCsNhXng3PlcgbCYS/y6YBiuYyawbI6BYnbwqtK 2s9tQgcVFswTpUnlwAXA3LnWaJLdXulfwNVFt1fFAY0NA8mKh5Wec93Jx1aOArJl/67o sSPXHeL79hm+zhwSbc9/AGO1vP91P+zEdvLxr6E54hV9hkiByCMoPEsASnqe+ijlppu+ VLcqY+nq1KZVAKCr3DstrxnCo8+djrYRBjtZybEUehTs1WhRj1bQmxhmUOc6yTIQCKMA nCEA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=jNjV6jbLsSxKqFUcs6SaE5ZLbGF2Gc8DIigDZ/uf3eA=; b=VW/qlvBu85oiMS++duWhVI1OGJl5TJRfFl9kQizCt021FEKKXSa923v1pOZ2+vz6EQ 5LBAVdZmi/O2mQI6pZB6xSXYIN579owuTezxUW+zGvlOndml/Jw2FBGaJAsvEx4i8v2H 8BQxrVmTgHob0puqDALhNXxcJ5uJndPW9fwX5P9zE7m+ZR0rxyh0BzoTEcwOf4W6cnKC kQvBn+3RxbfE5u5/Bkk67D6AZQgVtnmBN7Aknd+cboI8nQej+iDxaGYKS6dKFJrNa3gE u3czTykNBRK3iczi4kdUIf/slziVbZfcEaiR2ClctanLLm68Uz05iIpmzZOA4lbDewPk iq3g== X-Gm-Message-State: AA6/9Rkp80kxadwMbaqknClz4uneTeJqQVmDYg/T3P0Om0qCrkmIX+FwpXwMNuZKkEpkl47nUqNfzkPiNTC2KA== X-Received: by 10.194.147.229 with SMTP id tn5mr1625007wjb.127.1474875883240; Mon, 26 Sep 2016 00:44:43 -0700 (PDT) MIME-Version: 1.0 Received: by 10.28.36.212 with HTTP; Mon, 26 Sep 2016 00:44:42 -0700 (PDT) In-Reply-To: References: From: Michael Zimmermann Date: Mon, 26 Sep 2016 09:44:42 +0200 Message-ID: To: Ard Biesheuvel Cc: "edk2-devel@lists.01.org" , Leif Lindholm X-Content-Filtered-By: Mailman/MimeDel 2.1.21 Subject: Re: System hang when using SetMemoryAttributes X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 26 Sep 2016 07:44:45 -0000 Content-Type: text/plain; charset=UTF-8 oh and in case it makes a difference: it's a 64bit ARM device running 32bit code. On Mon, Sep 26, 2016 at 9:13 AM, Michael Zimmermann < sigmaepsilon92@gmail.com> wrote: > Ard, > > I have to mark the framebuffer as uncached, because if writes to it are > cached, they don't instantly reach the underlying hardware. I'd have to > manually flush the cache for that region every time otherwise. > > Isn't that the normal way? I don't think that any device would work with a > write-cache framebuffer - I actually copied the code from the ArmVirt LCD > drivers which do the same. > > Thanks > Michael > > On Mon, Sep 26, 2016 at 8:35 AM, Ard Biesheuvel > wrote: > >> On 25 September 2016 at 20:01, Michael Zimmermann >> wrote: >> > Hi, >> > >> > which side effects can SetMemoryAttributes have? >> > I have a device where setting the framebuffer(which is part of DRAM) to >> > EFI_MEMORY_UC makes UEFI hang later on(when already outside the lcd >> driver). >> > >> > If I do the same on a memory range allocated with AllocateAnyPages >> instead >> > of AllocateAddress UEFI boots just fine(but ofc, the screen doesn't >> work). >> > >> > Unfortunately I don't have UART on that device but I'm sure there's no >> > assert because I configured DebugLib to reboot the device in that case - >> > which never happens, it's just stuck when the console >> drivers(TerminalDxe >> > etc) initialize later on. >> > >> >> Hello Michael, >> >> EFI_MEMORY_WC is more suitable for a framebuffer than EFI_MEMORY_UC, >> since the latter does not allow unaligned accesses, so any unaligned >> store will crash the system. >> >> Since the framebuffer is in DRAM, I assume the reason for setting the >> memory attributes is that the device is not DMA coherent? Could you >> perhaps describe the hardware in more detail? >> >> -- >> Ard. >> > >