flat mapping vs identity mapping on ARM

flat mapping vs identity mapping on ARM

[valerij zaporogeci]

In the ARM architecture, there is such a thing - "flat mapping", where
MMU stage 1 is disabled and the mapping done is 1:1 and attributes set
to the predefined values.
Did I understand right, that this is NOT what UEFI means by "identity
mapping" with MMU enabled? And in the latter case there is need to
create all those page tables and stuff, setting 1:1 mapping between VA
and PA? If so, why to do that? Why "flat mapping" isn't what UEFI
would love to see as its mapping regime?

Re: flat mapping vs identity mapping on ARM

[Ard Biesheuvel]

On 22 September 2016 at 15:30, valerij zaporogeci <vlrzprgts@gmail.com> wrote:
> In the ARM architecture, there is such a thing - "flat mapping", where
> MMU stage 1 is disabled and the mapping done is 1:1 and attributes set
> to the predefined values.

What do you mean by 'attributes set to the predefined values' ?

> Did I understand right, that this is NOT what UEFI means by "identity
> mapping" with MMU enabled? And in the latter case there is need to
> create all those page tables and stuff, setting 1:1 mapping between VA
> and PA? If so, why to do that? Why "flat mapping" isn't what UEFI
> would love to see as its mapping regime?

On ARM, you need to enable the MMU in order to enable the Dcache.

Re: flat mapping vs identity mapping on ARM

[valerij zaporogeci]

2016-09-22 18:03 GMT+03:00, Ard Biesheuvel <ard.biesheuvel@linaro.org>:
> On 22 September 2016 at 15:30, valerij zaporogeci <vlrzprgts@gmail.com>
> wrote:
>> In the ARM architecture, there is such a thing - "flat mapping", where
>> MMU stage 1 is disabled and the mapping done is 1:1 and attributes set
>> to the predefined values.
>
> What do you mean by 'attributes set to the predefined values' ?
>

I meant what is written in the section B3.2.1, short quote:
"For all other accesses, when a stage 1 MMU is disabled, the assigned
attributes depend on whether
the access is a data access or an instruction access, as follows:
Data access
The stage 1 translation assigns the Strongly-Ordered memory type"

... and then, more lengthy description for instruction access.


>
> On ARM, you need to enable the MMU in order to enable the Dcache.
>

Thank you, I suspected this is for this, just wanted to be sure.

Re: flat mapping vs identity mapping on ARM

[Ard Biesheuvel]

On 22 September 2016 at 16:19, valerij zaporogeci <vlrzprgts@gmail.com> wrote:
> 2016-09-22 18:03 GMT+03:00, Ard Biesheuvel <ard.biesheuvel@linaro.org>:
>> On 22 September 2016 at 15:30, valerij zaporogeci <vlrzprgts@gmail.com>
>> wrote:
>>> In the ARM architecture, there is such a thing - "flat mapping", where
>>> MMU stage 1 is disabled and the mapping done is 1:1 and attributes set
>>> to the predefined values.
>>
>> What do you mean by 'attributes set to the predefined values' ?
>>
>
> I meant what is written in the section B3.2.1, short quote:
> "For all other accesses, when a stage 1 MMU is disabled, the assigned
> attributes depend on whether
> the access is a data access or an instruction access, as follows:
> Data access
> The stage 1 translation assigns the Strongly-Ordered memory type"
>
> ... and then, more lengthy description for instruction access.
>
>

Yes, so what this means is that all data accesses are strongly
ordered, and instruction fetches are cacheable.

So while you can enable both the data and the instruction cache with
the MMU off, only the instruction cache is actually functional, since
all data accesses or non-cacheable

Re: flat mapping vs identity mapping on ARM

[Ard Biesheuvel]

On 22 September 2016 at 16:22, Ard Biesheuvel <ard.biesheuvel@linaro.org> wrote:
> On 22 September 2016 at 16:19, valerij zaporogeci <vlrzprgts@gmail.com> wrote:
>> 2016-09-22 18:03 GMT+03:00, Ard Biesheuvel <ard.biesheuvel@linaro.org>:
>>> On 22 September 2016 at 15:30, valerij zaporogeci <vlrzprgts@gmail.com>
>>> wrote:
>>>> In the ARM architecture, there is such a thing - "flat mapping", where
>>>> MMU stage 1 is disabled and the mapping done is 1:1 and attributes set
>>>> to the predefined values.
>>>
>>> What do you mean by 'attributes set to the predefined values' ?
>>>
>>
>> I meant what is written in the section B3.2.1, short quote:
>> "For all other accesses, when a stage 1 MMU is disabled, the assigned
>> attributes depend on whether
>> the access is a data access or an instruction access, as follows:
>> Data access
>> The stage 1 translation assigns the Strongly-Ordered memory type"
>>
>> ... and then, more lengthy description for instruction access.
>>
>>
>
> Yes, so what this means is that all data accesses are strongly
> ordered, and instruction fetches are cacheable.
>
> So while you can enable both the data and the instruction cache with
> the MMU off, only the instruction cache is actually functional, since
> all data accesses or non-cacheable

*are* non-cacheable

Re: flat mapping vs identity mapping on ARM

[Andrew Fish]

> On Sep 22, 2016, at 8:03 AM, Ard Biesheuvel <ard.biesheuvel@linaro.org> wrote:
> 
> On 22 September 2016 at 15:30, valerij zaporogeci <vlrzprgts@gmail.com <mailto:vlrzprgts@gmail.com>> wrote:
>> In the ARM architecture, there is such a thing - "flat mapping", where
>> MMU stage 1 is disabled and the mapping done is 1:1 and attributes set
>> to the predefined values.
> 
> What do you mean by 'attributes set to the predefined values' ?
> 
>> Did I understand right, that this is NOT what UEFI means by "identity
>> mapping" with MMU enabled?

Identity mapping means the virtual address is the same as the physical address. 

For x86 IA64 (x86_64) you have to have paging enabled to enter long (64-bit) mode (the processor comes out of reset in 16-bit mode). For ARM you need the MMU to control cacheability.

For IA32 (i386) paging is not enabled and MTRR registers are used to control cacheability. For Itainium Processors paging is not enabled and bit 63 is used to disable cacheability.

Thanks,

Andrew Fish

>> And in the latter case there is need to
>> create all those page tables and stuff, setting 1:1 mapping between VA
>> and PA? If so, why to do that? Why "flat mapping" isn't what UEFI
>> would love to see as its mapping regime?
> 
> On ARM, you need to enable the MMU in order to enable the Dcache.
> _______________________________________________
> edk2-devel mailing list
> edk2-devel@lists.01.org <mailto:edk2-devel@lists.01.org>
> https://lists.01.org/mailman/listinfo/edk2-devel <https://lists.01.org/mailman/listinfo/edk2-devel>

Re: flat mapping vs identity mapping on ARM

[valerij zaporogeci]

Thank you, Ard and Andrew.