From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-lf1-f49.google.com (mail-lf1-f49.google.com [209.85.167.49]) by mx.groups.io with SMTP id smtpd.web12.6362.1661821077635237592 for ; Mon, 29 Aug 2022 17:57:58 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@gmail.com header.s=20210112 header.b=Irdiffww; spf=pass (domain: gmail.com, ip: 209.85.167.49, mailfrom: benjamin.doron00@gmail.com) Received: by mail-lf1-f49.google.com with SMTP id v26so3219061lfd.10 for ; Mon, 29 Aug 2022 17:57:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc; bh=tFLHqTEJUWJWNfA0RRpd4ep6l/On3bkz5qMSQN+FEa4=; b=IrdiffwwPlblLeNUxWD+DBr3n5lj93C/TOrA26pNElbZTtN94CBFedwXETi94Iatud PfPUn+4y/ZccEig/pKeHDFEuHlQnGgKlfjXWDi8z6foK3cB7FMKdLsCmsEjFsMJE5fru MsHIzcsHIqqlR+oP6NOuqaoB0n9ktfFEG7gcZqrlGvzOQQrMIhAuf0E9dPsZ6RHHD/OL ZPRS/R9O4VuxMzGqbgvY7JfizoHC9cHUXOeFxRvVRFAuR6QvMEGoZ9E6D2nyJkGFYAY+ 1hDc5NxMpjROx/AWVqmyoYSiLJFoR/fXg7+5BspvPhMqA8rkTTJS6Ob4uDpbWflMH7IW Fwlw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc; bh=tFLHqTEJUWJWNfA0RRpd4ep6l/On3bkz5qMSQN+FEa4=; b=uc+s/uD6kPcu8xWOsd5Oj9L373mUhjaiwBMT4eQwiWa2ySDeDAxOPzvzD6c2QeYdwY 8oEoXt0Qeo7fYg5/gD6R0LHBplzRpYTG4NuWt0lQVQ4jLZ73o3OhX6GJSTRj5scJvWaR H8fPvEOdL6bO3OnF2x5AV4fLMr+cFwDGLqDn02dEM4XD9m6qcgQxEIURB5iR8luOAcwI /SpAt0gLc2L8DJnRSSDiM8bdhLo5SScvXjfeXMysUBSjOMzk2lvJrgMwg8KvpbGIj4J+ 4Xm+cChtkmXGP3moMh29OukSbPZddjwGi+fyzF2Y4WMrRUxfC6NJYbw2pfJrX0zLD/Vt Co9A== X-Gm-Message-State: ACgBeo2SMLsLs61ghmUTmfWM4k16Z2ZzfiQI8hltBoYiPFgj+0EXRZ6f 80vr9gzndMLj4ao4gzyTSX5PspIqZ13kTUsDOq8= X-Google-Smtp-Source: AA6agR4kiHv6P0CyEybR852Lyl6jYhe2rDjsIPDqBLj6zR/U4Px5gq0Dqgq4NvRq623nRQPXdXwtkmUVUCNkFOQ6ras= X-Received: by 2002:a05:6512:2987:b0:492:e469:b327 with SMTP id du7-20020a056512298700b00492e469b327mr2948741lfb.534.1661821075798; Mon, 29 Aug 2022 17:57:55 -0700 (PDT) MIME-Version: 1.0 References: <5d3ee2d57676168af4d0a001683a719a5e57b66a.1661799519.git.benjamin.doron00@gmail.com> In-Reply-To: From: "Benjamin Doron" Date: Mon, 29 Aug 2022 20:57:44 -0400 Message-ID: Subject: Re: [edk2-devel][edk2-platforms][PATCH v1 2/5] Silicon/Intel: Port SmmControl protocol to PPI for S3 To: "Oram, Isaac W" Cc: "devel@edk2.groups.io" , "Desimone, Nathaniel L" , "Sinha, Ankit" , "Ni, Ray" , "Chaganty, Rangasai V" Content-Type: multipart/alternative; boundary="000000000000e7405605e76adea3" --000000000000e7405605e76adea3 Content-Type: text/plain; charset="UTF-8" Right, but Kabylake has a different implementation that retrieves it from HW registers - PchAcpiBaseGet(). This is probably optional, there is a PCD, but it's in a different package scope. I don't know how to handle the Packages in the INF to keep this silicon package agnostic. For that matter, it might not really be a CFL *plus* shim, because Tigerlake, etc are different package DECs too. Best regards, Benjamin On Mon, 29 Aug 2022 at 19:17, Oram, Isaac W wrote: > I think that the shim lib might be overkill. PmcGetAcpiBase just resolves > to PcdGet16 (PcdAcpiBaseAddress); > I think that you should be able to use that PCD for any Intel > chipset/silicon for the foreseeable future. > > I would prefer to see contents of sections in INF files indented, but it > is a nit. > > Regards, > Isaac > > -----Original Message----- > From: devel@edk2.groups.io On Behalf Of Benjamin > Doron > Sent: Monday, August 29, 2022 1:36 PM > To: devel@edk2.groups.io > Cc: Desimone, Nathaniel L ; Sinha, Ankit < > ankit.sinha@intel.com>; Ni, Ray ; Chaganty, Rangasai V < > rangasai.v.chaganty@intel.com>; Oram, Isaac W > Subject: [edk2-devel][edk2-platforms][PATCH v1 2/5] Silicon/Intel: Port > SmmControl protocol to PPI for S3 > > S3 resume may require communication with SMM, for which we need the > SmmControl PPI. Therefore, port the DXE drivers to a library, like there is > for SMM Access. > > As the registers are common across Intel platforms in the tree, while a > helper function definition is not, implement a new library as a > compatibility shim. > > Tested, working on Kabylake. Further testing required after the refactor > for compatibility. > > Cc: Nate DeSimone > Cc: Ankit Sinha > Cc: Ray Ni > Cc: Rangasai V Chaganty > Cc: Isaac Oram > Signed-off-by: Benjamin Doron > --- > .../BaseIntelCompatShimLibCfl.c | 24 ++ > .../BaseIntelCompatShimLibCfl.inf | 24 ++ > .../PeiSmmControlLib/PeiSmmControlLib.c | 309 ++++++++++++++++++ > .../PeiSmmControlLib/PeiSmmControlLib.inf | 36 ++ > .../Include/Library/IntelCompatShimLib.h | 20 ++ > .../Include/Library/SmmControlLib.h | 26 ++ > .../Intel/IntelSiliconPkg/IntelSiliconPkg.dec | 4 + > .../BaseIntelCompatShimLibKbl.c | 29 ++ > .../BaseIntelCompatShimLibKbl.inf | 24 ++ > 9 files changed, 496 insertions(+) > create mode 100644 > Silicon/Intel/CoffeelakeSiliconPkg/Library/BaseIntelCompatShimLibCfl/BaseIntelCompatShimLibCfl.c > create mode 100644 > Silicon/Intel/CoffeelakeSiliconPkg/Library/BaseIntelCompatShimLibCfl/BaseIntelCompatShimLibCfl.inf > create mode 100644 > Silicon/Intel/IntelSiliconPkg/Feature/SmmControl/Library/PeiSmmControlLib/PeiSmmControlLib.c > create mode 100644 > Silicon/Intel/IntelSiliconPkg/Feature/SmmControl/Library/PeiSmmControlLib/PeiSmmControlLib.inf > create mode 100644 > Silicon/Intel/IntelSiliconPkg/Include/Library/IntelCompatShimLib.h > create mode 100644 > Silicon/Intel/IntelSiliconPkg/Include/Library/SmmControlLib.h > create mode 100644 > Silicon/Intel/KabylakeSiliconPkg/Library/BaseIntelCompatShimLibKbl/BaseIntelCompatShimLibKbl.c > create mode 100644 > Silicon/Intel/KabylakeSiliconPkg/Library/BaseIntelCompatShimLibKbl/BaseIntelCompatShimLibKbl.inf > > diff --git > a/Silicon/Intel/CoffeelakeSiliconPkg/Library/BaseIntelCompatShimLibCfl/BaseIntelCompatShimLibCfl.c > b/Silicon/Intel/CoffeelakeSiliconPkg/Library/BaseIntelCompatShimLibCfl/BaseIntelCompatShimLibCfl.c > new file mode 100644 > index 000000000000..5353126267e6 > --- /dev/null > +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Library/BaseIntelCompatShimLibC > +++ fl/BaseIntelCompatShimLibCfl.c > @@ -0,0 +1,24 @@ > +/** @file > + A Coffeelake+ compatibility shim > + > + Copyright (c) 2022, Baruch Binyamin Doron
> + SPDX-License-Identifier: BSD-2-Clause-Patent > + > +**/ > + > +#include > +#include > + > +/** > + Get PCH ACPI base address. > + > + @retval Address Address of PWRM base address. > +**/ > +UINT16 > +EFIAPI > +CompatShimGetAcpiBase ( > + VOID > + ) > +{ > + return PmcGetAcpiBase (); > +} > diff --git > a/Silicon/Intel/CoffeelakeSiliconPkg/Library/BaseIntelCompatShimLibCfl/BaseIntelCompatShimLibCfl.inf > b/Silicon/Intel/CoffeelakeSiliconPkg/Library/BaseIntelCompatShimLibCfl/BaseIntelCompatShimLibCfl.inf > new file mode 100644 > index 000000000000..48b071ed05ae > --- /dev/null > +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Library/BaseIntelCompatShimLibC > +++ fl/BaseIntelCompatShimLibCfl.inf > @@ -0,0 +1,24 @@ > +## @file > +# Library description file for the Coffeelake+ compatibility shim # # > +Copyright (c) 2022, Baruch Binyamin Doron
# > +SPDX-License-Identifier: BSD-2-Clause-Patent # ## > + > +[Defines] > +INF_VERSION = 0x00010017 > +BASE_NAME = BaseIntelCompatShimLibCfl > +FILE_GUID = 3D0BB32E-D328-4615-ADFC-782CECC68D53 > +VERSION_STRING = 1.0 > +MODULE_TYPE = BASE > +LIBRARY_CLASS = IntelCompatShimLib > + > +[LibraryClasses] > +PmcLib > + > +[Packages] > +CoffeelakeSiliconPkg/SiPkg.dec > + > +[Sources] > +BaseIntelCompatShimLibCfl.c > diff --git > a/Silicon/Intel/IntelSiliconPkg/Feature/SmmControl/Library/PeiSmmControlLib/PeiSmmControlLib.c > b/Silicon/Intel/IntelSiliconPkg/Feature/SmmControl/Library/PeiSmmControlLib/PeiSmmControlLib.c > new file mode 100644 > index 000000000000..80c2c1be90b1 > --- /dev/null > +++ b/Silicon/Intel/IntelSiliconPkg/Feature/SmmControl/Library/PeiSmmCon > +++ trolLib/PeiSmmControlLib.c > @@ -0,0 +1,309 @@ > +/** @file+ This is to publish the SMM Control Ppi instance.++ Copyright > (c) 2019 - 2020, Intel Corporation. All rights reserved.
+ > SPDX-License-Identifier: BSD-2-Clause-Patent++**/+#include > +#include +#include > +#include +#include > +#include > ++#include +#include > ++#define SMM_CONTROL_PRIVATE_DATA_SIGNATURE > SIGNATURE_32 ('i', '4', 's', 'c')++typedef struct {+ UINTN > Signature;+ EFI_HANDLE Handle;+ > EFI_PEI_MM_CONTROL_PPI SmmControl;+} > SMM_CONTROL_PRIVATE_DATA;++#define SMM_CONTROL_PRIVATE_DATA_FROM_THIS(a) > \+ CR (a, \+ SMM_CONTROL_PRIVATE_DATA, \+ > SmmControl, \+ SMM_CONTROL_DEV_SIGNATURE \+ )++//+// Common > registers:+//+//+// APM Registers+//+#define R_PCH_APM_CNT > 0xB2+//+// ACPI and legacy I/O register offsets from > ACPIBASE+//+#define R_PCH_ACPI_PM1_STS 0x00+#define > B_PCH_ACPI_PM1_STS_PRBTNOR BIT11++#define R_PCH_SMI_EN > 0x30++#define R_PCH_SMI_STS > 0x34+#define B_PCH_SMI_STS_APM BIT5+#define > B_PCH_SMI_EN_APMC BIT5+#define B_PCH_SMI_EN_EOS > BIT1+#define B_PCH_SMI_EN_GBL_SMI > BIT0++/**+ Trigger the software SMI++ @param[in] Data > The value to be set on the software SMI data port++ @retval EFI_SUCCESS > Function completes successfully+**/+EFI_STATUS+EFIAPI+SmmTrigger > (+ UINT8 Data+ )+{+ UINT16 ABase;+ UINT32 OutputData;+ UINT32 > OutputPort;++ ABase = CompatShimGetAcpiBase ();++ ///+ /// Enable the > APMC SMI+ ///+ OutputPort = ABase + R_PCH_SMI_EN;+ OutputData = > IoRead32 ((UINTN) OutputPort);+ OutputData |= (B_PCH_SMI_EN_APMC | > B_PCH_SMI_EN_GBL_SMI);+ DEBUG (+ (DEBUG_EVENT,+ "The SMI Control > Port at address %x will be written to %x.\n",+ OutputPort,+ > OutputData)+ );+ IoWrite32 (+ (UINTN) OutputPort,+ (UINT32) > (OutputData)+ );++ OutputPort = R_PCH_APM_CNT;+ OutputData = > Data;++ ///+ /// Generate the APMC SMI+ ///+ IoWrite8 (+ (UINTN) > OutputPort,+ (UINT8) (OutputData)+ );++ return EFI_SUCCESS;+}++/**+ > Clear the SMI status+++ @retval EFI_SUCCESS The function > completes successfully+ @retval EFI_DEVICE_ERROR Something error > occurred+**/+EFI_STATUS+EFIAPI+SmmClear (+ VOID+ )+{+ UINT16 ABase;+ > UINT32 OutputData;+ UINT32 OutputPort;++ ABase = CompatShimGetAcpiBase > ();++ ///+ /// Clear the Power Button Override Status Bit, it gates EOS > from being set.+ ///+ OutputPort = ABase + R_PCH_ACPI_PM1_STS;+ > OutputData = B_PCH_ACPI_PM1_STS_PRBTNOR;+ DEBUG (+ (DEBUG_EVENT,+ > "The PM1 Status Port at address %x will be written to %x.\n",+ > OutputPort,+ OutputData)+ );+ IoWrite16 (+ (UINTN) > OutputPort,+ (UINT16) (OutputData)+ );++ ///+ /// Clear the APM SMI > Status Bit+ ///+ OutputPort = ABase + R_PCH_SMI_STS;+ OutputData = > B_PCH_SMI_STS_APM;+ DEBUG (+ (DEBUG_EVENT,+ "The SMI Status Port at > address %x will be written to %x.\n",+ OutputPort,+ OutputData)+ > );+ IoWrite32 (+ (UINTN) OutputPort,+ (UINT32) (OutputData)+ > );++ ///+ /// Set the EOS Bit+ ///+ OutputPort = ABase + > R_PCH_SMI_EN;+ OutputData = IoRead32 ((UINTN) OutputPort);+ OutputData > |= B_PCH_SMI_EN_EOS;+ DEBUG (+ (DEBUG_EVENT,+ "The SMI Control Port > at address %x will be written to %x.\n",+ OutputPort,+ > OutputData)+ );+ IoWrite32 (+ (UINTN) OutputPort,+ (UINT32) > (OutputData)+ );++ ///+ /// There is no need to read EOS back and > check if it is set.+ /// This can lead to a reading of zero if an SMI > occurs right after the SMI_EN port read+ /// but before the data is > returned to the CPU.+ /// SMM Dispatcher should make sure that EOS is set > after all SMI sources are processed.+ ///+ return EFI_SUCCESS;+}++/**+ > This routine generates an SMI++ @param[in] This The > EFI SMM Control protocol instance+ @param[in, out] ArgumentBuffer > The buffer of argument+ @param[in, out] ArgumentBufferSize The size of > the argument buffer+ @param[in] Periodic Periodic or > not+ @param[in] ActivationInterval Interval of periodic SMI++ > @retval EFI Status Describing the result of the > operation+ @retval EFI_INVALID_PARAMETER Some parameter value > passed is not supported+**/+EFI_STATUS+EFIAPI+Activate (+ IN > EFI_PEI_SERVICES **PeiServices,+ IN EFI_PEI_MM_CONTROL_PPI * > This,+ IN OUT INT8 *ArgumentBuffer OPTIONAL,+ IN OUT > UINTN *ArgumentBufferSize OPTIONAL,+ IN BOOLEAN > Periodic OPTIONAL,+ IN UINTN ActivationInterval > OPTIONAL+ )+{+ EFI_STATUS Status;+ UINT8 Data;++ if (Periodic) > {+ DEBUG ((DEBUG_WARN, "Invalid parameter\n"));+ return > EFI_INVALID_PARAMETER;+ }++ // NOTE: Copied from Quark. Matches the usage > in PiSmmCommunicationPei+ if (ArgumentBuffer == NULL) {+ Data = 0xFF;+ > } else {+ if (ArgumentBufferSize == NULL || *ArgumentBufferSize != 1) > {+ return EFI_INVALID_PARAMETER;+ }++ Data = *ArgumentBuffer;+ > }+ ///+ /// Clear any pending the APM SMI+ ///+ Status = SmmClear ();+ > if (EFI_ERROR (Status)) {+ return Status;+ }++ return SmmTrigger > (Data);+}++/**+ This routine clears an SMI++ @param[in] This > The EFI SMM Control protocol instance+ @param[in] Periodic > Periodic or not++ @retval EFI Status Describing the result > of the operation+ @retval EFI_INVALID_PARAMETER Some parameter value > passed is not supported+**/+EFI_STATUS+EFIAPI+Deactivate (+ IN > EFI_PEI_SERVICES **PeiServices,+ IN EFI_PEI_MM_CONTROL_PPI * > This,+ IN BOOLEAN Periodic OPTIONAL+ )+{+ if (Periodic) > {+ return EFI_INVALID_PARAMETER;+ }++ return SmmClear ();+}++/**+ > This function is to install an SMM Control PPI+ - Introduction \n+ > An API to install an instance of EFI_PEI_MM_CONTROL_PPI. This PPI > provides a standard+ way for other modules to trigger software SMIs.++ > @retval EFI_SUCCESS - Ppi successfully started and installed.+ > @retval EFI_NOT_FOUND - Ppi can't be found.+ @retval > EFI_OUT_OF_RESOURCES - Ppi does not have enough resources to initialize > the driver.+**/+EFI_STATUS+EFIAPI+PeiInstallSmmControlPpi (+ VOID+ )+{+ > EFI_STATUS Status;+ EFI_PEI_PPI_DESCRIPTOR > *PpiList;+ SMM_CONTROL_PRIVATE_DATA *SmmControlPrivate;++ //+ // > Initialize private data+ //+ SmmControlPrivate = AllocateZeroPool > (sizeof (*SmmControlPrivate));+ ASSERT (SmmControlPrivate != NULL);+ if > (SmmControlPrivate == NULL) {+ return EFI_OUT_OF_RESOURCES;+ }+ > PpiList = AllocateZeroPool (sizeof (*PpiList));+ ASSERT (PpiList > != NULL);+ if (PpiList == NULL) {+ return EFI_OUT_OF_RESOURCES;+ }++ > SmmControlPrivate->Signature = SMM_CONTROL_PRIVATE_DATA_SIGNATURE;+ > SmmControlPrivate->Handle = NULL;++ > SmmControlPrivate->SmmControl.Trigger = Activate;+ > SmmControlPrivate->SmmControl.Clear = Deactivate;++ //+ // Install > PPI+ //+ PpiList->Flags = (EFI_PEI_PPI_DESCRIPTOR_PPI | > EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST);+ PpiList->Guid = > &gEfiPeiMmControlPpiGuid;+ PpiList->Ppi = > &SmmControlPrivate->SmmControl;++ Status = PeiServicesInstallPpi > (PpiList);+ ASSERT_EFI_ERROR (Status);++ // Unlike driver, do not disable > SMIs as S3 resume continues+ return EFI_SUCCESS;+}diff --git > a/Silicon/Intel/IntelSiliconPkg/Feature/SmmControl/Library/PeiSmmControlLib/PeiSmmControlLib.inf > b/Silicon/Intel/IntelSiliconPkg/Feature/SmmControl/Library/PeiSmmControlLib/PeiSmmControlLib.inf > new file mode 100644 > index 000000000000..92f2879d82ab > --- /dev/null > +++ b/Silicon/Intel/IntelSiliconPkg/Feature/SmmControl/Library/PeiSmmCon > +++ trolLib/PeiSmmControlLib.inf > @@ -0,0 +1,36 @@ > +## @file+# Library description file for the SmmControl PPI+#+# > +Copyright (c) 2019, Intel Corporation. All rights reserved.
+# > +SPDX-License-Identifier: > +BSD-2-Clause-Patent+#+##++[Defines]+INF_VERSION = 0x00010017+BASE_NAME > += PeiSmmControlLib+FILE_GUID = > +F45D521A-C0DF-4283-A3CA-65AD01B479E7+VERSION_STRING = 1.0+MODULE_TYPE = > +PEIM+LIBRARY_CLASS = > +SmmControlLib+++[LibraryClasses]+IntelCompatShimLib+IoLib+DebugLib+Memo > +ryAllocationLib+PeiServicesLib+++[Packages]+MdePkg/MdePkg.dec+IntelSili > +conPkg/IntelSiliconPkg.dec+++[Sources]+PeiSmmControlLib.c+++[Ppis]+gEfi > +PeiMmControlPpiGuid ## PRODUCESdiff --git > +a/Silicon/Intel/IntelSiliconPkg/Include/Library/IntelCompatShimLib.h > +b/Silicon/Intel/IntelSiliconPkg/Include/Library/IntelCompatShimLib.h > new file mode 100644 > index 000000000000..f8621d92e41a > --- /dev/null > +++ b/Silicon/Intel/IntelSiliconPkg/Include/Library/IntelCompatShimLib.h > @@ -0,0 +1,20 @@ > +/** @file > + Library description file for compatibility shim > + > + Copyright (c) 2022, Baruch Binyamin Doron
> + SPDX-License-Identifier: BSD-2-Clause-Patent > + > +**/ > + > +#include > + > +/** > + Get PCH ACPI base address. > + > + @retval Address Address of PWRM base address. > +**/ > +UINT16 > +EFIAPI > +CompatShimGetAcpiBase ( > + VOID > + ); > diff --git a/Silicon/Intel/IntelSiliconPkg/Include/Library/SmmControlLib.h > b/Silicon/Intel/IntelSiliconPkg/Include/Library/SmmControlLib.h > new file mode 100644 > index 000000000000..b532dd13f373 > --- /dev/null > +++ b/Silicon/Intel/IntelSiliconPkg/Include/Library/SmmControlLib.h > @@ -0,0 +1,26 @@ > +/** @file+ This is to publish the SMM Control Ppi instance.++ Copyright > (c) 2019 - 2020, Intel Corporation. All rights reserved.
+ > SPDX-License-Identifier: BSD-2-Clause-Patent++**/+#ifndef > _SMM_CONTROL_LIB_H_+#define _SMM_CONTROL_LIB_H_++/**+ This function is to > install an SMM Control PPI+ - Introduction \n+ An API to install > an instance of EFI_PEI_MM_CONTROL_PPI. This PPI provides a standard+ way > for other modules to trigger software SMIs.++ @retval EFI_SUCCESS > - Ppi successfully started and installed.+ @retval EFI_NOT_FOUND > - Ppi can't be found.+ @retval EFI_OUT_OF_RESOURCES - Ppi does not > have enough resources to initialize the > driver.+**/+EFI_STATUS+EFIAPI+PeiInstallSmmControlPpi (+ VOID+ > );+#endifdiff --git a/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec > b/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec > index c36d130a0197..fc27b394d267 100644 > --- a/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec > +++ b/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec > @@ -35,6 +35,10 @@ > # SmmAccessLib|Include/Library/SmmAccessLib.h + ## @libraryclass > Provides services to trigger SMI+ #+ > SmmControlLib|Include/Library/SmmControlLib.h+ ## @libraryclass Provides > services to access config block # > ConfigBlockLib|Include/Library/ConfigBlockLib.hdiff --git > a/Silicon/Intel/KabylakeSiliconPkg/Library/BaseIntelCompatShimLibKbl/BaseIntelCompatShimLibKbl.c > b/Silicon/Intel/KabylakeSiliconPkg/Library/BaseIntelCompatShimLibKbl/BaseIntelCompatShimLibKbl.c > new file mode 100644 > index 000000000000..573f67555aa3 > --- /dev/null > +++ b/Silicon/Intel/KabylakeSiliconPkg/Library/BaseIntelCompatShimLibKbl > +++ /BaseIntelCompatShimLibKbl.c > @@ -0,0 +1,29 @@ > +/** @file > + A Kabylake compatibility shim > + > + Copyright (c) 2022, Baruch Binyamin Doron
> + SPDX-License-Identifier: BSD-2-Clause-Patent > + > +**/ > + > +#include > +#include > + > +/** > + Get PCH ACPI base address. > + > + @retval Address Address of PWRM base address. > +**/ > +UINT16 > +EFIAPI > +CompatShimGetAcpiBase ( > + VOID > + ) > +{ > + UINT16 Address; > + > + Address = 0; > + PchAcpiBaseGet (&Address); > + > + return Address; > +} > diff --git > a/Silicon/Intel/KabylakeSiliconPkg/Library/BaseIntelCompatShimLibKbl/BaseIntelCompatShimLibKbl.inf > b/Silicon/Intel/KabylakeSiliconPkg/Library/BaseIntelCompatShimLibKbl/BaseIntelCompatShimLibKbl.inf > new file mode 100644 > index 000000000000..af3e5a4726e6 > --- /dev/null > +++ b/Silicon/Intel/KabylakeSiliconPkg/Library/BaseIntelCompatShimLibKbl > +++ /BaseIntelCompatShimLibKbl.inf > @@ -0,0 +1,24 @@ > +## @file > +# Library description file for the Kabylake compatibility shim # # > +Copyright (c) 2022, Baruch Binyamin Doron
# > +SPDX-License-Identifier: BSD-2-Clause-Patent # ## > + > +[Defines] > +INF_VERSION = 0x00010017 > +BASE_NAME = BaseIntelCompatShimLibKbl > +FILE_GUID = B4A2193E-CF3E-46E6-8617-49E48143B5AB > +VERSION_STRING = 1.0 > +MODULE_TYPE = BASE > +LIBRARY_CLASS = IntelCompatShimLib > + > +[LibraryClasses] > +PchCycleDecodingLib > + > +[Packages] > +KabylakeSiliconPkg/SiPkg.dec > + > +[Sources] > +BaseIntelCompatShimLibKbl.c > -- > 2.37.2 > > > > -=-=-=-=-=-= > Groups.io Links: You receive all messages sent to this group. > View/Reply Online (#92921): https://edk2.groups.io/g/devel/message/92921 > Mute This Topic: https://groups.io/mt/93335519/1492418 > Group Owner: devel+owner@edk2.groups.io > Unsubscribe: https://edk2.groups.io/g/devel/unsub [isaac.w.oram@intel.com] > -=-=-=-=-=-= > > > --000000000000e7405605e76adea3 Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable
Right, but Kabylake has a different implementation that re= trieves it from HW registers - PchAcpiBaseGet(). This is probably optional,= there is a PCD, but it's in a different package scope. I don't kno= w how to handle the Packages in the INF to keep this silicon package agnost= ic. For that matter, it might not really be a CFL plus shim, because= Tigerlake, etc are different package DECs too.
=
<= br>
Best regards,
Benjamin

<= /div>

On Mon, 29 Aug 2022 at 19:17, Oram, Isaac W <isaac.w.oram@intel.com> wrote:=
I think that th= e shim lib might be overkill.=C2=A0 PmcGetAcpiBase just resolves to PcdGet1= 6 (PcdAcpiBaseAddress);
I think that you should be able to use that PCD for any Intel chipset/silic= on for the foreseeable future.

I would prefer to see contents of sections in INF files indented, but it is= a nit.

Regards,
Isaac

-----Original Message-----
From: devel@edk2.= groups.io <devel@edk2.groups.io> On Behalf Of Benjamin Doron
Sent: Monday, August 29, 2022 1:36 PM
To: devel@edk2.gr= oups.io
Cc: Desimone, Nathaniel L <nathaniel.l.desimone@intel.com>; Sinha, Ankit= <ankit.sinha= @intel.com>; Ni, Ray <ray.ni@intel.com>; Chaganty, Rangasai V <rangasai.v.chaganty@= intel.com>; Oram, Isaac W <isaac.w.oram@intel.com>
Subject: [edk2-devel][edk2-platforms][PATCH v1 2/5] Silicon/Intel: Port Smm= Control protocol to PPI for S3

S3 resume may require communication with SMM, for which we need the SmmCont= rol PPI. Therefore, port the DXE drivers to a library, like there is for SM= M Access.

As the registers are common across Intel platforms in the tree, while a hel= per function definition is not, implement a new library as a compatibility = shim.

Tested, working on Kabylake. Further testing required after the refactor fo= r compatibility.

Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Ankit Sinha <ankit.sinha@intel.com>
Cc: Ray Ni <ray.ni= @intel.com>
Cc: Rangasai V Chaganty <rangasai.v.chaganty@intel.com>
Cc: Isaac Oram <isaac.w.oram@intel.com>
Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com>
---
=C2=A0.../BaseIntelCompatShimLibCfl.c=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0|=C2=A0 24 ++
=C2=A0.../BaseIntelCompatShimLibCfl.inf=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0|=C2=A0 24 ++
=C2=A0.../PeiSmmControlLib/PeiSmmControlLib.c=C2=A0 =C2=A0 =C2=A0 =C2=A0| 3= 09 ++++++++++++++++++
=C2=A0.../PeiSmmControlLib/PeiSmmControlLib.inf=C2=A0 =C2=A0 =C2=A0|=C2=A0 = 36 ++
=C2=A0.../Include/Library/IntelCompatShimLib.h=C2=A0 =C2=A0 =C2=A0 |=C2=A0 = 20 ++
=C2=A0.../Include/Library/SmmControlLib.h=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0|=C2=A0 26 ++
=C2=A0.../Intel/IntelSiliconPkg/IntelSiliconPkg.dec |=C2=A0 =C2=A04 +
=C2=A0.../BaseIntelCompatShimLibKbl.c=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0|=C2=A0 29 ++
=C2=A0.../BaseIntelCompatShimLibKbl.inf=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0|=C2=A0 24 ++
=C2=A09 files changed, 496 insertions(+)
=C2=A0create mode 100644 Silicon/Intel/CoffeelakeSiliconPkg/Library/BaseInt= elCompatShimLibCfl/BaseIntelCompatShimLibCfl.c
=C2=A0create mode 100644 Silicon/Intel/CoffeelakeSiliconPkg/Library/BaseInt= elCompatShimLibCfl/BaseIntelCompatShimLibCfl.inf
=C2=A0create mode 100644 Silicon/Intel/IntelSiliconPkg/Feature/SmmControl/L= ibrary/PeiSmmControlLib/PeiSmmControlLib.c
=C2=A0create mode 100644 Silicon/Intel/IntelSiliconPkg/Feature/SmmControl/L= ibrary/PeiSmmControlLib/PeiSmmControlLib.inf
=C2=A0create mode 100644 Silicon/Intel/IntelSiliconPkg/Include/Library/Inte= lCompatShimLib.h
=C2=A0create mode 100644 Silicon/Intel/IntelSiliconPkg/Include/Library/SmmC= ontrolLib.h
=C2=A0create mode 100644 Silicon/Intel/KabylakeSiliconPkg/Library/BaseIntel= CompatShimLibKbl/BaseIntelCompatShimLibKbl.c
=C2=A0create mode 100644 Silicon/Intel/KabylakeSiliconPkg/Library/BaseIntel= CompatShimLibKbl/BaseIntelCompatShimLibKbl.inf

diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Library/BaseIntelCompatShim= LibCfl/BaseIntelCompatShimLibCfl.c b/Silicon/Intel/CoffeelakeSiliconPkg/Lib= rary/BaseIntelCompatShimLibCfl/BaseIntelCompatShimLibCfl.c
new file mode 100644
index 000000000000..5353126267e6
--- /dev/null
+++ b/Silicon/Intel/CoffeelakeSiliconPkg/Library/BaseIntelCompatShimLibC +++ fl/BaseIntelCompatShimLibCfl.c
@@ -0,0 +1,24 @@
+/** @file
+=C2=A0 A Coffeelake+ compatibility shim
+
+=C2=A0 Copyright (c) 2022, Baruch Binyamin Doron<BR>
+=C2=A0 SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Uefi.h>
+#include <Library/PmcLib.h>
+
+/**
+=C2=A0 Get PCH ACPI base address.
+
+=C2=A0 @retval Address=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0Address of PWRM base address.
+**/
+UINT16
+EFIAPI
+CompatShimGetAcpiBase (
+=C2=A0 VOID
+=C2=A0 )
+{
+=C2=A0 return PmcGetAcpiBase ();
+}
diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Library/BaseIntelCompatShim= LibCfl/BaseIntelCompatShimLibCfl.inf b/Silicon/Intel/CoffeelakeSiliconPkg/L= ibrary/BaseIntelCompatShimLibCfl/BaseIntelCompatShimLibCfl.inf
new file mode 100644
index 000000000000..48b071ed05ae
--- /dev/null
+++ b/Silicon/Intel/CoffeelakeSiliconPkg/Library/BaseIntelCompatShimLibC +++ fl/BaseIntelCompatShimLibCfl.inf
@@ -0,0 +1,24 @@
+## @file
+# Library description file for the Coffeelake+ compatibility shim # #
+Copyright (c) 2022, Baruch Binyamin Doron<BR> #
+SPDX-License-Identifier: BSD-2-Clause-Patent # ##
+
+[Defines]
+INF_VERSION =3D 0x00010017
+BASE_NAME =3D BaseIntelCompatShimLibCfl
+FILE_GUID =3D 3D0BB32E-D328-4615-ADFC-782CECC68D53
+VERSION_STRING =3D 1.0
+MODULE_TYPE =3D BASE
+LIBRARY_CLASS =3D IntelCompatShimLib
+
+[LibraryClasses]
+PmcLib
+
+[Packages]
+CoffeelakeSiliconPkg/SiPkg.dec
+
+[Sources]
+BaseIntelCompatShimLibCfl.c
diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/SmmControl/Library/PeiSm= mControlLib/PeiSmmControlLib.c b/Silicon/Intel/IntelSiliconPkg/Feature/SmmC= ontrol/Library/PeiSmmControlLib/PeiSmmControlLib.c
new file mode 100644
index 000000000000..80c2c1be90b1
--- /dev/null
+++ b/Silicon/Intel/IntelSiliconPkg/Feature/SmmControl/Library/PeiSmmCon +++ trolLib/PeiSmmControlLib.c
@@ -0,0 +1,309 @@
+/** @file+=C2=A0 This is to publish the SMM Control Ppi instance.++=C2=A0 = Copyright (c) 2019 - 2020, Intel Corporation. All rights reserved.<BR>= ;+=C2=A0 SPDX-License-Identifier: BSD-2-Clause-Patent++**/+#include <Uef= i/UefiBaseType.h>+#include <Library/DebugLib.h>+#include <Libra= ry/IntelCompatShimLib.h>+#include <Library/IoLib.h>+#include <L= ibrary/MemoryAllocationLib.h>+#include <Library/PeiServicesLib.h>+= +#include <Ppi/MmControl.h>+#include <IndustryStandard/Pci30.h>= ++#define SMM_CONTROL_PRIVATE_DATA_SIGNATURE=C2=A0 SIGNATURE_32 ('i'= ;, '4', 's', 'c')++typedef struct {+=C2=A0 UINTN=C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0Signature;+=C2=A0 EFI_HANDLE=C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 Handle;+=C2=A0 EFI_PEI_MM= _CONTROL_PPI=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 SmmControl;+} SMM_CONTROL_PR= IVATE_DATA;++#define SMM_CONTROL_PRIVATE_DATA_FROM_THIS(a) \+=C2=A0 =C2=A0 = =C2=A0 =C2=A0 CR (a, \+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 SMM_CONTROL_PRIVA= TE_DATA, \+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 SmmControl, \+=C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 SMM_CONTROL_DEV_SIGNATURE \+=C2=A0 =C2=A0 =C2=A0 )++//= +// Common registers:+//+//+// APM Registers+//+#define R_PCH_APM_CNT=C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A00xB2+//+// ACPI and legacy I/O register offsets fro= m ACPIBASE+//+#define R_PCH_ACPI_PM1_STS=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 0x00+#define B_PCH_ACPI_PM= 1_STS_PRBTNOR=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 BIT11+= +#define R_PCH_SMI_EN=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 0x30++#define R_PCH_SM= I_STS=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A00x34+#define B_PCH_SMI_STS_APM=C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0BIT5+#define B_PCH_SMI_EN_APMC=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0BIT5+#define B_PCH_SMI_= EN_EOS=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 BIT1+#define B_PCH_SMI_EN_GBL_SMI=C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 BIT0++/**+=C2=A0 T= rigger the software SMI++=C2=A0 @param[in] Data=C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0The value to be set on the software SMI d= ata port++=C2=A0 @retval EFI_SUCCESS=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0Function completes successfully+**/+EFI_STATUS+EFIAPI+SmmTrigger = (+=C2=A0 UINT8=C2=A0 =C2=A0Data+=C2=A0 )+{+=C2=A0 UINT16=C2=A0 ABase;+=C2= =A0 UINT32=C2=A0 OutputData;+=C2=A0 UINT32=C2=A0 OutputPort;++=C2=A0 ABase = =3D CompatShimGetAcpiBase ();++=C2=A0 ///+=C2=A0 /// Enable the APMC SMI+= =C2=A0 ///+=C2=A0 OutputPort=C2=A0 =3D ABase + R_PCH_SMI_EN;+=C2=A0 OutputD= ata=C2=A0 =3D IoRead32 ((UINTN) OutputPort);+=C2=A0 OutputData |=3D (B_PCH_= SMI_EN_APMC | B_PCH_SMI_EN_GBL_SMI);+=C2=A0 DEBUG (+=C2=A0 =C2=A0 (DEBUG_EV= ENT,+=C2=A0 =C2=A0 =C2=A0"The SMI Control Port at address %x will be w= ritten to %x.\n",+=C2=A0 =C2=A0 =C2=A0OutputPort,+=C2=A0 =C2=A0 =C2=A0= OutputData)+=C2=A0 =C2=A0 );+=C2=A0 IoWrite32 (+=C2=A0 =C2=A0 (UINTN) Outpu= tPort,+=C2=A0 =C2=A0 (UINT32) (OutputData)+=C2=A0 =C2=A0 );++=C2=A0 OutputP= ort=C2=A0 =3D R_PCH_APM_CNT;+=C2=A0 OutputData=C2=A0 =3D Data;++=C2=A0 ///+= =C2=A0 /// Generate the APMC SMI+=C2=A0 ///+=C2=A0 IoWrite8 (+=C2=A0 =C2=A0= (UINTN) OutputPort,+=C2=A0 =C2=A0 (UINT8) (OutputData)+=C2=A0 =C2=A0 );++= =C2=A0 return EFI_SUCCESS;+}++/**+=C2=A0 Clear the SMI status+++=C2=A0 @ret= val EFI_SUCCESS=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0The function= completes successfully+=C2=A0 @retval EFI_DEVICE_ERROR=C2=A0 =C2=A0 =C2=A0= =C2=A0 Something error occurred+**/+EFI_STATUS+EFIAPI+SmmClear (+=C2=A0 VO= ID+=C2=A0 )+{+=C2=A0 UINT16=C2=A0 ABase;+=C2=A0 UINT32=C2=A0 OutputData;+= =C2=A0 UINT32=C2=A0 OutputPort;++=C2=A0 ABase =3D CompatShimGetAcpiBase ();= ++=C2=A0 ///+=C2=A0 /// Clear the Power Button Override Status Bit, it gate= s EOS from being set.+=C2=A0 ///+=C2=A0 OutputPort=C2=A0 =3D ABase + R_PCH_= ACPI_PM1_STS;+=C2=A0 OutputData=C2=A0 =3D B_PCH_ACPI_PM1_STS_PRBTNOR;+=C2= =A0 DEBUG (+=C2=A0 =C2=A0 (DEBUG_EVENT,+=C2=A0 =C2=A0 =C2=A0"The PM1 S= tatus Port at address %x will be written to %x.\n",+=C2=A0 =C2=A0 =C2= =A0OutputPort,+=C2=A0 =C2=A0 =C2=A0OutputData)+=C2=A0 =C2=A0 );+=C2=A0 IoWr= ite16 (+=C2=A0 =C2=A0 (UINTN) OutputPort,+=C2=A0 =C2=A0 (UINT16) (OutputDat= a)+=C2=A0 =C2=A0 );++=C2=A0 ///+=C2=A0 /// Clear the APM SMI Status Bit+=C2= =A0 ///+=C2=A0 OutputPort=C2=A0 =3D ABase + R_PCH_SMI_STS;+=C2=A0 OutputDat= a=C2=A0 =3D B_PCH_SMI_STS_APM;+=C2=A0 DEBUG (+=C2=A0 =C2=A0 (DEBUG_EVENT,+= =C2=A0 =C2=A0 =C2=A0"The SMI Status Port at address %x will be written= to %x.\n",+=C2=A0 =C2=A0 =C2=A0OutputPort,+=C2=A0 =C2=A0 =C2=A0Output= Data)+=C2=A0 =C2=A0 );+=C2=A0 IoWrite32 (+=C2=A0 =C2=A0 (UINTN) OutputPort,= +=C2=A0 =C2=A0 (UINT32) (OutputData)+=C2=A0 =C2=A0 );++=C2=A0 ///+=C2=A0 //= / Set the EOS Bit+=C2=A0 ///+=C2=A0 OutputPort=C2=A0 =3D ABase + R_PCH_SMI_= EN;+=C2=A0 OutputData=C2=A0 =3D IoRead32 ((UINTN) OutputPort);+=C2=A0 Outpu= tData |=3D B_PCH_SMI_EN_EOS;+=C2=A0 DEBUG (+=C2=A0 =C2=A0 (DEBUG_EVENT,+=C2= =A0 =C2=A0 =C2=A0"The SMI Control Port at address %x will be written t= o %x.\n",+=C2=A0 =C2=A0 =C2=A0OutputPort,+=C2=A0 =C2=A0 =C2=A0OutputDa= ta)+=C2=A0 =C2=A0 );+=C2=A0 IoWrite32 (+=C2=A0 =C2=A0 (UINTN) OutputPort,+= =C2=A0 =C2=A0 (UINT32) (OutputData)+=C2=A0 =C2=A0 );++=C2=A0 ///+=C2=A0 ///= There is no need to read EOS back and check if it is set.+=C2=A0 /// This = can lead to a reading of zero if an SMI occurs right after the SMI_EN port = read+=C2=A0 /// but before the data is returned to the CPU.+=C2=A0 /// SMM = Dispatcher should make sure that EOS is set after all SMI sources are proce= ssed.+=C2=A0 ///+=C2=A0 return EFI_SUCCESS;+}++/**+=C2=A0 This routine gene= rates an SMI++=C2=A0 @param[in] This=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0The EFI SMM Control protocol i= nstance+=C2=A0 @param[in, out] ArgumentBuffer=C2=A0 =C2=A0 =C2=A0 =C2=A0 Th= e buffer of argument+=C2=A0 @param[in, out] ArgumentBufferSize=C2=A0 =C2=A0= The size of the argument buffer+=C2=A0 @param[in] Periodic=C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0Periodic or not+=C2= =A0 @param[in] ActivationInterval=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0Interval= of periodic SMI++=C2=A0 @retval EFI Status=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 Describing the result of the operati= on+=C2=A0 @retval EFI_INVALID_PARAMETER=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0So= me parameter value passed is not supported+**/+EFI_STATUS+EFIAPI+Activate (= +=C2=A0 IN EFI_PEI_SERVICES=C2=A0 =C2=A0 =C2=A0 =C2=A0 **PeiServices,+=C2= =A0 IN EFI_PEI_MM_CONTROL_PPI=C2=A0 * This,+=C2=A0 IN OUT INT8=C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 *ArgumentBuffer OPTIONAL,+=C2=A0= IN OUT UINTN=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0*Argume= ntBufferSize OPTIONAL,+=C2=A0 IN BOOLEAN=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0Periodic OPTIONAL,+=C2=A0 IN UINTN=C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0ActivationInterval O= PTIONAL+=C2=A0 )+{+=C2=A0 EFI_STATUS=C2=A0 Status;+=C2=A0 UINT8=C2=A0 =C2= =A0 =C2=A0 =C2=A0Data;++=C2=A0 if (Periodic) {+=C2=A0 =C2=A0 DEBUG ((DEBUG_= WARN, "Invalid parameter\n"));+=C2=A0 =C2=A0 return EFI_INVALID_P= ARAMETER;+=C2=A0 }++=C2=A0 // NOTE: Copied from Quark. Matches the usage in= PiSmmCommunicationPei+=C2=A0 if (ArgumentBuffer =3D=3D NULL) {+=C2=A0 =C2= =A0 Data =3D 0xFF;+=C2=A0 } else {+=C2=A0 =C2=A0 if (ArgumentBufferSize =3D= =3D NULL || *ArgumentBufferSize !=3D 1) {+=C2=A0 =C2=A0 =C2=A0 return EFI_I= NVALID_PARAMETER;+=C2=A0 =C2=A0 }++=C2=A0 =C2=A0 Data =3D *ArgumentBuffer;+= =C2=A0 }+=C2=A0 ///+=C2=A0 /// Clear any pending the APM SMI+=C2=A0 ///+=C2= =A0 Status =3D SmmClear ();+=C2=A0 if (EFI_ERROR (Status)) {+=C2=A0 =C2=A0 = return Status;+=C2=A0 }++=C2=A0 return SmmTrigger (Data);+}++/**+=C2=A0 Thi= s routine clears an SMI++=C2=A0 @param[in] This=C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0The EFI SMM Control protocol instance+=C2= =A0 @param[in] Periodic=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0Peri= odic or not++=C2=A0 @retval EFI Status=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 Describing the result of the operation+=C2=A0 @retval EFI_INV= ALID_PARAMETER=C2=A0 =C2=A0Some parameter value passed is not supported+**/= +EFI_STATUS+EFIAPI+Deactivate (+=C2=A0 IN EFI_PEI_SERVICES=C2=A0 =C2=A0 =C2= =A0 =C2=A0 **PeiServices,+=C2=A0 IN EFI_PEI_MM_CONTROL_PPI=C2=A0 * This,+= =C2=A0 IN BOOLEAN=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0Periodic OPTIONAL+=C2=A0 )+{+=C2=A0 if (Periodic) {+=C2=A0 =C2=A0 ret= urn EFI_INVALID_PARAMETER;+=C2=A0 }++=C2=A0 return SmmClear ();+}++/**+=C2= =A0 This function is to install an SMM Control PPI+=C2=A0 - <b>Introd= uction</b> \n+=C2=A0 =C2=A0 An API to install an instance of EFI_PEI_= MM_CONTROL_PPI. This PPI provides a standard+=C2=A0 =C2=A0 way for other mo= dules to trigger software SMIs.++=C2=A0 =C2=A0 @retval EFI_SUCCESS=C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0- Ppi successfully started and installed.= +=C2=A0 =C2=A0 @retval EFI_NOT_FOUND=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0- Ppi= can't be found.+=C2=A0 =C2=A0 @retval EFI_OUT_OF_RESOURCES=C2=A0 - Ppi= does not have enough resources to initialize the driver.+**/+EFI_STATUS+EF= IAPI+PeiInstallSmmControlPpi (+=C2=A0 VOID+=C2=A0 )+{+=C2=A0 EFI_STATUS=C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 S= tatus;+=C2=A0 EFI_PEI_PPI_DESCRIPTOR=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 *Ppi= List;+=C2=A0 SMM_CONTROL_PRIVATE_DATA=C2=A0 =C2=A0 =C2=A0 =C2=A0 *SmmContro= lPrivate;++=C2=A0 //+=C2=A0 // Initialize private data+=C2=A0 //+=C2=A0 Smm= ControlPrivate=C2=A0 =3D AllocateZeroPool (sizeof (*SmmControlPrivate));+= =C2=A0 ASSERT (SmmControlPrivate !=3D NULL);+=C2=A0 if (SmmControlPrivate = =3D=3D NULL) {+=C2=A0 =C2=A0 return EFI_OUT_OF_RESOURCES;+=C2=A0 }+=C2=A0 P= piList=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0=3D AllocateZeroPool (sizeof= (*PpiList));+=C2=A0 ASSERT (PpiList !=3D NULL);+=C2=A0 if (PpiList =3D=3D = NULL) {+=C2=A0 =C2=A0 return EFI_OUT_OF_RESOURCES;+=C2=A0 }++=C2=A0 SmmCont= rolPrivate->Signature =3D SMM_CONTROL_PRIVATE_DATA_SIGNATURE;+=C2=A0 Smm= ControlPrivate->Handle=C2=A0 =C2=A0 =3D NULL;++=C2=A0 SmmControlPrivate-= >SmmControl.Trigger=C2=A0 =3D Activate;+=C2=A0 SmmControlPrivate->Smm= Control.Clear=C2=A0 =C2=A0 =3D Deactivate;++=C2=A0 //+=C2=A0 // Install PPI= +=C2=A0 //+=C2=A0 PpiList->Flags=C2=A0 =3D (EFI_PEI_PPI_DESCRIPTOR_PPI |= EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST);+=C2=A0 PpiList->Guid=C2=A0 =C2= =A0=3D &gEfiPeiMmControlPpiGuid;+=C2=A0 PpiList->Ppi=C2=A0 =C2=A0 = =3D &SmmControlPrivate->SmmControl;++=C2=A0 Status=C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =3D PeiServicesInstallPpi (PpiList);+=C2=A0 ASSERT_EFI_ER= ROR (Status);++=C2=A0 // Unlike driver, do not disable SMIs as S3 resume co= ntinues+=C2=A0 return EFI_SUCCESS;+}diff --git a/Silicon/Intel/IntelSilicon= Pkg/Feature/SmmControl/Library/PeiSmmControlLib/PeiSmmControlLib.inf b/Sili= con/Intel/IntelSiliconPkg/Feature/SmmControl/Library/PeiSmmControlLib/PeiSm= mControlLib.inf
new file mode 100644
index 000000000000..92f2879d82ab
--- /dev/null
+++ b/Silicon/Intel/IntelSiliconPkg/Feature/SmmControl/Library/PeiSmmCon +++ trolLib/PeiSmmControlLib.inf
@@ -0,0 +1,36 @@
+## @file+# Library description file for the SmmControl PPI+#+#
+Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>+# +SPDX-License-Identifier:
+BSD-2-Clause-Patent+#+##++[Defines]+INF_VERSION =3D 0x00010017+BASE_NAME <= br> +=3D PeiSmmControlLib+FILE_GUID =3D
+F45D521A-C0DF-4283-A3CA-65AD01B479E7+VERSION_STRING =3D 1.0+MODULE_TYPE = =3D
+PEIM+LIBRARY_CLASS =3D
+SmmControlLib+++[LibraryClasses]+IntelCompatShimLib+IoLib+DebugLib+Memo +ryAllocationLib+PeiServicesLib+++[Packages]+MdePkg/MdePkg.dec+IntelSili +conPkg/IntelSiliconPkg.dec+++[Sources]+PeiSmmControlLib.c+++[Ppis]+gEfi +PeiMmControlPpiGuid ## PRODUCESdiff --git
+a/Silicon/Intel/IntelSiliconPkg/Include/Library/IntelCompatShimLib.h
+b/Silicon/Intel/IntelSiliconPkg/Include/Library/IntelCompatShimLib.h
new file mode 100644
index 000000000000..f8621d92e41a
--- /dev/null
+++ b/Silicon/Intel/IntelSiliconPkg/Include/Library/IntelCompatShimLib.h @@ -0,0 +1,20 @@
+/** @file
+=C2=A0 Library description file for compatibility shim
+
+=C2=A0 Copyright (c) 2022, Baruch Binyamin Doron<BR>
+=C2=A0 SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Uefi.h>
+
+/**
+=C2=A0 Get PCH ACPI base address.
+
+=C2=A0 @retval Address=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0Address of PWRM base address.
+**/
+UINT16
+EFIAPI
+CompatShimGetAcpiBase (
+=C2=A0 VOID
+=C2=A0 );
diff --git a/Silicon/Intel/IntelSiliconPkg/Include/Library/SmmControlLib.h = b/Silicon/Intel/IntelSiliconPkg/Include/Library/SmmControlLib.h
new file mode 100644
index 000000000000..b532dd13f373
--- /dev/null
+++ b/Silicon/Intel/IntelSiliconPkg/Include/Library/SmmControlLib.h
@@ -0,0 +1,26 @@
+/** @file+=C2=A0 This is to publish the SMM Control Ppi instance.++=C2=A0 = Copyright (c) 2019 - 2020, Intel Corporation. All rights reserved.<BR>= ;+=C2=A0 SPDX-License-Identifier: BSD-2-Clause-Patent++**/+#ifndef _SMM_CON= TROL_LIB_H_+#define _SMM_CONTROL_LIB_H_++/**+=C2=A0 This function is to ins= tall an SMM Control PPI+=C2=A0 - <b>Introduction</b> \n+=C2=A0 = =C2=A0 An API to install an instance of EFI_PEI_MM_CONTROL_PPI. This PPI pr= ovides a standard+=C2=A0 =C2=A0 way for other modules to trigger software S= MIs.++=C2=A0 =C2=A0 @retval EFI_SUCCESS=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0- Ppi successfully started and installed.+=C2=A0 =C2=A0 @retval EFI_N= OT_FOUND=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0- Ppi can't be found.+=C2=A0 = =C2=A0 @retval EFI_OUT_OF_RESOURCES=C2=A0 - Ppi does not have enough resour= ces to initialize the driver.+**/+EFI_STATUS+EFIAPI+PeiInstallSmmControlPpi= (+=C2=A0 VOID+=C2=A0 );+#endifdiff --git a/Silicon/Intel/IntelSiliconPkg/I= ntelSiliconPkg.dec b/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec
index c36d130a0197..fc27b394d267 100644
--- a/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec
+++ b/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec
@@ -35,6 +35,10 @@
=C2=A0 =C2=A0#=C2=A0 =C2=A0SmmAccessLib|Include/Library/SmmAccessLib.h +=C2= =A0 ## @libraryclass Provides services to trigger SMI+=C2=A0 #+=C2=A0 SmmCo= ntrolLib|Include/Library/SmmControlLib.h+=C2=A0 =C2=A0## @libraryclass Prov= ides services to access config block=C2=A0 =C2=A0#=C2=A0 =C2=A0ConfigBlockL= ib|Include/Library/ConfigBlockLib.hdiff --git a/Silicon/Intel/KabylakeSilic= onPkg/Library/BaseIntelCompatShimLibKbl/BaseIntelCompatShimLibKbl.c b/Silic= on/Intel/KabylakeSiliconPkg/Library/BaseIntelCompatShimLibKbl/BaseIntelComp= atShimLibKbl.c
new file mode 100644
index 000000000000..573f67555aa3
--- /dev/null
+++ b/Silicon/Intel/KabylakeSiliconPkg/Library/BaseIntelCompatShimLibKbl +++ /BaseIntelCompatShimLibKbl.c
@@ -0,0 +1,29 @@
+/** @file
+=C2=A0 A Kabylake compatibility shim
+
+=C2=A0 Copyright (c) 2022, Baruch Binyamin Doron<BR>
+=C2=A0 SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Uefi.h>
+#include <Library/PchCycleDecodingLib.h>
+
+/**
+=C2=A0 Get PCH ACPI base address.
+
+=C2=A0 @retval Address=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0Address of PWRM base address.
+**/
+UINT16
+EFIAPI
+CompatShimGetAcpiBase (
+=C2=A0 VOID
+=C2=A0 )
+{
+=C2=A0 UINT16=C2=A0 Address;
+
+=C2=A0 Address =3D 0;
+=C2=A0 PchAcpiBaseGet (&Address);
+
+=C2=A0 return Address;
+}
diff --git a/Silicon/Intel/KabylakeSiliconPkg/Library/BaseIntelCompatShimLi= bKbl/BaseIntelCompatShimLibKbl.inf b/Silicon/Intel/KabylakeSiliconPkg/Libra= ry/BaseIntelCompatShimLibKbl/BaseIntelCompatShimLibKbl.inf
new file mode 100644
index 000000000000..af3e5a4726e6
--- /dev/null
+++ b/Silicon/Intel/KabylakeSiliconPkg/Library/BaseIntelCompatShimLibKbl +++ /BaseIntelCompatShimLibKbl.inf
@@ -0,0 +1,24 @@
+## @file
+# Library description file for the Kabylake compatibility shim # #
+Copyright (c) 2022, Baruch Binyamin Doron<BR> #
+SPDX-License-Identifier: BSD-2-Clause-Patent # ##
+
+[Defines]
+INF_VERSION =3D 0x00010017
+BASE_NAME =3D BaseIntelCompatShimLibKbl
+FILE_GUID =3D B4A2193E-CF3E-46E6-8617-49E48143B5AB
+VERSION_STRING =3D 1.0
+MODULE_TYPE =3D BASE
+LIBRARY_CLASS =3D IntelCompatShimLib
+
+[LibraryClasses]
+PchCycleDecodingLib
+
+[Packages]
+KabylakeSiliconPkg/SiPkg.dec
+
+[Sources]
+BaseIntelCompatShimLibKbl.c
--
2.37.2



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