From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=209.85.128.67; helo=mail-wm1-f67.google.com; envelope-from=pmathieu@redhat.com; receiver=edk2-devel@lists.01.org Received: from mail-wm1-f67.google.com (mail-wm1-f67.google.com [209.85.128.67]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id E726221184AC5 for ; Mon, 26 Nov 2018 15:02:45 -0800 (PST) Received: by mail-wm1-f67.google.com with SMTP id 79so279540wmo.0 for ; Mon, 26 Nov 2018 15:02:45 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc:content-transfer-encoding; bh=asOBIJDXzHxHqRmioN4eHHQRqruHIf4I/en7uBUwBCo=; b=AsvOEBE/4H0Cw+EQHEj9/TiS6jKUjuC3tGEgFYHDhZ9h+1JNMGIy6s0Q3WFtg5Fi3n dfHiGp8Dhzt6GjgxOBxcduZGS7knNW+eHPhGdLgHpTSerW0YMgYMolhi4n1T9Ymo0H2A 2iJ/V5PXNOaXzzaWJoYQnoPzOfPlMiK4Dqr7nI0zVrZPBacu46LwJkc5JeBM+xF85/aP Pc66yE/2a7TEA4FZylSMzZfRQcKPubCVgTdpXbuJiIF8ir4+xLms7AXmcJd6n3TKmX5c UyYMnXAzQrFF+ppLo2mK3dfbLQiH1Wzxk+YPRzW8fGbNpSa3kxySyEq0bmqcJH0WhF4d J/Lw== X-Gm-Message-State: AA+aEWb/tWJrRX0lBgN9nwT/+j5dVcQJrawG4a88EoEG4tL37iiwZQuB 8dzMEfIUTnOBX/T84AWGsqk8LPq6+AufU6UthYA+BQ== X-Google-Smtp-Source: AJdET5fcyKWCrtqEMXtQlhGcaIT3n0brJfp4JK7bhsuszMCaluA7y1GpkqgjG4QUcl5/RlIEe/ngwnlkJwDDFfglvHA= X-Received: by 2002:a1c:1dce:: with SMTP id d197mr26677269wmd.66.1543273364426; Mon, 26 Nov 2018 15:02:44 -0800 (PST) MIME-Version: 1.0 References: <20181126223801.17121-1-ard.biesheuvel@linaro.org> <20181126223801.17121-2-ard.biesheuvel@linaro.org> In-Reply-To: From: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Date: Tue, 27 Nov 2018 00:02:32 +0100 Message-ID: To: Ard Biesheuvel , edk2-devel-01 Cc: Laszlo Ersek , Leif Lindholm , Auger Eric , Andrew Jones , Julien Grall Subject: Re: [PATCH v2 01/13] ArmPkg/ArmLib: add support for reading the max physical address space size X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 26 Nov 2018 23:02:46 -0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Mon, Nov 26, 2018 at 11:43 PM Philippe Mathieu-Daud=C3=A9 wrote: > > On 26/11/18 23:37, Ard Biesheuvel wrote: > > Add a helper function that returns the maximum physical address space > > size as supported by the current CPU. > > > > Contributed-under: TianoCore Contribution Agreement 1.1 > > Signed-off-by: Ard Biesheuvel > > Reviewed-by: Philippe Mathieu-Daud=C3=A9 > > > --- > > ArmPkg/Include/Library/ArmLib.h | 17 +++++++++++++++++ > > ArmPkg/Library/ArmLib/AArch64/ArmLibSupport.S | 16 ++++++++++++++++ > > ArmPkg/Library/ArmLib/Arm/ArmLibSupport.S | 8 ++++++++ > > 3 files changed, 41 insertions(+) > > > > diff --git a/ArmPkg/Include/Library/ArmLib.h b/ArmPkg/Include/Library/A= rmLib.h > > index ffda50e9d767..b22879fe6e94 100644 > > --- a/ArmPkg/Include/Library/ArmLib.h > > +++ b/ArmPkg/Include/Library/ArmLib.h > > @@ -29,6 +29,17 @@ > > #define EFI_MEMORY_CACHETYPE_MASK (EFI_MEMORY_UC | EFI_MEMORY_WC | \ > > EFI_MEMORY_WT | EFI_MEMORY_WB | \ > > EFI_MEMORY_UCE) > > +// > > +// ARM_MMU_IDMAP_RANGE defines the maximum size of the identity mappin= g > > +// that covers the entire address space when running in UEFI. This is > > +// limited to what can architecturally be mapped using a 4 KB granule, > > +// even if the hardware is capable of mapping more using larger pages. > > +// > > +#ifdef MDE_CPU_ARM > > +#define ARM_MMU_IDMAP_RANGE (1ULL << 32) > > +#else > > +#define ARM_MMU_IDMAP_RANGE (1ULL << 48) > > +#endif > > > > /** > > * The UEFI firmware must not use the ARM_MEMORY_REGION_ATTRIBUTE_NONS= ECURE_* attributes. > > @@ -733,4 +744,10 @@ ArmWriteCntvOff ( > > UINT64 Val > > ); > > > > +UINTN > > +EFIAPI > > +ArmGetPhysicalAddressBits ( > > + VOID > > + ); > > + > > #endif // __ARM_LIB__ > > diff --git a/ArmPkg/Library/ArmLib/AArch64/ArmLibSupport.S b/ArmPkg/Lib= rary/ArmLib/AArch64/ArmLibSupport.S > > index 1ef2f61f5979..7332601241aa 100644 > > --- a/ArmPkg/Library/ArmLib/AArch64/ArmLibSupport.S > > +++ b/ArmPkg/Library/ArmLib/AArch64/ArmLibSupport.S > > @@ -196,4 +196,20 @@ ASM_FUNC(ArmWriteSctlr) > > 3:msr sctlr_el3, x0 > > 4:ret > > > > +ASM_FUNC(ArmGetPhysicalAddressBits) > > + mrs x0, id_aa64mmfr0_el1 > > + adr x1, .LPARanges > > + and x0, x0, #7 > > + ldrb w0, [x1, x0] > > + ret > > + > > +// > > +// Bits 0..2 of the AA64MFR0_EL1 system register encode the size of th= e > > +// physical address space support on this CPU: > > +// 0 =3D=3D 32 bits, 1 =3D=3D 36 bits, etc etc > > +// 6 and 7 are reserved Oops the comment is now invalid for the index =3D=3D 6. > > +// > > +.LPARanges: > > + .byte 32, 36, 40, 42, 44, 48, 52, -1 > > + > > ASM_FUNCTION_REMOVE_IF_UNREFERENCED > > diff --git a/ArmPkg/Library/ArmLib/Arm/ArmLibSupport.S b/ArmPkg/Library= /ArmLib/Arm/ArmLibSupport.S > > index f2a517671f0a..f2f3c9a25991 100644 > > --- a/ArmPkg/Library/ArmLib/Arm/ArmLibSupport.S > > +++ b/ArmPkg/Library/ArmLib/Arm/ArmLibSupport.S > > @@ -165,4 +165,12 @@ ASM_FUNC(ArmWriteCpuActlr) > > isb > > bx lr > > > > +ASM_FUNC (ArmGetPhysicalAddressBits) > > + mrc p15, 0, r0, c0, c1, 4 // MMFR0 > > + and r0, r0, #0xf // VMSA [3:0] > > + cmp r0, #5 // >5 implies LPAE support > > + movlt r0, #32 // 32 bits if no LPAE > > + movge r0, #40 // 40 bits if LPAE > > + bx lr > > + > > ASM_FUNCTION_REMOVE_IF_UNREFERENCED > >