From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-lf0-x243.google.com (mail-lf0-x243.google.com [IPv6:2a00:1450:4010:c07::243]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 9437082134 for ; Fri, 17 Feb 2017 09:30:52 -0800 (PST) Received: by mail-lf0-x243.google.com with SMTP id q89so4326987lfi.1 for ; Fri, 17 Feb 2017 09:30:52 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc:content-transfer-encoding; bh=v8JpVRYYIJLYRKrNxwuB7mh4XD+0AcsCu0flbZmKbpA=; b=sP9+V8Mk90M5xRNthRGlxfSjOuMuvtbPLGeTpXF7dsBXFi4sZKMaVk5NaQ6lk/zlEm DXTnHr/1nFnXhI/IA43I5xCJ/DrASV2jHSJ13gfn5WYGNOfzkkmYLFbmiDuaZEHnH4s9 kJFKwwFFiG/eEYoNWGeEienrq0ifcMtEvmcMmLZKoZ4YF0LoiDvy1125GCJPBddcjv/a tgnmqtqCw1Sv+xVZNixcu9jKxwbAy0WSBezr0epgcx0ZFeZ5R5H9Wm8Zff+5B+rbv4hX xkQiX92f7b6JdGIfoJW0yTnJvPUQu8ZcC1fxWCECGHsiiJWD5Ee1FwmUss6vU7p4LSC6 hDGw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc:content-transfer-encoding; bh=v8JpVRYYIJLYRKrNxwuB7mh4XD+0AcsCu0flbZmKbpA=; b=TfgdgCdpaQm1Aj2lcCUQA0wTodNIlQu36M4EKw1ibVT2Avl5tOBjvUkdBBG59TyyHm yCZmxXrIl9/gvhTfqlGzc08UXzFQSs2Faj7lfwbNR0rh53M07k2N12dXMSw+0eJJGIM3 fG8SVIvl0uIOGRDQbYOGWOvr+/m+VztRMRlC+x3tIxm1KrIS2/dXiq5rFou/+xvW3XB2 QuNSGDc42+RuhEqagELpPqV2+Vs8fP3O002O7cbjq3STGPnhrO6NfRvpkRO1C25QeWok mcdsD9M2KTANgZPugxUnWZP/DW0+sfu/ezQ1YUut66hERYEwwQXUYvSlvKCptUdcLkhi w4bQ== X-Gm-Message-State: AMke39mc1h0fJ7SY57j2cb8f7qgmAWS1zXO2+uiw7SJGPBSqh+osUqrn7bAXoSsSX0QFjwj/zmjRTuQPiGxExg== X-Received: by 10.46.84.78 with SMTP id y14mr2366899ljd.63.1487352650735; Fri, 17 Feb 2017 09:30:50 -0800 (PST) MIME-Version: 1.0 Received: by 10.25.20.169 with HTTP; Fri, 17 Feb 2017 09:30:50 -0800 (PST) In-Reply-To: References: From: Arka Sharma Date: Fri, 17 Feb 2017 23:00:50 +0530 Message-ID: To: Andrew Fish Cc: edk2-devel@lists.01.org Subject: Re: Mapping of PrpList in NvmExpressDxe X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 17 Feb 2017 17:30:53 -0000 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Thanks Andrew for your response. Actually my question related to EfiPciOperationBusMasterCommonBuffer was only in case of PrpList buffer which is allocated and mapped in NvmeCreatePrpList function. In case of queues the mapping with EfiPciOperationBusMasterCommonBuffer is understood as in case of Completion queue the device will post the response of a command and driver will also poll the phase tag to detect a new completion entry so coherent buffer is needed. But in case of PrpList buffer such simultaneous access is not done. The host will update the prp entries and device will pick them up only after host update submission queue doorbell. So my question is in case of particularly PrpList buffer why it is mapped as EfiPciOperationBusMasterCommonBuffer, where as per my understanding EfiPciOperationBusMasterRead would have sufficed. Regards, Arka On Fri, Feb 17, 2017 at 10:13 PM, Andrew Fish wrote: > >> On Feb 17, 2017, at 5:54 AM, Arka Sharma wrote: >> >> I am wondering what is the reason for mapping the PrpList buffer with >> EfiPciIoOperationBusMasterCommonBuffer, as host will fill the Prp >> entries and after updating the submission queue doorbell device will >> start processing the command and fetch the Prp entries. So I am >> thinking the Prplist buffer could have been mapped as >> EfiPciIoOperationBusMasterRead. Is there any reason for mapping it as >> CommonBuffer that I am not able to figure out ? >> > > Arka, > > Good question. Historically there have been a lot of bugs in DMA code in = EFI. The reason being if you don't follow the rules the code still works si= nce DMA is so coherent in hardware on an x86 PC. This is not the case for a= lot of ARM platforms. > > There is a good overview of UEFI DMA operations in the UEFI Spec PCI Bus = Support Chapter. > > DMA Bus Master Read Operation > =E2=80=A2 Call Map() for EfiPciOperationBusMasterRead or EfiPciOperationB= usMasterRead64. > =E2=80=A2 Program the DMA Bus Master with the DeviceAddress returned by M= ap(). > =E2=80=A2 Start the DMA Bus Master. > =E2=80=A2 Wait for DMA Bus Master to complete the read operation. > =E2=80=A2 Call Unmap(). > > DMA Bus Master Write Operation > =E2=80=A2 Call Map() for EfiPciOperationBusMasterWrite or EfiPciOperation= BusMasterRead64. > =E2=80=A2 Program the DMA Bus Master with the DeviceAddress returned by M= ap(). > =E2=80=A2 Start the DMA Bus Master. > =E2=80=A2 Wait for DMA Bus Master to complete the write operation. > =E2=80=A2 Perform a PCI controller specific read transaction to flush all= PCI write buffers (See PCI Specification Section 3.2.5.2) . > =E2=80=A2 Call Flush(). > =E2=80=A2 Call Unmap(). > > DMA Bus Master Common Buffer Operation > =E2=80=A2 Call AllocateBuffer() to allocate a common buffer. > =E2=80=A2 Call Map() for EfiPciOperationBusMasterCommonBuffer or EfiPciOp= erationBusMasterCommonBuffer64. > =E2=80=A2 Program the DMA Bus Master with the DeviceAddress returned by M= ap(). > =E2=80=A2 The common buffer can now be accessed equally by the processor = and the DMA bus master. > =E2=80=A2 Call Unmap(). > =E2=80=A2 Call FreeBuffer(). > > So to answer your question. The Read and Write operations are one shot on= the buffer, while Common Buffer is a buffer that is DMA coherent and can b= e reused. Thats probably why Common Buffer is used by the NVMe driver. > > Basically the common usage for the Read and Write mappings are the caller= passing a buffer (like a block on the disk). The Queues that run DMA are c= ommon buffer as the PCI hardware and the CPU both need to access them inter= mittently. To be clear for the read and write case the CPU only has a coher= ent view of the buffer after the Unmap() is called. > > I think the only way you can enforce most of the UEFI driver DMA rules on= x86 is to turn on an IOMMU that would cause faults if you don't follow the= rules. Basically you have the IOMMU fault on DMA transactions to a buffer = that is not following the rules above. > > Thanks, > > Andrew Fish > >> Regards, >> Arka >> _______________________________________________ >> edk2-devel mailing list >> edk2-devel@lists.01.org >> https://lists.01.org/mailman/listinfo/edk2-devel >