Re: [PATCH v2 2/4] MdeModulePkg/SdMmcPciHcDxe: Add UhsSignaling to SdMmcOverride protocol

[Marcin Wojtas <mw@semihalf.com>]

wt., 9 paź 2018 o 13:51 Marcin Wojtas <mw@semihalf.com> napisał(a):
>
> wt., 9 paź 2018 o 13:45 Ard Biesheuvel <ard.biesheuvel@linaro.org> napisał(a):
> >
> > On 9 October 2018 at 13:32, Marcin Wojtas <mw@semihalf.com> wrote:
> > > wt., 9 paź 2018 o 13:28 Wu, Hao A <hao.a.wu@intel.com> napisał(a):
> > >>
> > >> > -----Original Message-----
> > >> > From: edk2-devel [mailto:edk2-devel-bounces@lists.01.org] On Behalf Of Ard
> > >> > Biesheuvel
> > >> > Sent: Monday, October 08, 2018 11:10 PM
> > >> > To: Marcin Wojtas; Ni, Ruiyu; Wu, Hao A
> > >> > Cc: Tian, Feng; Tomasz Michalec; Dong, Eric; edk2-devel-01; Gao, Liming;
> > >> > Nadav Haklai; Kinney, Michael D; Zeng, Star
> > >> > Subject: Re: [edk2] [PATCH v2 2/4] MdeModulePkg/SdMmcPciHcDxe: Add
> > >> > UhsSignaling to SdMmcOverride protocol
> > >> >
> > ...
> > >> >
> > >> > I suppose this is defined by the eMMC spec.
> > >> >
> > >> > Ruiyu, Hao, could you clarify? Are the host control 2 register values
> > >> > for HS200/HS400 defined by the eMMC spec?
> > >>
> > >> Hi Ard and Marcin,
> > >>
> > >> As far as I know, the EMMC Electrical Standard Spec 5.1 (latest) does not
> > >> mention on how to set the "UHS Mode Select" field of the Host Control 2
> > >> Register when switching to HS200/HS400. (Actually, the EMMC spec does not
> > >> mention Host Control 2 Register at all)
> > >>
> > >> When it comes to setting the bus mode for EMMC devices, the current
> > >> implementation of the SdMmcPciHcDxe driver does a mapping when setting the
> > >> Host Control 2 Register:
> > >>
> > >> EMMC High Speed SDR - Freq: 0-52 MHz, Data Rate: Single
> > >> matches
> > >> SD   SDR25          - Freq: 0-50 MHz, Data Rate: Single
> > >>
> > >> EMMC High Speed DDR - Freq: 0-52 MHz, Data Rate: Dual
> > >> matches
> > >> SD   DDR50          - Freq: 0-50 MHz, Data Rate: Dual
> > >>
> > >> EMMC HS200          - Freq: 0-200 MHz, Data Rate: Single
> > >> matches
> > >> SD   SDR104         - Freq: 0-208 MHz, Data Rate: Single
> > >>
> > >> EMMC HS400          - Freq: 0-200 MHz, Data Rate: Dual
> > >> matches
> > >> SD   None
> > >>
> > >> And there is no obvious counterpart for the EMMC HS400 mode in the SD
> > >> spec. The driver currently sets the "UHS Mode Select" field to a reserved
> > >> value 0x5.
> > >>
> > >
> > > Thank you Hao, above is on par with what the default UhsSignaling
> > > routine does in this patch. IMO especially in case the EMMC standard
> > > is not unequivocal regarding UHS_MODE_SEL, I'd encourage to accept
> > > some way of updating HostControl2 register, depending on the
> > > implementation. What is your opinion Ard?
> > >
> >
> > I would like to know where the current values in SdMmcPciHcDxe come
> > from if they are not defined in any spec.
> >
> > How do we know which ones are the correct ones?
>
> Hao, can you justify used values?
>

Hi Hao,

Can you please take a look at the UHS_MODE_SEL values source for eMMC?

Thanks,
Marcin