From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2607:f8b0:4864:20::133; helo=mail-it1-x133.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org Received: from mail-it1-x133.google.com (mail-it1-x133.google.com [IPv6:2607:f8b0:4864:20::133]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 818D621164F0B for ; Thu, 11 Oct 2018 08:43:31 -0700 (PDT) Received: by mail-it1-x133.google.com with SMTP id q70-v6so14169324itb.3 for ; Thu, 11 Oct 2018 08:43:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc:content-transfer-encoding; bh=nYdoyJUUCZSLUWSTb6tGZcutxjqF8AQyJtNyBMYPo8Q=; b=a2qfBumc4PCB9unmUEvSqjI+uV9M6l6Lg+fZ0z1+cB1GNRZN6lyFOsnJD4WdlUxqmX 8A4bYv52sZq6cnkMIaa0xFTi1nThg3VZSVat/CL8iuUofszT3vIb0vSiMHLwIUPI4ztd SE4lF/+gViB2NZUwgEo1VVd4jhyl6MdfgMXRZyrkQk1gsqO5qIlAUk5CXjN8oBw7siyg 9ynZO/jQJcEzc+APAQQlhJ0GFRqQURFcg9pVfU876MqpNxQ0T3jKFlyNNmZoK5lRNIaz ISv9ISb/x+iV4KQskeCAjT8PKV2bFjMNXDRNahZdXt1aI8Yy15v79oxxO3hfCK3qRQDo 3uSA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc:content-transfer-encoding; bh=nYdoyJUUCZSLUWSTb6tGZcutxjqF8AQyJtNyBMYPo8Q=; b=hdlWX5wBW/mxL/5A9hR9cu2plVtDwRhN/j2an+0TVymgiTi+Tt/St/E8ph7MSp0Owd thE1OLlFgybA0BOZN5j0ySpvCwr61HRj4HECu9fzwNkVQBLttE53Cpni2Yva0dMxJK2j 5Gu2k/zvIEd9TgZcAI+29xTv0KQjxLW1WcgEfWvRUFn6qPA8G1vK/f5AReJuWhaDy4uf QKq6TTayoCa4LS6GoKAl0SbGNFZGukPWhoq1YqkLsAnSXOpEPz03LNYRCIiQUjcCCU5t dWmGInDlt/VuLcgkfoQX6mOuTywxoMh/J3lwiN6GAkKuGju8SzH8fLjHjy9e5gUNowpt J2GA== X-Gm-Message-State: ABuFfohF/MnePpZC4shJk2uiJ3XXyEOTPS3pCFrNMzvjqmuhk8KyLbU+ 8c4e4nEphnGfTN7fAiBMi5KW4nrEWePXZnJUzbB1yg== X-Google-Smtp-Source: ACcGV61Dgbc11WGlhTtUDXDIMKaQFQScUastpqJpxfA66KHjg9zVZ2GfXDHEK3hU/u5MZHNIJhIR1Qr37Ox6op09rq4= X-Received: by 2002:a24:a0c:: with SMTP id 12-v6mr1435469itw.145.1539272610621; Thu, 11 Oct 2018 08:43:30 -0700 (PDT) MIME-Version: 1.0 References: <1538745911-22484-1-git-send-email-mw@semihalf.com> <1538745911-22484-3-git-send-email-mw@semihalf.com> In-Reply-To: From: Marcin Wojtas Date: Thu, 11 Oct 2018 17:43:19 +0200 Message-ID: To: hao.a.wu@intel.com Cc: "Ni, Ruiyu" , Ard Biesheuvel , "Tian, Feng" , Tomasz Michalec , eric.dong@intel.com, edk2-devel-01 , "Gao, Liming" , nadavh@marvell.com, "Kinney, Michael D" , "Zeng, Star" Subject: Re: [PATCH v2 2/4] MdeModulePkg/SdMmcPciHcDxe: Add UhsSignaling to SdMmcOverride protocol X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 11 Oct 2018 15:43:31 -0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable wt., 9 pa=C5=BA 2018 o 13:51 Marcin Wojtas napisa=C5=82(a= ): > > wt., 9 pa=C5=BA 2018 o 13:45 Ard Biesheuvel n= apisa=C5=82(a): > > > > On 9 October 2018 at 13:32, Marcin Wojtas wrote: > > > wt., 9 pa=C5=BA 2018 o 13:28 Wu, Hao A napisa=C5= =82(a): > > >> > > >> > -----Original Message----- > > >> > From: edk2-devel [mailto:edk2-devel-bounces@lists.01.org] On Behal= f Of Ard > > >> > Biesheuvel > > >> > Sent: Monday, October 08, 2018 11:10 PM > > >> > To: Marcin Wojtas; Ni, Ruiyu; Wu, Hao A > > >> > Cc: Tian, Feng; Tomasz Michalec; Dong, Eric; edk2-devel-01; Gao, L= iming; > > >> > Nadav Haklai; Kinney, Michael D; Zeng, Star > > >> > Subject: Re: [edk2] [PATCH v2 2/4] MdeModulePkg/SdMmcPciHcDxe: Add > > >> > UhsSignaling to SdMmcOverride protocol > > >> > > > ... > > >> > > > >> > I suppose this is defined by the eMMC spec. > > >> > > > >> > Ruiyu, Hao, could you clarify? Are the host control 2 register val= ues > > >> > for HS200/HS400 defined by the eMMC spec? > > >> > > >> Hi Ard and Marcin, > > >> > > >> As far as I know, the EMMC Electrical Standard Spec 5.1 (latest) doe= s not > > >> mention on how to set the "UHS Mode Select" field of the Host Contro= l 2 > > >> Register when switching to HS200/HS400. (Actually, the EMMC spec doe= s not > > >> mention Host Control 2 Register at all) > > >> > > >> When it comes to setting the bus mode for EMMC devices, the current > > >> implementation of the SdMmcPciHcDxe driver does a mapping when setti= ng the > > >> Host Control 2 Register: > > >> > > >> EMMC High Speed SDR - Freq: 0-52 MHz, Data Rate: Single > > >> matches > > >> SD SDR25 - Freq: 0-50 MHz, Data Rate: Single > > >> > > >> EMMC High Speed DDR - Freq: 0-52 MHz, Data Rate: Dual > > >> matches > > >> SD DDR50 - Freq: 0-50 MHz, Data Rate: Dual > > >> > > >> EMMC HS200 - Freq: 0-200 MHz, Data Rate: Single > > >> matches > > >> SD SDR104 - Freq: 0-208 MHz, Data Rate: Single > > >> > > >> EMMC HS400 - Freq: 0-200 MHz, Data Rate: Dual > > >> matches > > >> SD None > > >> > > >> And there is no obvious counterpart for the EMMC HS400 mode in the S= D > > >> spec. The driver currently sets the "UHS Mode Select" field to a res= erved > > >> value 0x5. > > >> > > > > > > Thank you Hao, above is on par with what the default UhsSignaling > > > routine does in this patch. IMO especially in case the EMMC standard > > > is not unequivocal regarding UHS_MODE_SEL, I'd encourage to accept > > > some way of updating HostControl2 register, depending on the > > > implementation. What is your opinion Ard? > > > > > > > I would like to know where the current values in SdMmcPciHcDxe come > > from if they are not defined in any spec. > > > > How do we know which ones are the correct ones? > > Hao, can you justify used values? > Hi Hao, Can you please take a look at the UHS_MODE_SEL values source for eMMC? Thanks, Marcin