From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: mx.groups.io; dkim=pass header.i=@semihalf-com.20150623.gappssmtp.com header.s=20150623 header.b=ZcYOlqjK; spf=none, err=SPF record not found (domain: semihalf.com, ip: 209.85.222.195, mailfrom: mw@semihalf.com) Received: from mail-qk1-f195.google.com (mail-qk1-f195.google.com [209.85.222.195]) by groups.io with SMTP; Thu, 08 Aug 2019 06:51:30 -0700 Received: by mail-qk1-f195.google.com with SMTP id r6so68859635qkc.0 for ; Thu, 08 Aug 2019 06:51:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc:content-transfer-encoding; bh=Qe4wHp5KAh+ChIKO4kgamKdLmitoDLDThuwIf39NXUU=; b=ZcYOlqjKonbb3YxkrzXhGxUvIVqgjqKIiRNQ6TejtiMbo6GoUQKACkRaGoW7/9NfZk YTHZyzT5smZORAFAp3AeJsAYJW10UowVfPZarUgPwjZuvMJxYpKFztuSC4F6OhXPTYzK LMpXZOZZsMZOOK3pkvKeEhXLs7rV03DntPYhKjlHtP0+xXa422p9iDKW5/G0iH7RhPVR gY8TxavMKVi0tQ0l/tvge83iUwB76pV00Jc80QmEG13VmxQQ3wcJMg43efFLtuGOAM21 0oi3/nj/OdPM4+/8Pg/0e3EIfY+Y65SWj21WDPDQC3x/E1hkO1Rtz/69YNV0FPuYuXRE BSEA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc:content-transfer-encoding; bh=Qe4wHp5KAh+ChIKO4kgamKdLmitoDLDThuwIf39NXUU=; b=Z8pGtw9fWYL8dITDMbKe7yFulgLso9BMjpCko8qWgP+K08n1J8xFSArMNQiddYIfHD ybDZAqY3+ipEvM2w21XNUxM1jmOzgMeHcYY1meO9/Qay3PiDsuTooV/zOktJrJQ+pAyX +MGf3NKq+fCcOV0oDRNJ8DpRvagu349z2xayCODH3uuJBhkTHe7NlhAhDhyHw43s7aam kuTOuhlY46eepRRa47DdqP+VNqxqCXGiXmLnffpT64zS5vGK8CQ34e95jVbPU7LaDwKc FtSHtcz+mOZMOHSyhD3PHBB0lGUTu5JmqBHsFjFDZp85/AFb9ERuWJfvrMbBJxHBB7ZA FD9g== X-Gm-Message-State: APjAAAUds9K5tbkmyPRaDF3eS/Lhpf/3uV9TBtQF1SeWMFYXMJ1dFYoR Th7+TeXFbbZHt91lCi6Ynl8MozTDpDqs7USJV1WyMg== X-Google-Smtp-Source: APXvYqyIenuJL+nxAwPNLx/4aPzcydjPOnYYCIzrbKolimbK00RbwOlwWNWby7XYgmsjCjjKZBeHTg0Tc3ddqtDfliU= X-Received: by 2002:a05:620a:1345:: with SMTP id c5mr1632916qkl.109.1565272289749; Thu, 08 Aug 2019 06:51:29 -0700 (PDT) MIME-Version: 1.0 References: <1565220630-1653-1-git-send-email-mw@semihalf.com> <20190808115153.GX25813@bivouac.eciton.net> In-Reply-To: <20190808115153.GX25813@bivouac.eciton.net> From: "Marcin Wojtas" Date: Thu, 8 Aug 2019 15:51:15 +0200 Message-ID: Subject: Re: [edk2-platforms: PATCH 0/9] Marvell Octeon CN913X SoC family support To: Leif Lindholm Cc: edk2-devel-groups-io , Ard Biesheuvel , "jsd@semihalf.com" , Grzegorz Jaszczyk , Kostya Porotchkin Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Hi Leif, czw., 8 sie 2019 o 13:51 Leif Lindholm napisa=C5= =82(a): > > Hi Marcin, > > On Thu, Aug 08, 2019 at 01:30:21AM +0200, Marcin Wojtas wrote: > > Hi, > > > > Marvell Octeon CN913X SoC is a new device, which is built of > > upgraded hardware blocks known from previously supported line > > of SoCs. It is avaialble in 3 variants - CN9130/CN9131/CN9132. > > > > CN9130 is made of a single Application Processor unit > > (AP807) and one internal south bridge (CP115). It can > > be extended to CN9131 (internal + external south bridges). > > The CN9132 has 3 south bridge units. > > > > This patchset adds all necessary components (.dsc/.fdf, > > libraries, ACPI, DT) to support all 3 variants, which > > are available on a modular CN913x Development Board. > > Thanks for this contribution. > Do you have any further information on this SoC/Devboard? > Searching only gets me the CN8xxx SoCs. > Indeed :/ I guess there should be some public information soon, unfortunately I'm not in charge of it. FYI, 2 days ago the support for it was submitted to the Linux lists: https://www.spinics.net/lists/arm-kernel/msg746208.html In high level this SoC is successor of Armada - enhanced modularity, more interfaces, higher freq, new DDR controller and so on. > > The patches are available in the github: > > https://github.com/MarvellEmbeddedProcessors/edk2-open-platform/commits= /cn913x-upstream-r20190808 > > > > I'm looking forward to your comments or remarks. > > First issue I run into is that 9130/9131 bail out on DSDT.aml: > "iasl" > -p/work/git/tianocore/Build/Cn9130DbA-AARCH64/DEBUG_GCC5/AARCH64/Silicon/= Marvell/OcteonTx/AcpiTables/T91/Cn9130DbA/OUTPUT/Cn913xDbA/Dsdt.aml > /work/git/tianocore/Build/Cn9130DbA-AARCH64/DEBUG_GCC5/AARCH64/Silicon/Ma= rvell/OcteonTx/AcpiTables/T91/Cn9130DbA/OUTPUT/Cn913xDbA/Dsdt.iiii > /work/git/tianocore/Build/Cn9130DbA-AARCH64/DEBUG_GCC5/AARCH64/Silicon/Ma= rvell/OcteonTx/AcpiTables/T91/Cn9130DbA/OUTPUT/Cn913xDbA/Dsdt.iiii > 17: DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN9130DBA", 3) > > Intel ACPI Component Architecture > ASL+ Optimizing Compiler/Disassembler version 20181213 > Copyright (c) 2000 - 2018 Intel Corporation > > ASL Input: > /work/git/tianocore/Build/Cn9130DbA-AARCH64/DEBUG_GCC5/AARCH64/Silicon/Ma= rvell/OcteonTx/AcpiTables/T91/Cn9130DbA/OUTPUT/Cn913xDbA/Dsdt.iiii > - 328 lines, 9303 bytes, 97 keywords > > Compilation complete. 1 Errors, 0 Warnings, 0 Remarks, 34 > Optimizations > Error 6155 - > Invalid OEM Table ID ^ (Length cannot exceed 8 characters) > > This does not affect Cn9132DbA, since that one does not include the > ACPI module. Is this intenional? > Maybe I should've mention this explicitly - yes, as for now we do not support ACPI on triple-CP115 variant. The reason is following - currently we have a static configuration of the ICU (CP115 interrupt controller) to GIC. Thanks to that, we can assign GIC interrupts in static ACPI tables. Unfortunately dual CP115/CP110 setup uses all available GIC IRQs for this. We need to create mapping only for the used devices and pass it to the ACPI tables. What is needed to fix it properly: - create ICU-GIC dynamic mapping - dynamically fill this information in DSDT/SSDT. > Which version of iasl has this been tested with? > I built it successfully with iasl versions: 20180105 and 20160108-2. Anyway, in v2 I'll shorten OEM table ID to 8 characters ( "CN9130DBA" is 9 character). > (Plese don't respin a v2, I will go through things a bit more and > provide feedback.) > Thanks, Marcin > Best Regards, > > Leif > > > Best regards, > > Marcin > > > > > > Marcin Wojtas (9): > > Marvell/Cn9130Db: Add ACPI tables > > Marvell/Cn9130Db: Add DeviceTree > > Marvell/Cn9130Db: Introduce board support > > Marvell/Library: ArmadaSoCDescLib: Extend Xenon information > > Marvell/Library: MppLib: Allow to configure more Xenon PHYs > > Marvell/Library: IcuLib: Fix debug information > > Marvell/Cn9131Db: Introduce board support > > Marvell/Cn9132Db: Introduce board support > > Marvell/Drivers: SmbiosPlatformDxe: Use more generic board name > > > > Platform/Marvell/Cn913xDb/Cn9130DbA.dsc.inc = | 107 ++++ > > Platform/Marvell/Cn913xDb/Cn9131DbA.dsc.inc = | 72 +++ > > Platform/Marvell/Cn913xDb/Cn9132DbA.dsc.inc = | 72 +++ > > Platform/Marvell/Cn913xDb/Cn9130DbA.dsc = | 46 ++ > > Platform/Marvell/Cn913xDb/Cn9131DbA.dsc = | 47 ++ > > Platform/Marvell/Cn913xDb/Cn9132DbA.dsc = | 45 ++ > > Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9130DbABoardDescLib.in= f | 29 + > > Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9132DbABoardDescLib.in= f | 29 + > > Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLi= b.inf | 37 ++ > > Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9130DbA.inf = | 56 ++ > > Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA.inf = | 57 ++ > > Silicon/Marvell/OcteonTx/DeviceTree/T91/Cn9130DbA.inf = | 22 + > > Silicon/Marvell/OcteonTx/DeviceTree/T91/Cn9131DbA.inf = | 22 + > > Silicon/Marvell/OcteonTx/DeviceTree/T91/Cn9132DbA.inf = | 22 + > > Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLi= b.h | 25 + > > Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCD= escLib.h | 5 +- > > Silicon/Marvell/OcteonTx/AcpiTables/T91/AcpiHeader.h = | 39 ++ > > Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Pcie.h = | 20 + > > Silicon/Marvell/OcteonTx/AcpiTables/T91/IcuInterrupts.h = | 36 ++ > > Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9130DbABoardDescLib.c = | 126 +++++ > > Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9132DbABoardDescLib.c = | 135 +++++ > > Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLi= b.c | 215 ++++++++ > > Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCD= escLib.c | 34 +- > > Silicon/Marvell/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.c = | 4 +- > > Silicon/Marvell/Library/IcuLib/IcuLib.c = | 4 +- > > Silicon/Marvell/Library/MppLib/MppLib.c = | 4 +- > > Platform/Marvell/Cn913xDb/Cn9130DbA.fdf.inc = | 17 + > > Platform/Marvell/Cn913xDb/Cn9131DbA.fdf.inc = | 18 + > > Platform/Marvell/Cn913xDb/Cn9132DbA.fdf.inc = | 13 + > > Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA/Ssdt.asl = | 98 ++++ > > Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dsdt.asl = | 324 ++++++++++++ > > Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Mcfg.aslc = | 41 ++ > > Silicon/Marvell/OcteonTx/AcpiTables/T91/Fadt.aslc = | 80 +++ > > Silicon/Marvell/OcteonTx/AcpiTables/T91/Gtdt.aslc = | 58 ++ > > Silicon/Marvell/OcteonTx/AcpiTables/T91/Madt.aslc = | 135 +++++ > > Silicon/Marvell/OcteonTx/AcpiTables/T91/Pptt.aslc = | 210 ++++++++ > > Silicon/Marvell/OcteonTx/AcpiTables/T91/Spcr.aslc = | 49 ++ > > Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-ap806-quad.dtsi = | 43 ++ > > Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-ap806.dtsi = | 264 ++++++++++ > > Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-common.dtsi = | 10 + > > Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-cp110.dtsi = | 552 ++++++++++++++++++++ > > Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9130-db-A.dts = | 185 +++++++ > > Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9130-db.dtsi = | 168 ++++++ > > Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9130.dtsi = | 126 +++++ > > Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9131-db-A.dts = | 29 + > > Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9131-db.dtsi = | 175 +++++++ > > Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9132-db-A.dts = | 70 +++ > > Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9132-db.dtsi = | 159 ++++++ > > 48 files changed, 4113 insertions(+), 21 deletions(-) > > create mode 100644 Platform/Marvell/Cn913xDb/Cn9130DbA.dsc.inc > > create mode 100644 Platform/Marvell/Cn913xDb/Cn9131DbA.dsc.inc > > create mode 100644 Platform/Marvell/Cn913xDb/Cn9132DbA.dsc.inc > > create mode 100644 Platform/Marvell/Cn913xDb/Cn9130DbA.dsc > > create mode 100644 Platform/Marvell/Cn913xDb/Cn9131DbA.dsc > > create mode 100644 Platform/Marvell/Cn913xDb/Cn9132DbA.dsc > > create mode 100644 Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn913= 0DbABoardDescLib.inf > > create mode 100644 Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn913= 2DbABoardDescLib.inf > > create mode 100644 Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/No= nDiscoverableInitLib.inf > > create mode 100644 Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9130DbA.i= nf > > create mode 100644 Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA.i= nf > > create mode 100644 Silicon/Marvell/OcteonTx/DeviceTree/T91/Cn9130DbA.i= nf > > create mode 100644 Silicon/Marvell/OcteonTx/DeviceTree/T91/Cn9131DbA.i= nf > > create mode 100644 Silicon/Marvell/OcteonTx/DeviceTree/T91/Cn9132DbA.i= nf > > create mode 100644 Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/No= nDiscoverableInitLib.h > > create mode 100644 Silicon/Marvell/OcteonTx/AcpiTables/T91/AcpiHeader.= h > > create mode 100644 Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/P= cie.h > > create mode 100644 Silicon/Marvell/OcteonTx/AcpiTables/T91/IcuInterrup= ts.h > > create mode 100644 Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn913= 0DbABoardDescLib.c > > create mode 100644 Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn913= 2DbABoardDescLib.c > > create mode 100644 Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/No= nDiscoverableInitLib.c > > create mode 100644 Platform/Marvell/Cn913xDb/Cn9130DbA.fdf.inc > > create mode 100644 Platform/Marvell/Cn913xDb/Cn9131DbA.fdf.inc > > create mode 100644 Platform/Marvell/Cn913xDb/Cn9132DbA.fdf.inc > > create mode 100644 Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA/S= sdt.asl > > create mode 100644 Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/D= sdt.asl > > create mode 100644 Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/M= cfg.aslc > > create mode 100644 Silicon/Marvell/OcteonTx/AcpiTables/T91/Fadt.aslc > > create mode 100644 Silicon/Marvell/OcteonTx/AcpiTables/T91/Gtdt.aslc > > create mode 100644 Silicon/Marvell/OcteonTx/AcpiTables/T91/Madt.aslc > > create mode 100644 Silicon/Marvell/OcteonTx/AcpiTables/T91/Pptt.aslc > > create mode 100644 Silicon/Marvell/OcteonTx/AcpiTables/T91/Spcr.aslc > > create mode 100644 Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-ap80= 6-quad.dtsi > > create mode 100644 Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-ap80= 6.dtsi > > create mode 100644 Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-comm= on.dtsi > > create mode 100644 Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-cp11= 0.dtsi > > create mode 100644 Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9130-db-A= .dts > > create mode 100644 Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9130-db.d= tsi > > create mode 100644 Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9130.dtsi > > create mode 100644 Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9131-db-A= .dts > > create mode 100644 Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9131-db.d= tsi > > create mode 100644 Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9132-db-A= .dts > > create mode 100644 Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9132-db.d= tsi > > > > -- > > 2.7.4 > >