From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2607:f8b0:4001:c0b::242; helo=mail-it0-x242.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org Received: from mail-it0-x242.google.com (mail-it0-x242.google.com [IPv6:2607:f8b0:4001:c0b::242]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 8228620352AAF for ; Mon, 6 Aug 2018 09:08:16 -0700 (PDT) Received: by mail-it0-x242.google.com with SMTP id d16-v6so12739417itj.0 for ; Mon, 06 Aug 2018 09:08:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc:content-transfer-encoding; bh=jMGSylyFX+JMjO55LmCr5OrFkMMyM+Ge75KtbjPNfq8=; b=SKElCSvjwZzY+yY67GE0SQ5LlisRO3Npt1f+IzeP2QLdBb99+CJcgFm0awjy+NRlFV 24YPp7Gb9Kg0F5if58jU4AS2qLd9Sro6+mFQI8RQU56eF2RATRslpUXwyi81xsCyJs+0 N7CPbDNDbwvN/cos10XAKObLYz2hjEBSaYaVmi/k8q0fjXkSA+3gFf4zTuiY+jqEZDra tq3vyFXJ3v0Aob7W4oohw0vnW/UlJADh4qdhJyuHOKxTGWicCzb/MGj4a9VaFqad3R1o yB//Rylue9/we1NS2P+OqAAQqLmr1I4HCV3+Jmut+W0fFsN9Y9ng/TZz5H1uZKfIQYBa ARLQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc:content-transfer-encoding; bh=jMGSylyFX+JMjO55LmCr5OrFkMMyM+Ge75KtbjPNfq8=; b=Pdvi/xpkG5QjPeZ1VltOHHgMpf8b0CgqAm0z8gxxutoyeKjDcr+ltRq5cX8S4bfuiK v6gbRvFWiWWa3eZC3dozyk01v4xnRTqDANuhf6a1Tabn7h1a0MzTXvy7Ryg3wKg5CL5S 3x+0aeJTK+MTgpXEp0ncYrrS6X4Q4pX80w8hbjLoajVzNvryClrll05gOj6SX4ewpALb IQwU84NHWlM7eMxaD9sdipZZPENQWC45JMMlI6x8uhbjm7ZucOvVk+YtiNoamSbpYmP5 C7d1AltJ5seJRm8fVs7nNMNjYqCnDYaiTfqaFhpSGPcFNKkFKCA1l7BdlES5g0/O5QC1 Bs8g== X-Gm-Message-State: AOUpUlEEPoUvUQxpKvocq+skDC/V7BQ3gR9kKn723xWhFi8j2XMYGe4d vwQveQYIs6EJqgQlbiziDMEhIdwTzRkM0ELdG0h32Q== X-Google-Smtp-Source: AAOMgpdldRS1c3uWp7IPQHhse4UCyd/1FffvOc+YOujSJToKOHmqmkeb6KuiM5kqDrqmqzmmF2FjeN31L9alqB8guYo= X-Received: by 2002:a24:9b82:: with SMTP id o124-v6mr14797154itd.56.1533571695472; Mon, 06 Aug 2018 09:08:15 -0700 (PDT) MIME-Version: 1.0 References: <1533511706-9344-1-git-send-email-mw@semihalf.com> <1533511706-9344-8-git-send-email-mw@semihalf.com> In-Reply-To: From: Marcin Wojtas Date: Mon, 6 Aug 2018 18:08:02 +0200 Message-ID: To: Ard Biesheuvel Cc: edk2-devel-01 , Leif Lindholm , nadavh@marvell.com, "jsd@semihalf.com" , Grzegorz Jaszczyk Subject: Re: [platforms: PATCH 7/9] Marvell/Armada70x0Db: Enable ACPI support X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.27 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 06 Aug 2018 16:08:16 -0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable HI Ard, pon., 6 sie 2018 o 13:54 Ard Biesheuvel napisa= =C5=82(a): > > On 6 August 2018 at 01:28, Marcin Wojtas wrote: > > This patch introduces DSDT table and adds necessary > > wiring in order to enable ACPI support on Armada 7040 DB. > > > > Contributed-under: TianoCore Contribution Agreement 1.1 > > Signed-off-by: Marcin Wojtas > > --- > > Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc | 1= 4 ++ > > Platform/Marvell/Armada70x0Db/Armada70x0Db.dsc | = 3 + > > Silicon/Marvell/Armada7k8k/Armada7k8k.fdf | 1= 2 + > > Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db/AcpiTables.inf | 6= 1 ++++++ > > Platform/Marvell/Armada70x0Db/Armada70x0Db.fdf.inc | = 5 + > > Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db/Dsdt.asl | 22= 9 ++++++++++++++++++++ > > Silicon/Marvell/Documentation/PortingGuide.txt | 2= 2 ++ > > 7 files changed, 346 insertions(+) > > create mode 100644 Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db/= AcpiTables.inf > > create mode 100644 Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db/= Dsdt.asl > > > > diff --git a/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc b/Silicon/Ma= rvell/Armada7k8k/Armada7k8k.dsc.inc > > index f1ccda0..d4c67a2 100644 > > --- a/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc > > +++ b/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc > > @@ -593,6 +593,20 @@ > > ShellPkg/DynamicCommand/TftpDynamicCommand/TftpDynamicCommand.inf > > !endif #$(INCLUDE_TFTP_COMMAND) > > > > +[Components.AARCH64] > > + # > > + # Generic ACPI modules > > + # > > + MdeModulePkg/Universal/Acpi/AcpiPlatformDxe/AcpiPlatformDxe.inf > > + MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf { > > + > > + PlatformHasAcpiLib|EmbeddedPkg/Library/PlatformHasAcpiLib/Platfo= rmHasAcpiLib.inf > > + > > + > > + # support ACPI v5.0 or later > > + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiExposedTableVersions|0x20 > > + } > > + > > [BuildOptions.common.EDKII.DXE_CORE,BuildOptions.common.EDKII.DXE_DRIV= ER,BuildOptions.common.EDKII.UEFI_DRIVER,BuildOptions.common.EDKII.UEFI_APP= LICATION] > > GCC:*_*_*_DLINK_FLAGS =3D -z common-page-size=3D0x1000 > > > > diff --git a/Platform/Marvell/Armada70x0Db/Armada70x0Db.dsc b/Platform/= Marvell/Armada70x0Db/Armada70x0Db.dsc > > index d3dffb0..f6faff1 100644 > > --- a/Platform/Marvell/Armada70x0Db/Armada70x0Db.dsc > > +++ b/Platform/Marvell/Armada70x0Db/Armada70x0Db.dsc > > @@ -51,6 +51,9 @@ > > [Components.common] > > Silicon/Marvell/Armada7k8k/DeviceTree/Armada70x0Db.inf > > > > +[Components.AARCH64] > > + Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db/AcpiTables.inf > > + > > ######################################################################= ########## > > # > > # Pcd Section - list of all EDK II PCD Entries defined by this Platfor= m > > diff --git a/Silicon/Marvell/Armada7k8k/Armada7k8k.fdf b/Silicon/Marvel= l/Armada7k8k/Armada7k8k.fdf > > index 909ad3e..c064a43 100644 > > --- a/Silicon/Marvell/Armada7k8k/Armada7k8k.fdf > > +++ b/Silicon/Marvell/Armada7k8k/Armada7k8k.fdf > > @@ -215,6 +215,12 @@ FvNameGuid =3D 5eda4200-2c5f-43cb-9da3-0ba= f74b1b30c > > # DTB > > INF EmbeddedPkg/Drivers/DtPlatformDxe/DtPlatformDxe.inf > > > > +!if $(ARCH) =3D=3D AARCH64 > > + # ACPI support > > + INF MdeModulePkg/Universal/Acpi/AcpiPlatformDxe/AcpiPlatformDxe.inf > > + INF MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf > > +!endif > > + > > !include $(BOARD_DXE_FV_COMPONENTS) > > > > # PEI phase firmware volume > > @@ -408,3 +414,9 @@ READ_LOCK_STATUS =3D TRUE > > FILE FREEFORM =3D $(NAMED_GUID) { > > RAW BIN |.dtb > > } > > + > > +[Rule.Common.USER_DEFINED.ACPITABLE] > > + FILE FREEFORM =3D $(NAMED_GUID) { > > + RAW ASL |.aml > > + RAW ACPI |.acpi > > + } > > diff --git a/Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db/AcpiTab= les.inf b/Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db/AcpiTables.inf > > new file mode 100644 > > index 0000000..8732e10 > > --- /dev/null > > +++ b/Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db/AcpiTables.inf > > @@ -0,0 +1,61 @@ > > +## @file > > +# Component description file for PlatformAcpiTables module. > > +# > > +# ACPI table data and ASL sources required to boot the platform. > > +# > > +# Copyright (c) 2018, Linaro, Ltd. All rights reserved.
> > +# Copyright (C) 2018, Marvell International Ltd. and its affiliates.<= BR> > > +# > > +# This program and the accompanying materials > > +# are licensed and made available under the terms and conditions of t= he BSD License > > +# which accompanies this distribution. The full text of the license = may be found at > > +# http://opensource.org/licenses/bsd-license.php > > +# > > +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASI= S, > > +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS O= R IMPLIED. > > +# > > +## > > + > > +[Defines] > > + INF_VERSION =3D 0x0001001A > > + BASE_NAME =3D PlatformAcpiTables > > + FILE_GUID =3D 7E374E25-8E01-4FEE-87F2-390C23C60= 6CD > > + MODULE_TYPE =3D USER_DEFINED > > + VERSION_STRING =3D 1.0 > > + > > +[Sources] > > + Dsdt.asl > > + ../Fadt.aslc > > + ../Gtdt.aslc > > + ../Madt.aslc > > + ../Pptt.aslc > > + ../Spcr.aslc > > + > > Could we reshuffle these files so we nog longer rely relative includes? > Possibly using a Common subdirectory? Would below directory tree be acceptable? Silicon/Marvell/Armada7k8k/AcpiTables/ =E2=94=9C=E2=94=80=E2=94=80 AcpiHeader.h =E2=94=9C=E2=94=80=E2=94=80 Armada70x0Db =E2=94=82 =E2=94=94=E2=94=80=E2=94=80 Dsdt.asl =E2=94=9C=E2=94=80=E2=94=80 Armada70x0Db.inf =E2=94=9C=E2=94=80=E2=94=80 Armada80x0Db =E2=94=82 =E2=94=94=E2=94=80=E2=94=80 Dsdt.asl =E2=94=9C=E2=94=80=E2=94=80 Armada80x0Db.inf =E2=94=9C=E2=94=80=E2=94=80 Armada80x0McBin =E2=94=82 =E2=94=94=E2=94=80=E2=94=80 Dsdt.asl =E2=94=9C=E2=94=80=E2=94=80 Armada80x0McBin.inf =E2=94=9C=E2=94=80=E2=94=80 Fadt.aslc =E2=94=9C=E2=94=80=E2=94=80 Gtdt.aslc =E2=94=9C=E2=94=80=E2=94=80 IcuInterrupts.h =E2=94=9C=E2=94=80=E2=94=80 Madt.aslc =E2=94=9C=E2=94=80=E2=94=80 Pptt.aslc =E2=94=94=E2=94=80=E2=94=80 Spcr.aslc This way we will have following in the .inf Armada80x0McBin/Dsdt.asl Fadt.aslc Gtdt.aslc Madt.aslc Pptt.aslc Spcr.aslc Best regards, Marcin > > > +[Packages] > > + ArmPkg/ArmPkg.dec > > + ArmPlatformPkg/ArmPlatformPkg.dec > > + EmbeddedPkg/EmbeddedPkg.dec > > + MdeModulePkg/MdeModulePkg.dec > > + MdePkg/MdePkg.dec > > + Silicon/Marvell/Marvell.dec > > + > > +[FixedPcd] > > + gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase > > + gArmTokenSpaceGuid.PcdGicDistributorBase > > + > > + gArmPlatformTokenSpaceGuid.PcdCoreCount > > + > > + gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum > > + gArmTokenSpaceGuid.PcdArmArchTimerIntrNum > > + gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum > > + gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum > > + > > + gArmTokenSpaceGuid.PcdGenericWatchdogControlBase > > + gArmTokenSpaceGuid.PcdGenericWatchdogRefreshBase > > + gArmTokenSpaceGuid.PcdGenericWatchdogEl2IntrNum > > + > > + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase > > + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialClockRate > > + > > +[BuildOptions] > > + *_*_*_ASLCC_FLAGS =3D -DARMADA7K > > diff --git a/Platform/Marvell/Armada70x0Db/Armada70x0Db.fdf.inc b/Platf= orm/Marvell/Armada70x0Db/Armada70x0Db.fdf.inc > > index b4c3e20..0610fdb 100644 > > --- a/Platform/Marvell/Armada70x0Db/Armada70x0Db.fdf.inc > > +++ b/Platform/Marvell/Armada70x0Db/Armada70x0Db.fdf.inc > > @@ -14,3 +14,8 @@ > > > > # DTB > > INF RuleOverride =3D DTB Silicon/Marvell/Armada7k8k/DeviceTree/Armad= a70x0Db.inf > > + > > +!if $(ARCH) =3D=3D AARCH64 > > + # ACPI support > > + INF RuleOverride =3D ACPITABLE Silicon/Marvell/Armada7k8k/AcpiTables= /Armada70x0Db/AcpiTables.inf > > +!endif > > diff --git a/Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db/Dsdt.as= l b/Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db/Dsdt.asl > > new file mode 100644 > > index 0000000..621b688 > > --- /dev/null > > +++ b/Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db/Dsdt.asl > > @@ -0,0 +1,229 @@ > > +/** @file > > + > > + Differentiated System Description Table Fields (DSDT) > > + > > + Copyright (c) 2018, Linaro Ltd. All rights reserved.
> > + Copyright (C) 2018, Marvell International Ltd. and its affiliates. > > + > > + This program and the accompanying materials > > + are licensed and made available under the terms and conditions of th= e BSD License > > + which accompanies this distribution. The full text of the license m= ay be found at > > + http://opensource.org/licenses/bsd-license.php > > + > > + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS= , > > + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR= IMPLIED. > > + > > +**/ > > + > > +#include "IcuInterrupts.h" > > + > > +DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA7K", 3) > > +{ > > + Scope (_SB) > > + { > > + Device (CPU0) > > + { > > + Name (_HID, "ACPI0007" /* Processor Device */) // _HID: H= ardware ID > > + Name (_UID, 0x000) // _UID: Unique ID > > + } > > + Device (CPU1) > > + { > > + Name (_HID, "ACPI0007" /* Processor Device */) // _HID: H= ardware ID > > + Name (_UID, 0x001) // _UID: Unique ID > > + } > > + Device (CPU2) > > + { > > + Name (_HID, "ACPI0007" /* Processor Device */) // _HID: H= ardware ID > > + Name (_UID, 0x100) // _UID: Unique ID > > + } > > + Device (CPU3) > > + { > > + Name (_HID, "ACPI0007" /* Processor Device */) // _HID: H= ardware ID > > + Name (_UID, 0x101) // _UID: Unique ID > > + } > > + > > + Device (AHC0) > > + { > > + Name (_HID, "LNRO001E") // _HID: Hardware ID > > + Name (_UID, 0x00) // _UID: Unique ID > > + Name (_CCA, 0x01) // _CCA: Cache Coherency Attri= bute > > + Name (_CLS, Package (0x03) // _CLS: Class Code > > + { > > + 0x01, > > + 0x06, > > + 0x01 > > + }) > > + > > + Name (_CRS, ResourceTemplate () // _CRS: Current Resource= Settings > > + { > > + Memory32Fixed (ReadWrite, > > + 0xF2540000, // Address Base (MMIO) > > + 0x00030000, // Address Length > > + ) > > + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclus= ive, ,, ) > > + { > > + CP_GIC_SPI_CP0_SATA_H0 > > + } > > + }) > > + } > > + > > + Device (XHC0) > > + { > > + Name (_HID, "PNP0D10") // _HID: Hardware ID > > + Name (_UID, 0x00) // _UID: Unique ID > > + Name (_CCA, 0x01) // _CCA: Cache Coherency Attri= bute > > + > > + Name (_CRS, ResourceTemplate () // _CRS: Current Resource= Settings > > + { > > + Memory32Fixed (ReadWrite, > > + 0xF2500000, // Address Base (MMIO) > > + 0x00004000, // Address Length > > + ) > > + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclus= ive, ,, ) > > + { > > + CP_GIC_SPI_CP0_USB_H0 > > + } > > + }) > > + } > > + > > + Device (XHC1) > > + { > > + Name (_HID, "PNP0D10") // _HID: Hardware ID > > + Name (_UID, 0x01) // _UID: Unique ID > > + Name (_CCA, 0x01) // _CCA: Cache Coherency Attri= bute > > + > > + Name (_CRS, ResourceTemplate () // _CRS: Current Resource= Settings > > + { > > + Memory32Fixed (ReadWrite, > > + 0xF2510000, // Address Base (MMIO) > > + 0x00004000, // Address Length > > + ) > > + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclus= ive, ,, ) > > + { > > + CP_GIC_SPI_CP0_USB_H1 > > + } > > + }) > > + } > > + > > + Device (COM1) > > + { > > + Name (_HID, "HISI0031") // _HI= D: Hardware ID > > + Name (_CID, "8250dw") // _CI= D: Compatible ID > > + Name (_ADR, FixedPcdGet64(PcdSerialRegisterBase)) // _AD= R: Address > > + Name (_CRS, ResourceTemplate () // _CR= S: Current Resource Settings > > + { > > + Memory32Fixed (ReadWrite, > > + FixedPcdGet64(PcdSerialRegisterBase), // Add= ress Base > > + 0x00000100, // Add= ress Length > > + ) > > + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclus= ive, ,, ) > > + { > > + 51 > > + } > > + }) > > + Name (_DSD, Package () { > > + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), > > + Package () { > > + Package () { "clock-frequency", FixedPcdGet32 (P= cdSerialClockRate) }, > > + Package () { "reg-io-width", 1 }, > > + Package () { "reg-shift", 2 }, > > + } > > + }) > > + } > > + > > + Device (PP20) > > + { > > + Name (_HID, "MRVL0110") // _HI= D: Hardware ID > > + Name (_CCA, 0x01) // Cac= he-coherent controller > > + Name (_UID, 0x00) // _UI= D: Unique ID > > + Name (_CRS, ResourceTemplate () > > + { > > + Memory32Fixed (ReadWrite, 0xf2000000 , 0x100000) > > + Memory32Fixed (ReadWrite, 0xf2129000 , 0xb000) > > + }) > > + Name (_DSD, Package () { > > + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), > > + Package () { > > + Package () { "clock-frequency", 333333333 }, > > + } > > + }) > > + Device (ETH0) > > + { > > + Name (_ADR, 0x0) > > + Name (_CRS, ResourceTemplate () > > + { > > + Interrupt (ResourceConsumer, Level, ActiveHigh, Excl= usive, ,, ) > > + { > > + CP_GIC_SPI_PP2_CP0_PORT0 > > + } > > + }) > > + Name (_DSD, Package () { > > + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), > > + Package () { > > + Package () { "port-id", 0 }, > > + Package () { "gop-port-id", 0 }, > > + Package () { "phy-mode", "10gbase-kr"}, > > + } > > + }) > > + } > > + Device (ETH1) > > + { > > + Name (_ADR, 0x0) > > + Name (_CRS, ResourceTemplate () > > + { > > + Interrupt (ResourceConsumer, Level, ActiveHigh, Excl= usive, ,, ) > > + { > > + CP_GIC_SPI_PP2_CP0_PORT1 > > + } > > + }) > > + Name (_DSD, Package () { > > + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), > > + Package () { > > + Package () { "port-id", 1 }, > > + Package () { "gop-port-id", 2 }, > > + Package () { "phy-mode", "sgmii"}, > > + } > > + }) > > + } > > + Device (ETH2) > > + { > > + Name (_ADR, 0x0) > > + Name (_CRS, ResourceTemplate () > > + { > > + Interrupt (ResourceConsumer, Level, ActiveHigh, Excl= usive, ,, ) > > + { > > + CP_GIC_SPI_PP2_CP0_PORT2 > > + } > > + }) > > + Name (_DSD, Package () { > > + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), > > + Package () { > > + Package () { "port-id", 2 }, > > + Package () { "gop-port-id", 3 }, > > + Package () { "phy-mode", "rgmii-id"}, > > + } > > + }) > > + } > > + } > > + > > + Device (RNG0) > > + { > > + Name (_HID, "PRP0001") // = _HID: Hardware ID > > + Name (_UID, 0x00) // = _UID: Unique ID > > + Name (_CRS, ResourceTemplate () > > + { > > + Memory32Fixed (ReadWrite, 0xF2760000, 0x7D) > > + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared= ) > > + { > > + CP_GIC_SPI_CP0_EIP_RNG0 > > + } > > + }) > > + Name (_DSD, Package () { > > + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), > > + Package () { > > + Package () { "compatible", "inside-secure,safexcel= -eip76" }, > > + } > > + }) > > + } > > + } > > +} > > diff --git a/Silicon/Marvell/Documentation/PortingGuide.txt b/Silicon/M= arvell/Documentation/PortingGuide.txt > > index d5deed5..2603980 100644 > > --- a/Silicon/Marvell/Documentation/PortingGuide.txt > > +++ b/Silicon/Marvell/Documentation/PortingGuide.txt > > @@ -43,6 +43,28 @@ board. For the sake of simplicity new Marvell board = will be called "new_board". > > - Output files (and among others FD file, which may be used by ATF) a= re > > generated under directory pointed by "OUTPUT_DIRECTORY" entry (see = point 1.2). > > > > +5. ACPI support (optional) > > + - The tables can be enabled as in A70x0Db example: > > + > > + /Platforms/Marvell/Armada/AcpiTables/Arma= da70x0Db/ > > + > > + - Enable compilation of the tables in the board's .dsc file. Add it t= o the > > + output flash image contents via .fdf.inc file - path to it defined = as > > + BOARD_DXE_FV_COMPONENTS. Example: > > + Armada70x0Db.dsc: > > + > > + BOARD_DXE_FV_COMPONENTS =3D Platform/Marvell/Armada70x0Db/Armada7= 0x0Db.fdf.inc > > + > > + [Components.AARCH64] > > + Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db/AcpiTables.i= nf > > + > > + Armada70x0Db.fdf.inc: > > + > > + !if $(ARCH) =3D=3D AARCH64 > > + # ACPI support > > + INF RuleOverride =3D ACPITABLE Silicon/Marvell/Armada7k8k/AcpiT= ables/Armada70x0Db/AcpiTables.inf > > + !endif > > + > > > > COMPHY configuration > > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > > -- > > 2.7.4 > >