From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: mx.groups.io; dkim=pass header.i=@semihalf-com.20150623.gappssmtp.com header.s=20150623 header.b=LhpOxhI2; spf=none, err=SPF record not found (domain: semihalf.com, ip: 209.85.222.193, mailfrom: mw@semihalf.com) Received: from mail-qk1-f193.google.com (mail-qk1-f193.google.com [209.85.222.193]) by groups.io with SMTP; Fri, 10 May 2019 08:03:49 -0700 Received: by mail-qk1-f193.google.com with SMTP id d4so3833688qkc.9 for ; Fri, 10 May 2019 08:03:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc:content-transfer-encoding; bh=WdxfPbMMb7hfb5CSHyLpVCu0RFf3xyy++bmO+323B0g=; b=LhpOxhI2o1F/K9fuwueyu3OWyv0BUQNRPP8DXJYBNCZ/e9Pbcqwnj4BTkz6d8sIp9N AkLDvyLLxyzQuKNt93x3gYq38h1JFLxxg+VhOkR3OICActgtEnwhxW3YEXJMfJgMVqSH YZx8AdTxi3On54chXMsjh9Ney79kEEZlNVK/tlWZFdUVRmUjKhzdPV/Fe1bmDdaxS+6d wGC0/Ne4EHG59XAthPEiA0zoMEO93K2wtLoL5hj/C0wTswcGHyAPY39as2p9tX2k9DWF gkLtjw6qI4wxepHIMPHQ82gtqcxLXi1+fRudXVaztEbuFk07TvQfqCHaK/n6GXRkDyKA DoMQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc:content-transfer-encoding; bh=WdxfPbMMb7hfb5CSHyLpVCu0RFf3xyy++bmO+323B0g=; b=B2f3I0qqRfKu1cS7lqdKZuz0haLTTja+1WcqdecKP2fOw7PLxn+EMO2a/XyTc5DzGH fWuOnecGqF/sFvT2B1L77H/Lp7X46EdcN3Y2as4ScDSccyRRLUUnuQexqdt3NWSoYYDw rweRL/Z6ms4lu9s+2f1bmUXg4HTN4yf83Jxm5TyyIJ9z4A+NfTUnF5mmRSNYNSEbTB6B CHC2re24/o3FORfTqfpBAzZ0avbJdECItP+qZUlNMmbo0V1NE1wjy9BJ6aBUpLe09Pl3 TJ0tZPXW6RMa1CNGjYymdQi4VOVn3c79wDsQQxVzbn7Qn/dV8FLWCApWJCNY/673wqUC undw== X-Gm-Message-State: APjAAAWTqOFmCrlKsRrxywFztEx5dv0cbEAUSvazwnvuVeSPddgSFHNQ vI+tIl6JvKxCX5Mfs1l9qHMNBZLktC0yb4gghjUzsA== X-Google-Smtp-Source: APXvYqyNpjGs3sqkeVvLyhmRTADkIAbyW9AI+ari2u9mbY8mWA/v3bD7DOJ4ws9xdle6V702m6b2k5P96yyaODZ0DkE= X-Received: by 2002:a37:a289:: with SMTP id l131mr9182874qke.231.1557500628312; Fri, 10 May 2019 08:03:48 -0700 (PDT) MIME-Version: 1.0 References: <1557395622-32425-1-git-send-email-mw@semihalf.com> <1557395622-32425-3-git-send-email-mw@semihalf.com> <20190510145941.lsbv44eeuw67vbav@bivouac.eciton.net> In-Reply-To: <20190510145941.lsbv44eeuw67vbav@bivouac.eciton.net> From: "Marcin Wojtas" Date: Fri, 10 May 2019 17:03:37 +0200 Message-ID: Subject: Re: [edk2-platforms: PATCH 02/14] Marvell/Library: ArmadaSoCDescLib: Add PCIE information To: Leif Lindholm Cc: edk2-devel-groups-io , Ard Biesheuvel , "jsd@semihalf.com" , Grzegorz Jaszczyk , Kostya Porotchkin , Jici Gao , Rebecca Cran , Mark Kettenis Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable pt., 10 maj 2019 o 16:59 Leif Lindholm napisa=C5= =82(a): > > On Thu, May 09, 2019 at 11:53:30AM +0200, Marcin Wojtas wrote: > > This patch introduces new library callback (ArmadaSoCPcieGet ()), > > which dynamically allocates and fills array with all available PCIE > > controllers' base addresses. It is needed for the configuration of PCIE= , > > whose support will be added in the upcoming patches. > > > > Contributed-under: TianoCore Contribution Agreement 1.1 > > Signed-off-by: Marcin Wojtas > > --- > > Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCD= escLib.h | 6 +++ > > Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h = | 20 +++++++++ > > Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCD= escLib.c | 44 ++++++++++++++++++++ > > 3 files changed, 70 insertions(+) > > > > diff --git a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Ar= mada7k8kSoCDescLib.h b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDesc= Lib/Armada7k8kSoCDescLib.h > > index 8bbc5b0..e904222 100644 > > --- a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8= kSoCDescLib.h > > +++ b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8= kSoCDescLib.h > > @@ -82,6 +82,12 @@ > > #define MV_SOC_MDIO_ID(Cp) (Cp) > > > > // > > +// Platform description of PCIE > > +// > > +#define MV_SOC_PCIE_PER_CP_COUNT 3 > > +#define MV_SOC_PCIE_BASE(Index) (0x600000 + ((Index) * 0x2000= 0)) > > + > > +// > > // Platform description of PP2 NIC > > // > > #define MV_SOC_PP2_BASE(Cp) MV_SOC_CP_BASE (Cp) > > diff --git a/Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h b/Silic= on/Marvell/Include/Library/ArmadaSoCDescLib.h > > index fc17c3a..ff617e6 100644 > > --- a/Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h > > +++ b/Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h > > @@ -191,6 +191,26 @@ ArmadaSoCDescXhciGet ( > > IN OUT UINTN *DescCount > > ); > > > > +/** > > + This function returns the total number of PCIE controllers and an ar= ray > > + with their base addresses. > > + > > + @param[in out] **PcieBaseAddresses Array containing PCIE controller= s' base > > Extra space before "Array" messes up alignment. > Either drop that or add one to the lines below. > That's an effect of :%s typo fixing... Will correct in v2. Thanks, Marcin > > > + adresses. > > + @param[in out] *Count Total amount of available PCIE co= ntrollers. > > + > > + @retval EFI_SUCCESS The data were obtained successful= ly. > > + @retval EFI_OUT_OF_RESOURCES The request could not be complete= d due to a > > + lack of resources. > > + > > +**/ > > +EFI_STATUS > > +EFIAPI > > +ArmadaSoCPcieGet ( > > + IN OUT EFI_PHYSICAL_ADDRESS **PcieBaseAddresses, > > + IN OUT UINTN *Count > > + ); > > + > > // > > // PP2 NIC devices SoC description > > // > > diff --git a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Ar= mada7k8kSoCDescLib.c b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDesc= Lib/Armada7k8kSoCDescLib.c > > index 355be64..4f8a59a 100644 > > --- a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8= kSoCDescLib.c > > +++ b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8= kSoCDescLib.c > > @@ -278,6 +278,50 @@ ArmadaSoCDescAhciGet ( > > return EFI_SUCCESS; > > } > > > > +/** > > + This function returns the total number of PCIE controllers and an ar= ray > > + with their base addresses. > > + > > + @param[in out] **PcieBaseAddresses Array containing PCIE controllers= ' base > > + adresses. > > + @param[in out] *Count Total amount of available PCIE co= ntrollers. > > + > > + @retval EFI_SUCCESS The data were obtained successful= ly. > > + @retval EFI_OUT_OF_RESOURCES The request could not be complete= d due to a > > + lack of resources. > > + > > +**/ > > +EFI_STATUS > > +EFIAPI > > +ArmadaSoCPcieGet ( > > + IN OUT EFI_PHYSICAL_ADDRESS **PcieBaseAddresses, > > + IN OUT UINTN *Count > > + ) > > +{ > > + UINTN CpCount, CpIndex, Index; > > + EFI_PHYSICAL_ADDRESS *BaseAddress; > > + > > + CpCount =3D FixedPcdGet8 (PcdMaxCpCount); > > + > > + *Count =3D CpCount * MV_SOC_PCIE_PER_CP_COUNT; > > + BaseAddress =3D AllocateZeroPool (*Count * sizeof (EFI_PHYSICAL_ADDR= ESS)); > > + if (BaseAddress =3D=3D NULL) { > > + DEBUG ((DEBUG_ERROR, "%a: Cannot allocate memory\n", __FUNCTION__)= ); > > + return EFI_OUT_OF_RESOURCES; > > + } > > + > > + *PcieBaseAddresses =3D BaseAddress; > > + > > + for (CpIndex =3D 0; CpIndex < CpCount; CpIndex++) { > > + for (Index =3D 0; Index < MV_SOC_PCIE_PER_CP_COUNT; Index++) { > > + *BaseAddress =3D MV_SOC_CP_BASE (CpIndex) + MV_SOC_PCIE_BASE (In= dex); > > + BaseAddress++; > > + } > > + } > > + > > + return EFI_SUCCESS; > > +} > > + > > EFI_STATUS > > EFIAPI > > ArmadaSoCDescPp2Get ( > > -- > > 2.7.4 > >