From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2607:f8b0:4864:20::133; helo=mail-it1-x133.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org Received: from mail-it1-x133.google.com (mail-it1-x133.google.com [IPv6:2607:f8b0:4864:20::133]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id F412521AE30DB for ; Tue, 25 Sep 2018 08:41:16 -0700 (PDT) Received: by mail-it1-x133.google.com with SMTP id q70-v6so7423579itb.3 for ; Tue, 25 Sep 2018 08:41:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc:content-transfer-encoding; bh=YxripYM68qvQnEjkZhI4EL40yhq55pa2KEAxOjRxQJA=; b=dnRR3sh+7o3Gncra/h6Sc5zyi3WpV09oHoaEcgDsk7Kja6pJVfCf6INxe1c8eo5Jo5 6ZwGMqs8Q22029/+skbSd25TR5hOSz8YQRqKLp5VWR7feaxSHxJ5qqcWpz4Yu1I7gTQb 0XjkldQBRJgz7r8zLqHIYe/I3TDsvy4L89VNt+z+nywzH8GDjcIFumGeQoSgZoxVfYdC CC8dPbPB0Z5p8g2ugm1a742oQgrfO0xauPuMm/Gj3gYZtg2cqcfcp75vCePlK+Ew81R4 m7ENpDU5G31s8DHZhwJkqboPHJVzyJflaVObuMaMDm/aeXdkDFIiALkRBb9z9gBRyR4S KI1g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc:content-transfer-encoding; bh=YxripYM68qvQnEjkZhI4EL40yhq55pa2KEAxOjRxQJA=; b=JGaEgTmExcaWNz9dprroQdig4Bn3LBXFjU1fPIB+nkI+QgonQiTyxSn+wkSdKf1CKL 6bjBzYM6fkVpgQaRK/ecCTpTeXWk6okGB1kp6KFvBdrWB68+pimTZO5PD5VxRUUs5/oB gwylechpuwl/zMwvxnz1e2929a5gPnGXJXDUCNmERNGG/9/TKL8n1ltddqo3Qbat5YHk HvHQfT7vluySB6VtaLCgY1D/nL8kcT7MxIi6dXGfxdpR0aQzCI5IwiHHyGPqFofE/ytP i6vsqLlC6cKUjaTUxxNH6DRb9aZHFI1iAvlE4XvHhxYL6UTkI72kvAEmd1KXBrijybuj IdBg== X-Gm-Message-State: ABuFfohP9J9DRel7287qZMDb8qmXziY8vopM+3+QX1d549aO1P/ReJJw ydicY7Md5SrDl3XxC4ibLWW+L/RlWfXoixl6mcbyww== X-Google-Smtp-Source: ACcGV63e8z9Ol8SLKh3kAk+jnoJFpdFPLcxptrvoG2VXGJ9wK7g5yAwEaFdEM4KlQHnaB4rEG3kbWvFtN0kkjBH+z/k= X-Received: by 2002:a24:25c1:: with SMTP id g184-v6mr1243681itg.120.1537890075473; Tue, 25 Sep 2018 08:41:15 -0700 (PDT) MIME-Version: 1.0 References: <1536631417-39920-1-git-send-email-star.zeng@intel.com> <734D49CCEBEEF84792F5B80ED585239D5BE028B7@SHSMSX104.ccr.corp.intel.com> In-Reply-To: <734D49CCEBEEF84792F5B80ED585239D5BE028B7@SHSMSX104.ccr.corp.intel.com> From: Marcin Wojtas Date: Tue, 25 Sep 2018 17:41:02 +0200 Message-ID: To: "Zeng, Star" , Ard Biesheuvel Cc: edk2-devel-01 , "Ni, Ruiyu" , fei1.wang@intel.com, Grzegorz Jaszczyk , nadavh@marvell.com Subject: Re: [PATCH] MdeModulePkg XhciDxe: Set HSEE Bit if SERR# Enable Bit is set X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 25 Sep 2018 15:41:17 -0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Hi Star, Ard With this patch, my platforms which use NonDiscoverableDevices layer for supporting generic Xhci controller, fail in a strange way: "Synchronous Exception at 0x000000003F910AFC PC 0x00003F910AFC (0x00003F908000+0x00008AFC) [ 0] DxeCore.dll PC 0x00003F910AE0 (0x00003F908000+0x00008AE0) [ 0] DxeCore.dll PC 0x00003F91BDF4 (0x00003F908000+0x00013DF4) [ 0] DxeCore.dll PC 0x0000BF5BD000 (0x0000BF5AF000+0x0000E000) [ 1] XhciDxe.dll PC 0xAFAFAFAFAFAFAFAF Recursive exception occurred while dumping the CPU state" I've quickly checked and although XhcSetHsee() is eventually called from XhcDriverBindingStart() sequence, below line is not even executed: XhcSetOpRegBit (Xhc, XHC_USBCMD_OFFSET, XHC_USBCMD_HSEE); The XhcDriverBindingStart() returns EFI_SUCCESS and we get the sync abort right afterwards (haven't found exact place yet). What makes the difference is commenting out in XhcSetHsee(): // Status =3D PciIo->Pci.Read ( // PciIo, // EfiPciIoWidthUint16, // PCI_COMMAND_OFFSET, // sizeof (XhciCmd), // &XhciCmd // ); With that everything keeps working as usual. I'd appreciate any hint. Best regards. Marcin wt., 11 wrz 2018 o 04:30 Ni, Ruiyu napisa=C5=82(a): > > Reviewed-by: Ruiyu Ni > > Thanks/Ray > > > -----Original Message----- > > From: Zeng, Star > > Sent: Tuesday, September 11, 2018 10:04 AM > > To: edk2-devel@lists.01.org > > Cc: Zeng, Star ; Ni, Ruiyu ; W= ang, > > Jian J ; Wang, Fei1 > > Subject: [PATCH] MdeModulePkg XhciDxe: Set HSEE Bit if SERR# Enable Bit= is > > set > > > > When the HSEE in the USBCMD bit is a '1' and the HSE bit in the USBSTS > > register is a '1', the xHC shall assert out-of-band error signaling to = the host > > and assert the SERR# pin. > > To prevent masking any potential issues with SERR, this patch is to set > > USBCMD Host System Error Enable(HSEE) Bit if PCICMD SERR# Enable Bit is > > set. > > > > Cc: Ruiyu Ni > > Cc: Jian J Wang > > Cc: Fei1 Wang > > Contributed-under: TianoCore Contribution Agreement 1.1 > > Signed-off-by: Star Zeng > > --- > > MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.c | 41 > > ++++++++++++++++++++++++++++++++++ > > 1 file changed, 41 insertions(+) > > > > diff --git a/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.c > > b/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.c > > index 5f0736a516b6..89f073e1d83f 100644 > > --- a/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.c > > +++ b/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.c > > @@ -587,6 +587,39 @@ XhcIsSysError ( > > } > > > > /** > > + Set USBCMD Host System Error Enable(HSEE) Bit if PCICMD SERR# Enable > > Bit is set. > > + > > + The USBCMD HSEE Bit will be reset to default 0 by USBCMD Host Contro= ller > > Reset(HCRST). > > + This function is to set USBCMD HSEE Bit if PCICMD SERR# Enable Bit i= s set. > > + > > + @param Xhc The XHCI Instance. > > + > > +**/ > > +VOID > > +XhcSetHsee ( > > + IN USB_XHCI_INSTANCE *Xhc > > + ) > > +{ > > + EFI_STATUS Status; > > + EFI_PCI_IO_PROTOCOL *PciIo; > > + UINT16 XhciCmd; > > + > > + PciIo =3D Xhc->PciIo; > > + Status =3D PciIo->Pci.Read ( > > + PciIo, > > + EfiPciIoWidthUint16, > > + PCI_COMMAND_OFFSET, > > + sizeof (XhciCmd), > > + &XhciCmd > > + ); > > + if (!EFI_ERROR (Status)) { > > + if ((XhciCmd & EFI_PCI_COMMAND_SERR) !=3D 0) { > > + XhcSetOpRegBit (Xhc, XHC_USBCMD_OFFSET, XHC_USBCMD_HSEE); > > + } > > + } > > +} > > + > > +/** > > Reset the XHCI host controller. > > > > @param Xhc The XHCI Instance. > > @@ -628,6 +661,14 @@ XhcResetHC ( > > // > > gBS->Stall (XHC_1_MILLISECOND); > > Status =3D XhcWaitOpRegBit (Xhc, XHC_USBCMD_OFFSET, > > XHC_USBCMD_RESET, FALSE, Timeout); > > + > > + if (!EFI_ERROR (Status)) { > > + // > > + // The USBCMD HSEE Bit will be reset to default 0 by USBCMD HCRS= T. > > + // Set USBCMD HSEE Bit if PCICMD SERR# Enable Bit is set. > > + // > > + XhcSetHsee (Xhc); > > + } > > } > > > > return Status; > > -- > > 2.7.0.windows.1 > > _______________________________________________ > edk2-devel mailing list > edk2-devel@lists.01.org > https://lists.01.org/mailman/listinfo/edk2-devel