From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-io0-x232.google.com (mail-io0-x232.google.com [IPv6:2607:f8b0:4001:c06::232]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 3709421EB88E0 for ; Fri, 1 Sep 2017 08:22:17 -0700 (PDT) Received: by mail-io0-x232.google.com with SMTP id f99so3331167ioi.3 for ; Fri, 01 Sep 2017 08:25:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc; bh=m2MNeI6mcXY9w1AzxS1zWNXoiWp4HUTK4ZtnuvpTCAc=; b=wZ1h6yYvKNyhQoNBOe2PDcVM6Fpv+DhRgpvhkSFA3rHhPbTYK2fOFi3wSc3++8W2o5 eFGwDb86GjbwxsYD798FCy1st3RYFPsqmP1cGQUR7jj0rndxsayeh5js8p9OMnQkjKuV FnbJ09S8BLa32yfRVfIBIBmvBw1EiX/F2/WReumJbmehfTnsff3r3P4VLeEhYbxBQim9 Xb7y6+iOCr5qUtLxmEkGAMY3HmVArKTEhXig8Ixyf/wSJ1YaCw3wV4Y2pWOoE8rBOgLj gxNAltBlnrRUziDnwuI098XqhTFPq/jiM7cvTk6E7d174YgTwgp7J4l/bCG/ChaZVYhy 6VEA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=m2MNeI6mcXY9w1AzxS1zWNXoiWp4HUTK4ZtnuvpTCAc=; b=EOgGmH9HyWXlaoKSttHlYWXLXVETWaAl6ruroX68C/yQuivzgcz+ZrLdPZA8QE6GT7 52PVrMOLFLTTPXGp9C9I0zRPJqlAtYkihd1U2clv2yqkRR+ujqn1O5TDVC7rXeCI7PiF A7c3yNZqn9QEjWB1kCUY7mO1Rrg2ZCRp8gvn42+RuZYDTAm4lrSnAktmfJg/2Yc61KYc 7PoG9sn+0sUFyl7MSR4WupQee1DZ30xSIe4gZ8WlLPewC1NZq+JET7tIfJ+SimsCaW5E PSXU6YzihtOP966Dzc6Ue1ID+gA4IIbiUgZOdAC7qzy1FtFvfoXkiHCrhqdc/v95/WKA NowA== X-Gm-Message-State: AHPjjUjjdVVBi7lPIMkurfi8O4lG90fH8ofLWEiAF+eIYX7HnkSWc6Fz GKNhsPd8976RH5/rIgLI8aLaXbgrgQPF X-Google-Smtp-Source: ADKCNb4SFAi+aiKCCaQzCyeeLp/33qJ2DSnJ0bUbJAX9VKHkHLWTP1TbmAhCDrtkQPi2KVMU6l4haVuQZLpSjkn/6WY= X-Received: by 10.36.81.85 with SMTP id s82mr1094565ita.79.1504279501239; Fri, 01 Sep 2017 08:25:01 -0700 (PDT) MIME-Version: 1.0 Received: by 10.107.190.199 with HTTP; Fri, 1 Sep 2017 08:25:00 -0700 (PDT) In-Reply-To: <20170901152144.mo5q4nabvqgbqic6@bivouac.eciton.net> References: <1504271303-1782-1-git-send-email-mw@semihalf.com> <1504271303-1782-10-git-send-email-mw@semihalf.com> <20170901152144.mo5q4nabvqgbqic6@bivouac.eciton.net> From: Marcin Wojtas Date: Fri, 1 Sep 2017 17:25:00 +0200 Message-ID: To: Leif Lindholm Cc: edk2-devel-01 , Ard Biesheuvel , nadavh@marvell.com, Neta Zur Hershkovits , Kostya Porotchkin , Hua Jing , Alexander Graf , semihalf-dabros-jan Subject: Re: [platforms: PATCH 09/11] Drivers/Spi/Devices/MvSpiFlash: Fix usage of erase size parameter X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 01 Sep 2017 15:22:17 -0000 Content-Type: text/plain; charset="UTF-8" 2017-09-01 17:21 GMT+02:00 Leif Lindholm : > On Fri, Sep 01, 2017 at 03:08:21PM +0200, Marcin Wojtas wrote: >> Although, hitherto support allowed for using configurable EraseSize, >> the erase command was fixed to CMD_ERASE_64K. Also it was >> assumed that EraseSize equals SectorSize, which is not true >> for some flash devices. > > Another thing I immediately wish I had never learned. > Thanks :/ Do you mean the code or flash quirks? :) > >> Fix both issues by adding new PCD >> (gMarvellTokenSpaceGuid.PcdSpiFlashPageSize) and using >> this parameter properly in MvSpiFlashUpdate routine instead >> of the EraseSize. Also erase command is adjusted to the settings. >> Update PortingGuide accordingly. >> >> Contributed-under: TianoCore Contribution Agreement 1.1 >> Signed-off-by: Marcin Wojtas >> --- >> Platform/Marvell/Documentation/PortingGuide.txt | 3 +++ >> Platform/Marvell/Drivers/Spi/Devices/MvSpiFlash.c | 26 +++++++++++++++++----- >> Platform/Marvell/Drivers/Spi/Devices/MvSpiFlash.h | 6 +++++ >> .../Marvell/Drivers/Spi/Devices/MvSpiFlash.inf | 1 + >> Platform/Marvell/Marvell.dec | 1 + >> 5 files changed, 31 insertions(+), 6 deletions(-) >> >> diff --git a/Platform/Marvell/Documentation/PortingGuide.txt b/Platform/Marvell/Documentation/PortingGuide.txt >> index 3b79bd2..f637fee 100644 >> --- a/Platform/Marvell/Documentation/PortingGuide.txt >> +++ b/Platform/Marvell/Documentation/PortingGuide.txt >> @@ -297,6 +297,9 @@ Folowing PCDs for spi flash driver configuration must be set properly: >> - gMarvellTokenSpaceGuid.PcdSpiFlashPageSize >> (Size of SPI flash page) >> >> + - gMarvellTokenSpaceGuid.PcdSpiFlashSectorSize >> + (Size of SPI flash sector, 65536 bytes by default) >> + >> - gMarvellTokenSpaceGuid.PcdSpiFlashId >> (Id of SPI flash) >> >> diff --git a/Platform/Marvell/Drivers/Spi/Devices/MvSpiFlash.c b/Platform/Marvell/Drivers/Spi/Devices/MvSpiFlash.c >> index 9a04493..f3fdba4 100755 >> --- a/Platform/Marvell/Drivers/Spi/Devices/MvSpiFlash.c >> +++ b/Platform/Marvell/Drivers/Spi/Devices/MvSpiFlash.c >> @@ -191,7 +191,21 @@ MvSpiFlashErase ( >> return EFI_DEVICE_ERROR; >> } >> >> - Cmd[0] = CMD_ERASE_64K; >> + switch (EraseSize) { >> + case SPI_ERASE_SIZE_4K: >> + Cmd[0] = CMD_ERASE_4K; >> + break; >> + case SPI_ERASE_SIZE_32K: >> + Cmd[0] = CMD_ERASE_32K; >> + break; >> + case SPI_ERASE_SIZE_64K: >> + Cmd[0] = CMD_ERASE_64K; >> + break; >> + default: >> + DEBUG ((DEBUG_ERROR, "MvSpiFlash: Invalid EraseSize parameter\n")); >> + return EFI_INVALID_PARAMETER; >> + } >> + >> while (Length) { >> EraseAddr = Offset; >> >> @@ -353,14 +367,14 @@ MvSpiFlashUpdate ( >> ) >> { >> EFI_STATUS Status; >> - UINT64 EraseSize, ToUpdate, Scale = 1; >> + UINT64 SectorSize, ToUpdate, Scale = 1; >> UINT8 *TmpBuf, *End; >> >> - EraseSize = PcdGet64 (PcdSpiFlashEraseSize); >> + SectorSize = PcdGet64 (PcdSpiFlashSectorSize); >> >> End = Buf + ByteCount; >> >> - TmpBuf = (UINT8 *)AllocateZeroPool (EraseSize); >> + TmpBuf = (UINT8 *)AllocateZeroPool (SectorSize); >> if (TmpBuf == NULL) { >> DEBUG((DEBUG_ERROR, "SpiFlash: Cannot allocate memory\n")); >> return EFI_OUT_OF_RESOURCES; >> @@ -370,9 +384,9 @@ MvSpiFlashUpdate ( >> Scale = (End - Buf) / 100; >> >> for (; Buf < End; Buf += ToUpdate, Offset += ToUpdate) { >> - ToUpdate = MIN((UINT64)(End - Buf), EraseSize); >> + ToUpdate = MIN((UINT64)(End - Buf), SectorSize); >> Print (L" \rUpdating, %d%%", 100 - (End - Buf) / Scale); >> - Status = MvSpiFlashUpdateBlock (Slave, Offset, ToUpdate, Buf, TmpBuf, EraseSize); >> + Status = MvSpiFlashUpdateBlock (Slave, Offset, ToUpdate, Buf, TmpBuf, SectorSize); >> >> if (EFI_ERROR (Status)) { >> DEBUG((DEBUG_ERROR, "SpiFlash: Error while updating\n")); >> diff --git a/Platform/Marvell/Drivers/Spi/Devices/MvSpiFlash.h b/Platform/Marvell/Drivers/Spi/Devices/MvSpiFlash.h >> index 3889643..646598a 100755 >> --- a/Platform/Marvell/Drivers/Spi/Devices/MvSpiFlash.h >> +++ b/Platform/Marvell/Drivers/Spi/Devices/MvSpiFlash.h >> @@ -57,6 +57,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. >> #define CMD_READ_ARRAY_FAST 0x0b >> #define CMD_PAGE_PROGRAM 0x02 >> #define CMD_BANK_WRITE 0xc5 >> +#define CMD_ERASE_4K 0x20 >> +#define CMD_ERASE_32K 0x52 >> #define CMD_ERASE_64K 0xd8 >> #define CMD_4B_ADDR_ENABLE 0xb7 >> >> @@ -66,6 +68,10 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. >> #define SPI_TRANSFER_BEGIN 0x01 // Assert CS before transfer >> #define SPI_TRANSFER_END 0x02 // Deassert CS after transfers >> >> +#define SPI_ERASE_SIZE_4K 4096 >> +#define SPI_ERASE_SIZE_32K 32768 >> +#define SPI_ERASE_SIZE_64K 65536 >> + > > Maybe just replace these with SIZE_4KB, SIZE_32KB and SIZE_64KB? > Sure, will do. Marcin