From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-qk1-f196.google.com (mail-qk1-f196.google.com [209.85.222.196]) by mx.groups.io with SMTP id smtpd.web12.2257.1589843390251241660 for ; Mon, 18 May 2020 16:09:50 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@semihalf-com.20150623.gappssmtp.com header.s=20150623 header.b=dy6WltLd; spf=none, err=SPF record not found (domain: semihalf.com, ip: 209.85.222.196, mailfrom: mw@semihalf.com) Received: by mail-qk1-f196.google.com with SMTP id y22so12401420qki.3 for ; Mon, 18 May 2020 16:09:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc:content-transfer-encoding; bh=0b8MxpGP8Z3XOOCZzhNbN0obX6oqYH7wNCJJbuL0C0A=; b=dy6WltLd0Bs6lKggbLtucYBpsShJzGDTKAur9S4tBQN6tv3uUGxuy1xBZ6E8ltXNpf 4ScWd9C8uVpmgrQnM7dQHhe5ntuqhaMV+9EFeYZJpuN1RU9K8QFzHqO/Yj6sy9hqTeVY SWN1hl85QkqeN0gZbZq6ZfGfL3GCvZGU300WArvIqr5AtPFDv0FUlL3RyRGyGeoDd1B3 YLyQ1Rva0GzAGhctQ4c3uyrN+RauWhHdHWnzR555qhkHi6FiDDUeONthTpm26+AvkGIL sqULLgjQatL6uV+yc1DOVg39cm1rf6fUeZpoX5Qf9HdGJSZOhidEh9CoJzZbMq29BbDL xbwQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc:content-transfer-encoding; bh=0b8MxpGP8Z3XOOCZzhNbN0obX6oqYH7wNCJJbuL0C0A=; b=m9NrQ9nAcj5MTi7+1U4pOsjTt32Ba3episHze1OYQIpD2lgtuzaJFwHRyoyGQ7v6ya LrbVRIrG5m5LvjFsUh1SfwKRTbgvmDIo391EsVeYeNrG4JPqKf73xj2l244fs6Y18GGF /7bh6QQhTHoNEMCHB/Lsili/Fpy/4EAi2cw4CvBcFVLuTcJ2ciCbwODxU2zJ9XPvHdHa 4CjMstB2B+mzk9MbBvYziFEa7gjwmSB0O3iSRSt62FqR4GOJmTsDqkL/FdAA46OiA5kR JhEIjZmnBe2z3nse5QanisoZ/k3wHRKVV6tIoyUmAhULFjX2cbqwyh0FqFAk+StqbhTD Y2QA== X-Gm-Message-State: AOAM530R0WPNN77zhdwe1pRGitycILb0BAh1oSxykouskzyk5OTA9CyE 8kx4TkagOL3WaHgtKwkD9zmVLgsCu0aBh0M8CH5ddQ== X-Google-Smtp-Source: ABdhPJyUo7Xzh79hse/dv9OPvQRi7S/L2ooCMU+lm8+S/ErhtCV2FvMrFuX8XtoUUj7BxP7gBhgtFuJ7IuKKzxvecbM= X-Received: by 2002:a37:a0d5:: with SMTP id j204mr18354223qke.128.1589843389110; Mon, 18 May 2020 16:09:49 -0700 (PDT) MIME-Version: 1.0 References: <1589576758-28501-1-git-send-email-mw@semihalf.com> <1589576758-28501-2-git-send-email-mw@semihalf.com> <20200518171221.GC10467@vanye> <20200518181613.GJ10467@vanye> In-Reply-To: <20200518181613.GJ10467@vanye> From: "Marcin Wojtas" Date: Tue, 19 May 2020 01:09:37 +0200 Message-ID: Subject: Re: [edk2-platforms: PATCH v2 1/3] Marvell/Library: UtmiLib: update USB2.0 analog settings To: Leif Lindholm Cc: edk2-devel-groups-io , ard.biesheuvel@arm.com, "jsd@semihalf.com" , Grzegorz Jaszczyk , Kostya Porotchkin Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Hi Leif, pon., 18 maj 2020 o 20:16 Leif Lindholm napisa=C5=82(a)= : > > On Mon, May 18, 2020 at 20:11:49 +0200, Marcin Wojtas wrote: > > Hi Leif, > > > > pon., 18 maj 2020 o 19:12 Leif Lindholm napisa=C5= =82(a): > > > > > > On Fri, May 15, 2020 at 23:05:56 +0200, Marcin Wojtas wrote: > > > > This patch introduce following modifications, allowing to > > > > overcome the instabilities observed with certain USB2.0 endpoints: > > > > * Add additional step which enables the Impedance and PLL calibrati= on. > > > > * Enable old squelch detector instead of the new analog squelch det= ector > > > > circuit and update host disconnect threshold value. > > > > * Update LS TX driver strength coarse and fine adjustment values. > > > > > > > > Signed-off-by: Grzegorz Jaszczyk > > > > Signed-off-by: Marcin Wojtas > > > > > > I'm OK with the current version of the code, but just noticed this. > > > No one can give Signed-off-by for another. > > > If Grzegorz is the author, that should be noted in a From: tag. Git > > > format-patch does this automatically if the commit's Author metadata > > > is set. > > > > > > This applies to all 3 patches. > > > > > > > The 3/3 has only only my signed-off tag (and my authorship). > > OK, I admit it, I was lazy and spotted this and only checked 2/3 and > assumed it was all of them :) > > > Regarding the first 2, I did the actual change, but it was based on > > the original U-Boot patch from Grzegorz. How about, instead of the tag, > > I give him a credit in a following way: > > > > Based on the original U-Boot patch from Grzegorz Jaszczyk > > > > Would that work for you? > > I have no objections to that as such, but perhaps a link to the patch > posting in an email archive, or the commit in a git repo, would be > more generically useful. > The patches have not yet made their way to the mainline U-Boot and are not public. I talked to Grzegorz and he's ok to withdraw the credit lines - changes are too minor to spend so much time on such detail. Thanks, Marcin > > > > > > > > > --- > > > > Silicon/Marvell/Library/UtmiPhyLib/UtmiPhyLib.h | 10 +++++++++- > > > > Silicon/Marvell/Library/UtmiPhyLib/UtmiPhyLib.c | 18 +++++++++++++= +---- > > > > 2 files changed, 23 insertions(+), 5 deletions(-) > > > > > > > > diff --git a/Silicon/Marvell/Library/UtmiPhyLib/UtmiPhyLib.h b/Sili= con/Marvell/Library/UtmiPhyLib/UtmiPhyLib.h > > > > index 20e3133..8659110 100644 > > > > --- a/Silicon/Marvell/Library/UtmiPhyLib/UtmiPhyLib.h > > > > +++ b/Silicon/Marvell/Library/UtmiPhyLib/UtmiPhyLib.h > > > > @@ -44,6 +44,10 @@ SPDX-License-Identifier: BSD-2-Clause-Patent > > > > #define UTMI_CALIB_CTRL_REG 0x8 > > > > #define UTMI_CALIB_CTRL_IMPCAL_VTH_OFFSET 8 > > > > #define UTMI_CALIB_CTRL_IMPCAL_VTH_MASK (0x7 << UTMI_CAL= IB_CTRL_IMPCAL_VTH_OFFSET) > > > > +#define UTMI_CALIB_CTRL_IMPCAL_START_OFFSET 13 > > > > +#define UTMI_CALIB_CTRL_IMPCAL_START_MASK (0x1 << UTMI_CAL= IB_CTRL_IMPCAL_START_OFFSET) > > > > +#define UTMI_CALIB_CTRL_PLLCAL_START_OFFSET 22 > > > > +#define UTMI_CALIB_CTRL_PLLCAL_START_MASK (0x1 << UTMI_CAL= IB_CTRL_PLLCAL_START_OFFSET) > > > > #define UTMI_CALIB_CTRL_IMPCAL_DONE_OFFSET 23 > > > > #define UTMI_CALIB_CTRL_IMPCAL_DONE_MASK (0x1 << UTMI_CAL= IB_CTRL_IMPCAL_DONE_OFFSET) > > > > #define UTMI_CALIB_CTRL_PLLCAL_DONE_OFFSET 31 > > > > @@ -54,8 +58,12 @@ SPDX-License-Identifier: BSD-2-Clause-Patent > > > > #define UTMI_TX_CH_CTRL_DRV_EN_LS_MASK (0xf << UTMI_TX_= CH_CTRL_DRV_EN_LS_OFFSET) > > > > #define UTMI_TX_CH_CTRL_IMP_SEL_LS_OFFSET 16 > > > > #define UTMI_TX_CH_CTRL_IMP_SEL_LS_MASK (0xf << UTMI_TX_= CH_CTRL_IMP_SEL_LS_OFFSET) > > > > +#define UTMI_TX_CH_CTRL_AMP_OFFSET 20 > > > > +#define UTMI_TX_CH_CTRL_AMP_MASK (0x7 << UTMI_TX_= CH_CTRL_AMP_OFFSET) > > > > > > > > #define UTMI_RX_CH_CTRL0_REG 0x14 > > > > +#define UTMI_RX_CH_CTRL0_DISCON_THRESH_OFFSET 8 > > > > +#define UTMI_RX_CH_CTRL0_DISCON_THRESH_MASK (0x3 << UTMI_RX_= CH_CTRL0_DISCON_THRESH_OFFSET) > > > > #define UTMI_RX_CH_CTRL0_SQ_DET_OFFSET 15 > > > > #define UTMI_RX_CH_CTRL0_SQ_DET_MASK (0x1 << UTMI_RX_= CH_CTRL0_SQ_DET_OFFSET) > > > > #define UTMI_RX_CH_CTRL0_SQ_ANA_DTC_OFFSET 28 > > > > @@ -63,7 +71,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent > > > > > > > > #define UTMI_RX_CH_CTRL1_REG 0x18 > > > > #define UTMI_RX_CH_CTRL1_SQ_AMP_CAL_OFFSET 0 > > > > -#define UTMI_RX_CH_CTRL1_SQ_AMP_CAL_MASK (0x3 << UTMI_RX_= CH_CTRL1_SQ_AMP_CAL_OFFSET) > > > > +#define UTMI_RX_CH_CTRL1_SQ_AMP_CAL_MASK (0x7 << UTMI_RX_= CH_CTRL1_SQ_AMP_CAL_OFFSET) > > > > #define UTMI_RX_CH_CTRL1_SQ_AMP_CAL_EN_OFFSET 3 > > > > #define UTMI_RX_CH_CTRL1_SQ_AMP_CAL_EN_MASK (0x1 << UTMI_RX_= CH_CTRL1_SQ_AMP_CAL_EN_OFFSET) > > > > > > > > diff --git a/Silicon/Marvell/Library/UtmiPhyLib/UtmiPhyLib.c b/Sili= con/Marvell/Library/UtmiPhyLib/UtmiPhyLib.c > > > > index 3881ebd..42f38db 100644 > > > > --- a/Silicon/Marvell/Library/UtmiPhyLib/UtmiPhyLib.c > > > > +++ b/Silicon/Marvell/Library/UtmiPhyLib/UtmiPhyLib.c > > > > @@ -118,23 +118,33 @@ UtmiPhyConfig ( > > > > > > > > /* Impedance Calibration Threshold Setting */ > > > > RegSet (UtmiBaseAddr + UTMI_CALIB_CTRL_REG, > > > > - 0x6 << UTMI_CALIB_CTRL_IMPCAL_VTH_OFFSET, > > > > + 0x7 << UTMI_CALIB_CTRL_IMPCAL_VTH_OFFSET, > > > > UTMI_CALIB_CTRL_IMPCAL_VTH_MASK); > > > > > > > > + /* Start Impedance and PLL Calibration */ > > > > + Mask =3D UTMI_CALIB_CTRL_PLLCAL_START_MASK; > > > > + Data =3D (0x1 << UTMI_CALIB_CTRL_PLLCAL_START_OFFSET); > > > > + Mask |=3D UTMI_CALIB_CTRL_IMPCAL_START_MASK; > > > > + Data |=3D (0x1 << UTMI_CALIB_CTRL_IMPCAL_START_OFFSET); > > > > + RegSet (UtmiBaseAddr + UTMI_CALIB_CTRL_REG, Data, Mask); > > > > + > > > > /* Set LS TX driver strength coarse control */ > > > > Mask =3D UTMI_TX_CH_CTRL_DRV_EN_LS_MASK; > > > > Data =3D 0x3 << UTMI_TX_CH_CTRL_DRV_EN_LS_OFFSET; > > > > - /* Set LS TX driver fine adjustment */ > > > > + Mask |=3D UTMI_TX_CH_CTRL_AMP_MASK; > > > > + Data |=3D 0x4 << UTMI_TX_CH_CTRL_AMP_OFFSET; > > > > Mask |=3D UTMI_TX_CH_CTRL_IMP_SEL_LS_MASK; > > > > Data |=3D 0x3 << UTMI_TX_CH_CTRL_IMP_SEL_LS_OFFSET; > > > > RegSet (UtmiBaseAddr + UTMI_TX_CH_CTRL_REG, Data, Mask); > > > > > > > > /* Enable SQ */ > > > > Mask =3D UTMI_RX_CH_CTRL0_SQ_DET_MASK; > > > > - Data =3D 0x0 << UTMI_RX_CH_CTRL0_SQ_DET_OFFSET; > > > > + Data =3D 0x1 << UTMI_RX_CH_CTRL0_SQ_DET_OFFSET; > > > > /* Enable analog squelch detect */ > > > > Mask |=3D UTMI_RX_CH_CTRL0_SQ_ANA_DTC_MASK; > > > > - Data |=3D 0x1 << UTMI_RX_CH_CTRL0_SQ_ANA_DTC_OFFSET; > > > > + Data |=3D 0x0 << UTMI_RX_CH_CTRL0_SQ_ANA_DTC_OFFSET; > > > > + Mask |=3D UTMI_RX_CH_CTRL0_DISCON_THRESH_MASK; > > > > + Data |=3D 0x0 << UTMI_RX_CH_CTRL0_DISCON_THRESH_OFFSET; > > > > RegSet (UtmiBaseAddr + UTMI_RX_CH_CTRL0_REG, Data, Mask); > > > > > > > > /* Set External squelch calibration number */ > > > > -- > > > > 2.7.4 > > > >