From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: mx.groups.io; dkim=pass header.i=@semihalf-com.20150623.gappssmtp.com header.s=20150623 header.b=bGwpsHwf; spf=none, err=SPF record not found (domain: semihalf.com, ip: 209.85.160.196, mailfrom: mw@semihalf.com) Received: from mail-qt1-f196.google.com (mail-qt1-f196.google.com [209.85.160.196]) by groups.io with SMTP; Thu, 25 Apr 2019 05:35:27 -0700 Received: by mail-qt1-f196.google.com with SMTP id s10so13340856qtc.11 for ; Thu, 25 Apr 2019 05:35:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc:content-transfer-encoding; bh=Bk3Wk+UKfpf7j8I029kSYyW/+TP49Ze9QpM5Sulw5FM=; b=bGwpsHwfMvnKaPG+kJc47HlVU/nvkkDkxAzsh+Cj0xfmK98ORsiwOShhnuTZSDn4nu J7+n6ejVUrCyieq2+fxbGhNkigPKSZ/VhG3ekqaO5k0wKrOT5oZdWRcbL8e4qEL9maM2 ZmIhrwCjAIv9aDjZxNDWPViSsFAAgIaafBVK0h1GJ3VK8BDeHvyScFAtgiLbO82bsfff KAPiCA4AG3kIqiiYz6w6F//aizApjUJlN/HCC+oJbZfFKnvQf3wyku2YJuby9PGsWFNL ZJWN+jl6QEtumwUU+WiOAywDXFWNLl9ZVPSMATEsdBiWXAYZJf3IOpIL9pMZ3VgGFri3 cUgA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc:content-transfer-encoding; bh=Bk3Wk+UKfpf7j8I029kSYyW/+TP49Ze9QpM5Sulw5FM=; b=qjPPIl5xt1a3pBfatGMJj8X7s/HY0JDoWO52mwGq9J5kXve41EzezopwxJdiwQGjVw vpi0Eanh3iYDnm6ae/g5LPOYvPdgL72A+Eys9eEhsYqHwQxIdlu/FZ9gx4JccGo8Zgxd mR2a8gbafSBBOAXOMFpmt8w3vV5yjVj8vDl01Qyaza8H7CJDOmOy/lfBadRqaXgn7cHX 2+6CaJWhXOr/SzMoGuidoKflOGV5cmwCvoL/i+5q6zZUGaaomRdHWhh1chBDU2TPymwE oKaB3ovZvVtvA3O8iwronHj0cBVTdFAf8roJjYiIyTMTyOl4gs+V9djA113F3keS6b0u +uLg== X-Gm-Message-State: APjAAAXuLpVF69WhLrjamV3V4x4sClV0AliZQxxmAmaf5qQXs7pD7Zrh lET/R5IDe0ickPxiSivnD3h4mwrLrcsoYBTpfbL/rg== X-Google-Smtp-Source: APXvYqwJZMCqNNhU8jfozyLj7W8hxNNfowi6vAK4NoLYxd1YZa5VbnJJjI4VVG6y1SpL39oPpRmsy/Kir95oo1Jq7t4= X-Received: by 2002:ac8:4a95:: with SMTP id l21mr24265775qtq.42.1556195726358; Thu, 25 Apr 2019 05:35:26 -0700 (PDT) MIME-Version: 1.0 References: <1556191704-28834-1-git-send-email-mw@semihalf.com> <20190425120123.55ytftaqcbmzdzri@bivouac.eciton.net> In-Reply-To: <20190425120123.55ytftaqcbmzdzri@bivouac.eciton.net> From: "Marcin Wojtas" Date: Thu, 25 Apr 2019 14:35:12 +0200 Message-ID: Subject: Re: [edk2-platforms: PATCH v3 0/4] Armada7k8k FVB improvements To: Leif Lindholm Cc: edk2-devel-groups-io , Ard Biesheuvel , "jsd@semihalf.com" , Grzegorz Jaszczyk , Kostya Porotchkin , Jici Gao Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Hi Leif, czw., 25 kwi 2019 o 14:01 Leif Lindholm napisa= =C5=82(a): > > Hi Marcin, > > Just to be awkward - edk2-platforms (and edk2-non-osi) have not yet > been relicensed, so we still need "contributed-under" here. > > For this series, can you confirm to the list that this is indeed > Contributed-under: TianoCore Contribution Agreement 1.1 > ? If so, we can fix that up before committing. > Yes, I confirm that - if possible fix-up. Actually I removed those lines right before sending :) Best regards, Marcin > I'll start looking into what we need to do for a license transition > for edk2-platforms master next week. > > Best Regards, > > Leif > > On Thu, Apr 25, 2019 at 01:28:20PM +0200, Marcin Wojtas wrote: > > Hi, > > > > The third version of the patchset cleans up the dependencies between > > the SPI drivers, so that now they explicitly rely on the protocols' > > instead of BEFORE statements and modules GUIDs. Also force dependency > > between FTW and MvFvbDxe using library NULL resolution. > > > > The patches are available in the github: > > https://github.com/MarvellEmbeddedProcessors/edk2-open-platform/commits= /fvb-upstream-r20190425 > > > > I'm looking forward to your comments or remarks. > > > > Best regards, > > Marcin > > > > Changelog: > > v2->v3 > > > > 3/4 (new patch) > > * Clean-up MvSpiFlashDxe / MvSpiOrionDxe / MvFvbDxe dependencies and > > rely on the protocols' GUIDs > > > > 4/4 > > * Force dependency for loading FTW driver > > > > v1->v2 > > * Replace clock-enabling patch with PEI phase FV cleanup > > > > Hanna Hawa (1): > > Marvell/Drivers: MvFvbDxe: Change Pcd parameters to be 64 bit > > > > Kornel Duleba (1): > > Marvell/Drivers: MvFvbDxe: Introduce non-mmio mode > > > > Marcin Wojtas (2): > > Marvell/Armada7k8k: Cleanup PEI phase FV > > Marvell/Drivers/Spi: Improve modules dependencies > > > > Silicon/Marvell/Marvell.dec | 7 +- > > Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc | 18 ++- > > Silicon/Marvell/Armada7k8k/Armada7k8k.fdf | 3 - > > Silicon/Marvell/Drivers/Spi/MvFvbDxe/MvFvbDxe.inf | 14 +- > > Silicon/Marvell/Drivers/Spi/MvSpiFlashDxe/MvSpiFlashDxe.inf | 5 +- > > Silicon/Marvell/Drivers/Spi/MvSpiOrionDxe/MvSpiOrionDxe.inf | 5 +- > > Silicon/Marvell/Drivers/Spi/MvFvbDxe/MvFvbDxe.h | 1 + > > Silicon/Marvell/Drivers/Spi/MvFvbDxe/MvFvbDxe.c | 149 ++++= +++++++++++----- > > 8 files changed, 140 insertions(+), 62 deletions(-) > > > > -- > > 2.7.4 > >