From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: mx.groups.io; dkim=pass header.i=@semihalf-com.20150623.gappssmtp.com header.s=20150623 header.b=NU7J9hBe; spf=none, err=SPF record not found (domain: semihalf.com, ip: 209.85.160.178, mailfrom: mw@semihalf.com) Received: from mail-qt1-f178.google.com (mail-qt1-f178.google.com [209.85.160.178]) by groups.io with SMTP; Fri, 31 May 2019 16:09:42 -0700 Received: by mail-qt1-f178.google.com with SMTP id z24so2901233qtj.10 for ; Fri, 31 May 2019 16:09:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc:content-transfer-encoding; bh=cQbL6fko7jH4mcDd7BEKoYXBudbu3soGyrAcbnDN1U4=; b=NU7J9hBeF2liEezabYuVn/A5Mq+LVP9f5bPJgXzLM9HPSnqrIs5ioMjQf1cd2on+7p IgMbdCzj9NaquOv7jy1byr69b4IW8RYpCE4zxOJs5tTY6/DwyC+ptp6k6DgvSCDHw2jz Sdsac6zM2nistcA2UvIPoTBJ6IxArcTuPve5B4kZEdS09PrmuZU/rZCkt1TaIkX1lWgZ rWOm30TUYBSSvmqHCngCaMh8Q1Gs9Ps6H0qA6HvZUfp7wvMT8NqtuOme1S7jPG8/2OI1 zBcqCN3a96mI8hHB6azjLT4/lZkJDDceug14eV7Lrl70/7b0KOm0QsvpSWsaCqWr8DKI W76A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc:content-transfer-encoding; bh=cQbL6fko7jH4mcDd7BEKoYXBudbu3soGyrAcbnDN1U4=; b=n5+TN6Ms6GUuP8PqRnVWtxpCDG61iuAlhzS8I54XjfQWzYP4DsVfyzJ/1UgwH3vxgk 1AFaFznX43id7vVF3WIJAJaiaIXapFEtY/+HSi4HA7IJHB3YygP2Mvd3ca/qeaODEF0u r9t6yAJ5Ke2XdM6n4bC3vIG1DZePL+SkxN7Xm9JJySB37oktdbJ7LmU/i6oM9fGeSRWs P++b/lq7HA9rKu7wylgpSDoptdCiQrSzp9IQy703JFHE4OSc4VUN6ziJNZ5Us9puWAIw Y8B3XRuk4QYyxNtLSpY9XR1Ax9487C/0zjeO/fKE+iu8BHYqpHfF9wLUAzDGA2zMNLZV m7MA== X-Gm-Message-State: APjAAAU7ttPI8b3mgaotD2F6HHQ0HYsAnzRlLBpj4a0gpFn4QZsyve+W RjJqiVLrRVFFqPg+PT9iMFtL4KR41wVvvjQYLy3V/Ex5 X-Google-Smtp-Source: APXvYqx5i2OYo1SArDZAl7YaPVOkVCf35P+CotMwdtcXgWaWWPk3r2C5eTl92pTBJlX2CJL8CeDh/W2+1ByQ5kumVhI= X-Received: by 2002:ac8:1c7b:: with SMTP id j56mr2508236qtk.247.1559344180377; Fri, 31 May 2019 16:09:40 -0700 (PDT) MIME-Version: 1.0 References: <1559319619-12833-1-git-send-email-mw@semihalf.com> <582a403c-7c4f-00b4-abad-8a2fef010c37@arm.com> In-Reply-To: From: "Marcin Wojtas" Date: Sat, 1 Jun 2019 01:09:27 +0200 Message-ID: Subject: Re: [edk2-devel] [edk2-platforms: PATCH v2] Marvell/Armada7k8k: Introduce SMBIOS/DMI support To: edk2-devel-groups-io , Jeremy Linton Cc: Leif Lindholm , Ard Biesheuvel , "jsd@semihalf.com" , Grzegorz Jaszczyk , Kostya Porotchkin , Jici Gao Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Jeremy, pt., 31 maj 2019 o 22:08 Jeremy Linton napisa=C5= =82(a): > > > Hi, > > So I told myself not to debug this, but did anyway. Its because edk2 is > advertising a > smbios 3.1 table. SMBIOS 3.1 adds > > // > // Add for smbios 3.1.0 > // > UINT32 MaximumCacheSize2; > UINT32 InstalledSize2; > } SMBIOS_TABLE_TYPE7; > > which means that dmidecodes which are new enough notice this, go ahead > and use the larger cache size descriptions which were added in 3.1 > instead of the old description. So in this case you need to fill out > both the Installed/MaximumCacheSize fields as your doing as well as the > new MaximumCacheSize2/InstalledSize2 fields. > > Thanks a lot! As requested, I increased version PCD and with my dmidecode I didn't notice any issue. I will submit v3 with this extension - I will appreciate your testing and confirmation. Best regards, Marcin > > On 5/31/19 1:04 PM, Marcin Wojtas wrote: > > Hi Jeremy, > > > > Thanks for a quick test! > > > > 1. Cache sizes - here's the dmidecode output > > > > Handle 0x1000, DMI type 7, 27 bytes > > Cache Information > > Socket Designation: L1 Instruction > > [...] > > Installed Size: 48 kB > > [...] > > > > Handle 0x1001, DMI type 7, 27 bytes > > Cache Information > > Socket Designation: L1 Data > > [...] > > Installed Size: 32 kB > > Maximum Size: 32 kB > > [...] > > > > Handle 0x1002, DMI type 7, 27 bytes > > Cache Information > > Socket Designation: L2 > > [...] > > Installed Size: 512 kB > > Maximum Size: 512 kB > > [...] > > > > Handle 0x1003, DMI type 7, 27 bytes > > Cache Information > > Socket Designation: L3 > > [...] > > Installed Size: 1024 kB > > Maximum Size: 1024 kB > > [...] > > > > Above size values match the spec. Am I missing something? > > > > 2. DIMM/SPD data is read and processed in ARM-TF. Currently processing= this > > data is not available in EDK2. On the other hand Table19 and TYPE 17 s= hows > > the real memory map and size, which is read during EDK2 init (check > > GetDramSize () > > in Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLibMem.c= ) > > from via SMC from the secure world. > > > > DDR speed is also read from the SoC registers. > > > > Any particular data that you are missing? > > > > 3. In next step I'd like to use BoardDescProtocol to update a couple o= f > > tables fields such as name, revision number, PCIE slots information. > > > > Best regards, > > Marcin > > > > > > > > pt., 31 maj 2019 o 19:05 Jeremy Linton napisa= =C5=82(a): > > > >> Hi, > >> > >> I'm super in favor of this, but.. I noticed while trying to test it t= hat > >> the cache sizes being displayed by dmidecode don't seem to match what= is > >> in this table, implying something doesn't appear to be 100% correct. > >> > >> Also, while its understandable all the missing serial/chassis/etc > >> fields, the dimm data should be available? I assume the dimm training > >> add-on is reading the SPD from the dimm, so it can/should be stored > >> somewhere? > >> > >> Thanks, > >> > >> > >> On 5/31/19 11:20 AM, Marcin Wojtas via Groups.Io wrote: > >>> Fill in the basic requirements of the SMBIOS specification by specif= ying > >>> the minimum required structures. The basic fixup is performed. > >>> CPU/DRAM frequency is obtained via SampleAtResetlib and the DRAM siz= e > >>> is calculated from the information stored in the HOB list. > >>> > >>> Add new Armada SmbiosPlatformDxe and MdeModulePkg/SmbiosDxe to the > >>> build and firmware image. With these changes, the EFI BDS, EFI shell= , > >>> and Linux dmidecode command return useful information. > >>> > >>> Contributed-under: TianoCore Contribution Agreement 1.1 > >>> Signed-off-by: Marcin Wojtas > >>> --- > >>> Hi, > >>> > >>> This is the second version of the SmBios support for > >>> Armada platforms, addressing all remarks from the initial > >>> patch. Please check the changelog below. > >>> > >>> In order to ease review, the patch is available in the github: > >>> > >> https://github.com/MarvellEmbeddedProcessors/edk2-open-platform/commi= ts/smbios-upstream-r20190531 > >>> > >>> Looking forward to your comments. > >>> > >>> Best regards, > >>> Marcin > >>> > >>> Changelog: > >>> v1->v2: > >>> * Update SMBIOS version to 3.2 > >>> * Correct copyright name and remove unused Packages/LibraryClasses/P= cds > >>> * Remove unused headers > >>> * SMBIOS_REFRENCE_HANDLES > >>> - Drop CA53 references > >>> - SMBIOS_HANDLE_A72_L3/SMBIOS_HANDLE_L3 > >>> - Add SMBIOS_HANDLE_A72_L1D and according type7 table > >>> * Do not use 'fixup' word > >>> * Unify string placeholders to 32 signs > >>> * LogSmbiosData > >>> - Use same variable name as in DoxyGen blurb > >>> - Fix indentation in for loop > >>> - Set double null in the same way in all cases. > >>> - Cast Record with (VOID *) > >>> * Add missing parameters description of SmbiosInstallMemoryStructure= () > >> and SmbiosInstallStructures() > >>> * Split variable assignment with its declaration in SmbiosMemoryInst= all() > >>> * Keep firmware revision in local variables in > >> SmbiosInstallAllStructures() > >>> > >>> Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc |= 9 + > >>> Silicon/Marvell/Armada7k8k/Armada7k8k.fdf |= 4 + > >>> Silicon/Marvell/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.inf |= 50 > >> ++ > >>> Silicon/Marvell/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.c |= 813 > >> ++++++++++++++++++++ > >>> 4 files changed, 876 insertions(+) > >>> create mode 100644 > >> Silicon/Marvell/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.inf > >>> create mode 100644 > >> Silicon/Marvell/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.c > >>> > >>> diff --git a/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc > >> b/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc > >>> index 0e63bc8..ed716a7 100644 > >>> --- a/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc > >>> +++ b/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc > >>> @@ -398,6 +398,11 @@ > >>> gMarvellTokenSpaceGuid.PcdOpTeeRegionBase|0x4400000 > >>> gMarvellTokenSpaceGuid.PcdOpTeeRegionSize|0x1000000 > >>> > >>> + # SMBIOS/DMI > >>> + gEfiMdeModulePkgTokenSpaceGuid.PcdSmbiosDocRev|0x0 > >>> + gEfiMdeModulePkgTokenSpaceGuid.PcdSmbiosEntryPointProvideMethod|0= x2 > >>> + gEfiMdeModulePkgTokenSpaceGuid.PcdSmbiosVersion|0x0320 > >>> + > >>> # TRNG > >>> gMarvellTokenSpaceGuid.PcdEip76TrngBaseAddress|0xF2760000 > >>> > >>> @@ -615,6 +620,10 @@ > >>> ShellPkg/DynamicCommand/TftpDynamicCommand/TftpDynamicCommand.i= nf > >>> !endif #$(INCLUDE_TFTP_COMMAND) > >>> > >>> + # SMBIOS/DMI > >>> + MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf > >>> + Silicon/Marvell/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.inf > >>> + > >>> [Components.AARCH64] > >>> # > >>> # Generic ACPI modules > >>> diff --git a/Silicon/Marvell/Armada7k8k/Armada7k8k.fdf > >> b/Silicon/Marvell/Armada7k8k/Armada7k8k.fdf > >>> index f59cc1f..e003623 100644 > >>> --- a/Silicon/Marvell/Armada7k8k/Armada7k8k.fdf > >>> +++ b/Silicon/Marvell/Armada7k8k/Armada7k8k.fdf > >>> @@ -207,6 +207,10 @@ FvNameGuid =3D > >> 5eda4200-2c5f-43cb-9da3-0baf74b1b30c > >>> # DTB > >>> INF EmbeddedPkg/Drivers/DtPlatformDxe/DtPlatformDxe.inf > >>> > >>> + # SMBIOS/DMI > >>> + INF MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf > >>> + INF Silicon/Marvell/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.i= nf > >>> + > >>> !if $(ARCH) =3D=3D AARCH64 > >>> # ACPI support > >>> INF MdeModulePkg/Universal/Acpi/AcpiPlatformDxe/AcpiPlatformDxe= .inf > >>> diff --git > >> a/Silicon/Marvell/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.inf > >> b/Silicon/Marvell/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.inf > >>> new file mode 100644 > >>> index 0000000..8fa0438 > >>> --- /dev/null > >>> +++ b/Silicon/Marvell/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.in= f > >>> @@ -0,0 +1,50 @@ > >>> +#/** @file > >>> +# SMBIOS Table for ARM platform > >>> +# > >>> +# Copyright (c) 2013, Linaro Ltd. All rights reserved.
> >>> +# Copyright (c) 2019, Marvell International Ltd. and its affiliate= s > >>> +# > >>> +# This program and the accompanying materials > >>> +# are licensed and made available under the terms and conditions o= f > >> the BSD License > >>> +# which accompanies this distribution. The full text of the licen= se > >> may be found at > >>> +# http://opensource.org/licenses/bsd-license.php > >>> +# > >>> +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" B= ASIS, > >>> +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRES= S OR > >> IMPLIED. > >>> +# > >>> +#**/ > >>> + > >>> +[Defines] > >>> + INF_VERSION =3D 0x0001001B > >>> + BASE_NAME =3D SmbiosPlatformDxe > >>> + FILE_GUID =3D 1c5028a4-3bd0-43cf-9e56-b45058= 4dc22b > >>> + MODULE_TYPE =3D DXE_DRIVER > >>> + VERSION_STRING =3D 1.0 > >>> + ENTRY_POINT =3D SmbiosPlatformDriverEntryPoint > >>> + > >>> +[Sources] > >>> + SmbiosPlatformDxe.c > >>> + > >>> +[Packages] > >>> + MdeModulePkg/MdeModulePkg.dec > >>> + MdePkg/MdePkg.dec > >>> + Silicon/Marvell/Marvell.dec > >>> + > >>> +[LibraryClasses] > >>> + BaseLib > >>> + BaseMemoryLib > >>> + DebugLib > >>> + HobLib > >>> + PcdLib > >>> + SampleAtResetLib > >>> + UefiBootServicesTableLib > >>> + UefiDriverEntryPoint > >>> + > >>> +[FixedPcd] > >>> + gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareRevision > >>> + > >>> +[Protocols] > >>> + gEfiSmbiosProtocolGuid # PROTOCOL ALWAYS_CON= SUMED > >>> + > >>> +[Depex] > >>> + gEfiSmbiosProtocolGuid > >>> diff --git > >> a/Silicon/Marvell/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.c > >> b/Silicon/Marvell/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.c > >>> new file mode 100644 > >>> index 0000000..12ee72e > >>> --- /dev/null > >>> +++ b/Silicon/Marvell/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.c > >>> @@ -0,0 +1,813 @@ > >>> +/** @file > >>> + This driver installs SMBIOS information for Marvell Armada platfo= rms > >>> + > >>> + Copyright (c) 2015, ARM Limited. All rights reserved. > >>> + Copyright (c) 2019, Marvell International Ltd. and its affiliates > >>> + > >>> + This program and the accompanying materials > >>> + are licensed and made available under the terms and conditions of= the > >> BSD License > >>> + which accompanies this distribution. The full text of the licens= e > >> may be found at > >>> + http://opensource.org/licenses/bsd-license.php > >>> + > >>> + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BA= SIS, > >>> + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS= OR > >> IMPLIED. > >>> + > >>> +**/ > >>> +#include > >>> +#include > >>> +#include > >>> +#include > >>> +#include > >>> +#include > >>> +#include > >>> +#include > >>> + > >>> +#include > >>> + > >>> +#include > >>> + > >>> +// > >>> +// SMBIOS tables often reference each other using > >>> +// fixed constants, define a list of these constants > >>> +// for our hardcoded tables > >>> +// > >>> +enum SMBIOS_REFRENCE_HANDLES { > >>> + SMBIOS_HANDLE_A72_L1I =3D 0x1000, > >>> + SMBIOS_HANDLE_A72_L1D, > >>> + SMBIOS_HANDLE_A72_L2, > >>> + SMBIOS_HANDLE_L3, > >>> + SMBIOS_HANDLE_MOTHERBOARD, > >>> + SMBIOS_HANDLE_CHASSIS, > >>> + SMBIOS_HANDLE_A72_CLUSTER, > >>> + SMBIOS_HANDLE_MEMORY, > >>> + SMBIOS_HANDLE_DIMM > >>> +}; > >>> + > >>> +// > >>> +// Type definition and contents of the default SMBIOS table. > >>> +// This table covers only the minimum structures required by > >>> +// the SMBIOS specification (section 6.2, version 3.0) > >>> +// > >>> + > >>> +// BIOS information (section 7.1) > >>> +STATIC SMBIOS_TABLE_TYPE0 mArmadaDefaultType0 =3D { > >>> + { // SMBIOS_STRUCTURE Hdr > >>> + EFI_SMBIOS_TYPE_BIOS_INFORMATION, // UINT8 Type > >>> + sizeof (SMBIOS_TABLE_TYPE0), // UINT8 Length > >>> + SMBIOS_HANDLE_PI_RESERVED, > >>> + }, > >>> + 1, // SMBIOS_TABLE_STRING Vendor > >>> + 2, // SMBIOS_TABLE_STRING BiosVersion > >>> + 0xE800,// UINT16 BiosSegment > >>> + 3, // SMBIOS_TABLE_STRING BiosReleaseDate > >>> + 0, // UINT8 BiosSize > >>> + { > >>> + 0,0,0,0,0,0, > >>> + 1, //PCI supported > >>> + 0, > >>> + 1, //PNP supported > >>> + 0, > >>> + 1, //BIOS upgradable > >>> + 0, 0, 0, > >>> + 0, //Boot from CD > >>> + 1, //selectable boot > >>> + }, // MISC_BIOS_CHARACTERISTICS BiosCharacteristics > >>> + { // BIOSCharacteristicsExtensionBytes[2] > >>> + 0x3, > >>> + 0xC, > >>> + }, > >>> + 0, // UINT8 SystemBiosMajorRelease > >>> + 0, // UINT8 SystemBiosMinorRelease > >>> + 0xFF, // UINT8 > >> EmbeddedControllerFirmwareMajorRelease > >>> + 0xFF, // UINT8 > >> EmbeddedControllerFirmwareMinorRelease > >>> +}; > >>> + > >>> +STATIC CHAR8 CONST *mArmadaDefaultType0Strings[] =3D { > >>> + "EFI Development Kit II / Marvell\0", /* Vendor */ > >>> + "EDK II\0", /* BiosVersion */ > >>> + __DATE__"\0", /* BiosReleaseDate */ > >>> + NULL > >>> +}; > >>> + > >>> +// System information (section 7.2) > >>> +STATIC SMBIOS_TABLE_TYPE1 mArmadaDefaultType1 =3D { > >>> + { // SMBIOS_STRUCTURE Hdr > >>> + EFI_SMBIOS_TYPE_SYSTEM_INFORMATION, > >>> + sizeof (SMBIOS_TABLE_TYPE1), > >>> + SMBIOS_HANDLE_PI_RESERVED, > >>> + }, > >>> + 1, //Manufacturer > >>> + 2, //Product Name > >>> + 3, //Version > >>> + 4, //Serial > >>> + { 0x97c93925, 0x1273, 0x4f03, { > >> 0x9f,0x75,0x2f,0x2b,0x7e,0xd1,0x94,0x80 }}, //UUID > >>> + 6, //Wakeup type > >>> + 0, //SKU > >>> + 0, //Family > >>> +}; > >>> + > >>> +STATIC CHAR8 CONST *mArmadaDefaultType1Strings[] =3D { > >>> + "Marvell \0",/* Manufacturer */ > >>> + "Armada 7k/8k Family Board \0",/* Product Name placeholder*/ > >>> + "Revision unknown \0",/* Version placeholder */ > >>> + " \0",/* 32 character buffer */ > >>> + NULL > >>> +}; > >>> + > >>> +// Baseboard (section 7.3) > >>> +STATIC SMBIOS_TABLE_TYPE2 mArmadaDefaultType2 =3D { > >>> + { // SMBIOS_STRUCTURE Hdr > >>> + EFI_SMBIOS_TYPE_BASEBOARD_INFORMATION, // UINT8 Type > >>> + sizeof (SMBIOS_TABLE_TYPE2), // UINT8 Length > >>> + SMBIOS_HANDLE_MOTHERBOARD, > >>> + }, > >>> + 1, //Manufacturer > >>> + 2, //Product Name > >>> + 3, //Version > >>> + 4, //Serial > >>> + 0, //Asset tag > >>> + {1}, //motherboard, not replaceable > >>> + 5, //location of board > >>> + SMBIOS_HANDLE_CHASSIS, > >>> + BaseBoardTypeMotherBoard, > >>> + 1, > >>> + {SMBIOS_HANDLE_A72_CLUSTER}, > >>> +}; > >>> + > >>> +STATIC CHAR8 CONST *mArmadaDefaultType2Strings[] =3D { > >>> + "Marvell \0",/* Manufacturer */ > >>> + "Armada 7k/8k Family Board \0",/* Product Name placeholder*/ > >>> + "Revision unknown \0",/* Version placeholder */ > >>> + "Serial Not Set \0",/* Serial */ > >>> + "Base of Chassis \0",/* Board location */ > >>> + NULL > >>> +}; > >>> + > >>> +// Enclosure > >>> +STATIC SMBIOS_TABLE_TYPE3 mArmadaDefaultType3 =3D { > >>> + { // SMBIOS_STRUCTURE Hdr > >>> + EFI_SMBIOS_TYPE_SYSTEM_ENCLOSURE, // UINT8 Type > >>> + sizeof (SMBIOS_TABLE_TYPE3), // UINT8 Length > >>> + SMBIOS_HANDLE_CHASSIS, > >>> + }, > >>> + 1, //Manufacturer > >>> + 2, //enclosure type > >>> + 2, //version > >>> + 3, //serial > >>> + 0, //asset tag > >>> + ChassisStateUnknown, //boot chassis state > >>> + ChassisStateSafe, //power supply state > >>> + ChassisStateSafe, //thermal state > >>> + ChassisSecurityStatusNone, //security state > >>> + {0,0,0,0,}, //OEM defined > >>> + 1, //1U height > >>> + 1, //number of power cords > >>> + 0, //no contained elements > >>> +}; > >>> + > >>> +STATIC CHAR8 CONST *mArmadaDefaultType3Strings[] =3D { > >>> + "Marvell \0",/* Manufacturer placeholder *= / > >>> + "Revision unknown \0",/* Version placeholder */ > >>> + "Serial Not Set \0",/* Serial placeholder */ > >>> + NULL > >>> +}; > >>> + > >>> +// Processor > >>> +STATIC SMBIOS_TABLE_TYPE4 mArmadaDefaultType4 =3D { > >>> + { // SMBIOS_STRUCTURE Hdr > >>> + EFI_SMBIOS_TYPE_PROCESSOR_INFORMATION, // UINT8 Type > >>> + sizeof (SMBIOS_TABLE_TYPE4), // UINT8 Length > >>> + SMBIOS_HANDLE_A72_CLUSTER, > >>> + }, > >>> + 1, //socket type > >>> + 3, //processor type CPU > >>> + ProcessorFamilyIndicatorFamily2, //processor family, acquire from > >> field2 > >>> + 2, //manufactuer > >>> + {{0,},{0.}}, //processor id > >>> + 3, //version > >>> + {0,0,0,0,0,1}, //voltage > >>> + 0, //external clock > >>> + 2000, //max speed > >>> + 0, //current speed - requires update > >>> + 0x41, //status > >>> + ProcessorUpgradeOther, > >>> + SMBIOS_HANDLE_A72_L1I, //l1 cache handle > >>> + SMBIOS_HANDLE_A72_L2, //l2 cache handle > >>> + SMBIOS_HANDLE_L3, //l3 cache handle > >>> + 0, //serial not set > >>> + 0, //asset not set > >>> + 4, //part number > >>> + 4, //core count in socket > >>> + 4, //enabled core count in socket > >>> + 0, //threads per socket > >>> + 0xEC, //processor characteristics > >>> + ProcessorFamilyARM, //ARMADA core > >>> +}; > >>> + > >>> +STATIC CHAR8 CONST *mArmadaDefaultType4Strings[] =3D { > >>> + "Socket type unknown \0", /* Socket type placeholder */ > >>> + "Marvell\0", /* manufactuer */ > >>> + "Cortex-A72\0", /* processor description */ > >>> + "0xd08\0", /* A72 part number */ > >>> + NULL > >>> +}; > >>> + > >>> +// Cache > >>> +STATIC SMBIOS_TABLE_TYPE7 mArmadaDefaultType7_a72_l1i =3D { > >>> + { // SMBIOS_STRUCTURE Hdr > >>> + EFI_SMBIOS_TYPE_CACHE_INFORMATION, // UINT8 Type > >>> + sizeof (SMBIOS_TABLE_TYPE7), // UINT8 Length > >>> + SMBIOS_HANDLE_A72_L1I, > >>> + }, > >>> + 1, > >>> + 0x380, //L1 enabled, unknown WB > >>> + 48, //48k I-cache max > >>> + 48, //48k installed > >>> + {0,1}, //SRAM type > >>> + {0,1}, //SRAM type > >>> + 0, //speed unknown > >>> + CacheErrorParity, //parity checking > >>> + CacheTypeInstruction, //instruction cache > >>> + CacheAssociativityOther, //three way > >>> +}; > >>> + > >>> +STATIC SMBIOS_TABLE_TYPE7 mArmadaDefaultType7_a72_l1d =3D { > >>> + { // SMBIOS_STRUCTURE Hdr > >>> + EFI_SMBIOS_TYPE_CACHE_INFORMATION, // UINT8 Type > >>> + sizeof (SMBIOS_TABLE_TYPE7), // UINT8 Length > >>> + SMBIOS_HANDLE_A72_L1D, > >>> + }, > >>> + 2, > >>> + 0x380, //L1 enabled, unknown WB > >>> + 32, //32k D-cache max > >>> + 32, //32k installed > >>> + {0,1}, //SRAM type > >>> + {0,1}, //SRAM type > >>> + 0, //speed unknown > >>> + CacheErrorParity, //parity checking > >>> + CacheTypeInstruction, //instruction cache > >>> + CacheAssociativityOther, //three way > >>> +}; > >>> + > >>> +STATIC SMBIOS_TABLE_TYPE7 mArmadaDefaultType7_a72_l2 =3D { > >>> + { // SMBIOS_STRUCTURE Hdr > >>> + EFI_SMBIOS_TYPE_CACHE_INFORMATION, // UINT8 Type > >>> + sizeof (SMBIOS_TABLE_TYPE7), // UINT8 Length > >>> + SMBIOS_HANDLE_A72_L2, > >>> + }, > >>> + 3, > >>> + 0x181, //L2 enabled, WB > >>> + 512, //512k D-cache max > >>> + 512, //512k installed > >>> + {0,1}, //SRAM type > >>> + {0,1}, //SRAM type > >>> + 0, //speed unknown > >>> + CacheErrorSingleBit, //ECC checking > >>> + CacheTypeUnified, //instruction cache > >>> + CacheAssociativity16Way, //16 way associative > >>> +}; > >>> + > >>> +STATIC SMBIOS_TABLE_TYPE7 mArmadaDefaultType7_l3 =3D { > >>> + { // SMBIOS_STRUCTURE Hdr > >>> + EFI_SMBIOS_TYPE_CACHE_INFORMATION, // UINT8 Type > >>> + sizeof (SMBIOS_TABLE_TYPE7), // UINT8 Length > >>> + SMBIOS_HANDLE_L3, > >>> + }, > >>> + 4, > >>> + 0x182, //L3 enabled, WB > >>> + 1024, //1M cache max > >>> + 1024, //1M installed > >>> + {0,1}, //SRAM type > >>> + {0,1}, //SRAM type > >>> + 0, //speed unknown > >>> + CacheErrorSingleBit, //ECC checking > >>> + CacheTypeUnified, //instruction cache > >>> + CacheAssociativity8Way, //8 way associative > >>> +}; > >>> + > >>> +STATIC CONST CHAR8 *mArmadaDefaultType7Strings[] =3D { > >>> + "L1 Instruction\0", /* L1I */ > >>> + "L1 Data\0", /* L1D */ > >>> + "L2\0", /* L2 */ > >>> + "L3\0", /* L3 */ > >>> + NULL > >>> +}; > >>> + > >>> +// Slots > >>> +STATIC SMBIOS_TABLE_TYPE9 mArmadaDefaultType9_0 =3D { > >>> + { // SMBIOS_STRUCTURE Hdr > >>> + EFI_SMBIOS_TYPE_INACTIVE, // UINT8 Type > >>> + sizeof (SMBIOS_TABLE_TYPE9), // UINT8 Length > >>> + SMBIOS_HANDLE_PI_RESERVED, > >>> + }, > >>> + 1, // CP0 PCIE0 > >>> + SlotTypePciExpressGen2X1, > >>> + SlotDataBusWidth1X, > >>> + SlotUsageUnknown, > >>> + SlotLengthShort, > >>> + 0, > >>> + {1}, //Unknown > >>> + {1,0,1}, //PME and SMBUS > >>> + 0, > >>> + 0, > >>> + 1, > >>> +}; > >>> + > >>> +STATIC SMBIOS_TABLE_TYPE9 mArmadaDefaultType9_1 =3D { > >>> + { // SMBIOS_STRUCTURE Hdr > >>> + EFI_SMBIOS_TYPE_INACTIVE, // UINT8 Type > >>> + sizeof (SMBIOS_TABLE_TYPE9), // UINT8 Length > >>> + SMBIOS_HANDLE_PI_RESERVED, > >>> + }, > >>> + 2, // CP0 PCIE1 > >>> + SlotTypePciExpressGen2X1, > >>> + SlotDataBusWidth1X, > >>> + SlotUsageUnknown, > >>> + SlotLengthShort, > >>> + 0, > >>> + {1}, > >>> + {1,0,1}, //PME and SMBUS > >>> + 0, > >>> + 0, > >>> + 2, > >>> +}; > >>> + > >>> +STATIC SMBIOS_TABLE_TYPE9 mArmadaDefaultType9_2 =3D { > >>> + { // SMBIOS_STRUCTURE Hdr > >>> + EFI_SMBIOS_TYPE_INACTIVE, // UINT8 Type > >>> + sizeof (SMBIOS_TABLE_TYPE9), // UINT8 Length > >>> + SMBIOS_HANDLE_PI_RESERVED, > >>> + }, > >>> + 3, // CP0 PCIE2 > >>> + SlotTypePciExpressGen2X1, > >>> + SlotDataBusWidth1X, > >>> + SlotUsageUnknown, > >>> + SlotLengthShort, > >>> + 0, > >>> + {1}, > >>> + {1,0,1}, //PME and SMBUS > >>> + 0, > >>> + 0, > >>> + 3, > >>> +}; > >>> + > >>> +STATIC SMBIOS_TABLE_TYPE9 mArmadaDefaultType9_3 =3D { > >>> + { // SMBIOS_STRUCTURE Hdr > >>> + EFI_SMBIOS_TYPE_INACTIVE, // UINT8 Type > >>> + sizeof (SMBIOS_TABLE_TYPE9), // UINT8 Length > >>> + SMBIOS_HANDLE_PI_RESERVED, > >>> + }, > >>> + 4, // CP1 PCIE0 > >>> + SlotTypePciExpressGen2X1, > >>> + SlotDataBusWidth1X, > >>> + SlotUsageUnknown, > >>> + SlotLengthShort, > >>> + 0, > >>> + {1}, > >>> + {1,0,1}, //PME and SMBUS > >>> + 0, > >>> + 0, > >>> + 0xc, > >>> +}; > >>> + > >>> +STATIC SMBIOS_TABLE_TYPE9 mArmadaDefaultType9_4 =3D { > >>> + { // SMBIOS_STRUCTURE Hdr > >>> + EFI_SMBIOS_TYPE_INACTIVE, // UINT8 Type > >>> + sizeof (SMBIOS_TABLE_TYPE9), // UINT8 Length > >>> + SMBIOS_HANDLE_PI_RESERVED, > >>> + }, > >>> + 5, // CP1 PCIE1 > >>> + SlotTypePciExpressGen2X1, > >>> + SlotDataBusWidth1X, > >>> + SlotUsageUnknown, > >>> + SlotLengthShort, > >>> + 0, > >>> + {1}, > >>> + {1,0,1}, //PME and SMBUS > >>> + 0, > >>> + 0, > >>> + 0xc, > >>> +}; > >>> + > >>> +STATIC SMBIOS_TABLE_TYPE9 mArmadaDefaultType9_5 =3D { > >>> + { // SMBIOS_STRUCTURE Hdr > >>> + EFI_SMBIOS_TYPE_INACTIVE, // UINT8 Type > >>> + sizeof (SMBIOS_TABLE_TYPE9), // UINT8 Length > >>> + SMBIOS_HANDLE_PI_RESERVED, > >>> + }, > >>> + 6, // CP1 PCIE2 > >>> + SlotTypePciExpressGen2X1, > >>> + SlotDataBusWidth1X, > >>> + SlotUsageUnknown, > >>> + SlotLengthShort, > >>> + 0, > >>> + {1}, > >>> + {1,0,1}, //PME and SMBUS > >>> + 0, > >>> + 0, > >>> + 0xc, > >>> +}; > >>> + > >>> +STATIC CHAR8 CONST *mArmadaDefaultType9Strings[] =3D { > >>> + "PCIE0 CP0 \0",/* Slot0 */ > >>> + "PCIE1 CP0 \0",/* Slot1 */ > >>> + "PCIE2 CP0 \0",/* Slot2 */ > >>> + "PCIE0 CP1 \0",/* Slot3 */ > >>> + "PCIE1 CP1 \0",/* Slot4 */ > >>> + "PCIE2 CP1 \0",/* Slot5 */ > >>> + NULL > >>> +}; > >>> + > >>> +// Memory array > >>> +STATIC SMBIOS_TABLE_TYPE16 mArmadaDefaultType16 =3D { > >>> + { // SMBIOS_STRUCTURE Hdr > >>> + EFI_SMBIOS_TYPE_PHYSICAL_MEMORY_ARRAY, // UINT8 Type > >>> + sizeof (SMBIOS_TABLE_TYPE16), // UINT8 Length > >>> + SMBIOS_HANDLE_MEMORY, > >>> + }, > >>> + MemoryArrayLocationSystemBoard, //on motherboard > >>> + MemoryArrayUseSystemMemory, //system RAM > >>> + MemoryErrorCorrectionNone, //ECC RAM > >>> + 0x1000000, //16GB > >>> + 0xFFFE, //No error information structure > >>> + 0x1, //soldered memory > >>> +}; > >>> + > >>> +STATIC CHAR8 CONST *mArmadaDefaultType16Strings[] =3D { > >>> + NULL > >>> +}; > >>> + > >>> +// Memory device > >>> +STATIC SMBIOS_TABLE_TYPE17 mArmadaDefaultType17 =3D { > >>> + { // SMBIOS_STRUCTURE Hdr > >>> + EFI_SMBIOS_TYPE_MEMORY_DEVICE, // UINT8 Type > >>> + sizeof (SMBIOS_TABLE_TYPE17), // UINT8 Length > >>> + SMBIOS_HANDLE_DIMM, > >>> + }, > >>> + SMBIOS_HANDLE_MEMORY, //array to which this module belongs > >>> + 0xFFFE, //no errors > >>> + 64, //single DIMM, no ECC is 64bits (for ecc this would be 72) > >>> + 32, //data width of this device (32-bits) > >>> + 0, //Memory size obtained dynamically > >>> + MemoryFormFactorRowOfChips, //Memory factor > >>> + 0, //Not part of a set > >>> + 1, //Right side of board > >>> + 2, //Bank 0 > >>> + MemoryTypeDdr4, //DDR4 > >>> + {0,0,0,0,0,0,0,0,0,0,0,0,0,0,1}, //unbuffered > >>> + 0, //DRAM speed - requires update > >>> + 0, //varies between diffrent production runs > >>> + 0, //serial > >>> + 0, //asset tag > >>> + 0, //part number > >>> + 0, //rank > >>> +}; > >>> + > >>> +STATIC CHAR8 CONST *mArmadaDefaultType17Strings[] =3D { > >>> + "RIGHT SIDE\0", /* location */ > >>> + "BANK 0\0", /* bank description */ > >>> + NULL > >>> +}; > >>> + > >>> +// > >>> +// Memory array mapped address, this structure > >>> +// is overridden by SmbiosInstallMemoryStructure. > >>> +// > >>> +STATIC SMBIOS_TABLE_TYPE19 mArmadaDefaultType19 =3D { > >>> + { // SMBIOS_STRUCTURE Hdr > >>> + EFI_SMBIOS_TYPE_MEMORY_ARRAY_MAPPED_ADDRESS, // UINT8 Type > >>> + sizeof (SMBIOS_TABLE_TYPE19), // UINT8 Length > >>> + SMBIOS_HANDLE_PI_RESERVED, > >>> + }, > >>> + 0xFFFFFFFF, //invalid, look at extended addr field > >>> + 0xFFFFFFFF, > >>> + SMBIOS_HANDLE_DIMM, //handle > >>> + 1, > >>> + 0x080000000, //starting addr of first 2GB > >>> + 0x100000000, //ending addr of first 2GB > >>> +}; > >>> + > >>> +// System boot infomArmadaDefaultType4. > >>> +STATIC SMBIOS_TABLE_TYPE32 mArmadaDefaultType32 =3D { > >>> + { // SMBIOS_STRUCTURE Hdr > >>> + EFI_SMBIOS_TYPE_SYSTEM_BOOT_INFORMATION, // UINT8 Type > >>> + sizeof (SMBIOS_TABLE_TYPE32), // UINT8 Length > >>> + SMBIOS_HANDLE_PI_RESERVED, > >>> + }, > >>> + {0, 0, 0, 0, 0, 0}, //reserved > >>> + BootInformationStatusNoError, > >>> +}; > >>> + > >>> +STATIC CHAR8 CONST *mArmadaDefaultType32Strings[] =3D { > >>> + NULL > >>> +}; > >>> + > >>> +STATIC CONST VOID *DefaultCommonTables[][2] =3D > >>> +{ > >>> + { &mArmadaDefaultType0, mArmadaDefaultType0Strings }, > >>> + { &mArmadaDefaultType1, mArmadaDefaultType1Strings }, > >>> + { &mArmadaDefaultType2, mArmadaDefaultType2Strings }, > >>> + { &mArmadaDefaultType3, mArmadaDefaultType3Strings }, > >>> + { &mArmadaDefaultType4, mArmadaDefaultType4Strings }, > >>> + { &mArmadaDefaultType7_a72_l1i, mArmadaDefaultType7Strings }, > >>> + { &mArmadaDefaultType7_a72_l1d, mArmadaDefaultType7Strings }, > >>> + { &mArmadaDefaultType7_a72_l2, mArmadaDefaultType7Strings }, > >>> + { &mArmadaDefaultType7_l3, mArmadaDefaultType7Strings }, > >>> + { &mArmadaDefaultType9_0, mArmadaDefaultType9Strings }, > >>> + { &mArmadaDefaultType9_1, mArmadaDefaultType9Strings }, > >>> + { &mArmadaDefaultType9_2, mArmadaDefaultType9Strings }, > >>> + { &mArmadaDefaultType9_3, mArmadaDefaultType9Strings }, > >>> + { &mArmadaDefaultType9_4, mArmadaDefaultType9Strings }, > >>> + { &mArmadaDefaultType9_5, mArmadaDefaultType9Strings }, > >>> + { &mArmadaDefaultType16, mArmadaDefaultType16Strings }, > >>> + { &mArmadaDefaultType17, mArmadaDefaultType17Strings }, > >>> + { &mArmadaDefaultType32, mArmadaDefaultType32Strings }, > >>> + { NULL, NULL }, > >>> +}; > >>> + > >>> +/** > >>> + > >>> + Create SMBIOS record. > >>> + > >>> + Converts a fixed SMBIOS structure and an array of pointers to str= ings > >> into > >>> + an SMBIOS record where the strings are cat'ed on the end of the f= ixed > >> record > >>> + and terminated via a double NULL and add to SMBIOS table. > >>> + > >>> + SMBIOS_TABLE_TYPE32 gSmbiosType12 =3D { > >>> + { EFI_SMBIOS_TYPE_SYSTEM_CONFIGURATION_OPTIONS, sizeof > >> (SMBIOS_TABLE_TYPE12), 0 }, > >>> + 1 // StringCount > >>> + }; > >>> + > >>> + CHAR8 *gSmbiosType12Strings[] =3D { > >>> + "Not Found", > >>> + NULL > >>> + }; > >>> + > >>> + ... > >>> + > >>> + LogSmbiosData ( > >>> + (EFI_SMBIOS_TABLE_HEADER*)&gSmbiosType12, > >>> + gSmbiosType12Strings > >>> + ); > >>> + > >>> + @param Smbios SMBIOS protocol > >>> + @param Template Fixed SMBIOS structure, required. > >>> + @param StringArray Array of strings to convert to an SMBIOS stri= ng > >> pack. > >>> + NULL is OK. > >>> +**/ > >>> +STATIC > >>> +EFI_STATUS > >>> +EFIAPI > >>> +LogSmbiosData ( > >>> + IN EFI_SMBIOS_PROTOCOL *Smbios, > >>> + IN EFI_SMBIOS_TABLE_HEADER *Template, > >>> + IN CONST CHAR8 * CONST *StringArray > >>> + ) > >>> +{ > >>> + EFI_STATUS Status; > >>> + EFI_SMBIOS_TABLE_HEADER *Record; > >>> + UINTN Index; > >>> + UINTN StringSize; > >>> + UINTN Size; > >>> + CHAR8 *Str; > >>> + > >>> + > >>> + // Calculate the size of the fixed record and optional string pac= k > >>> + Size =3D Template->Length; > >>> + if (StringArray =3D=3D NULL) { > >>> + // At least a double null is required > >>> + Size +=3D 1; > >>> + } else { > >>> + for (Index =3D 0; StringArray[Index] !=3D NULL; Index++) { > >>> + StringSize =3D AsciiStrSize (StringArray[Index]); > >>> + Size +=3D StringSize; > >>> + } > >>> + if (StringArray[0] =3D=3D NULL) { > >>> + // At least a double null is required > >>> + Size +=3D 1; > >>> + } > >>> + > >>> + // Don't forget the terminating double null > >>> + Size +=3D 1; > >>> + } > >>> + > >>> + // Copy over Template > >>> + Record =3D (EFI_SMBIOS_TABLE_HEADER *)AllocateZeroPool (Size); > >>> + if (Record =3D=3D NULL) { > >>> + return EFI_OUT_OF_RESOURCES; > >>> + } > >>> + CopyMem (Record, Template, Template->Length); > >>> + > >>> + // Append string pack > >>> + Str =3D ((VOID *)Record) + Record->Length; > >>> + for (Index =3D 0; StringArray[Index] !=3D NULL; Index++) { > >>> + StringSize =3D AsciiStrSize (StringArray[Index]); > >>> + CopyMem (Str, StringArray[Index], StringSize); > >>> + Str +=3D StringSize; > >>> + } > >>> + *Str =3D 0; > >>> + > >>> + Status =3D Smbios->Add (Smbios, > >>> + NULL, > >>> + &Record->Handle, > >>> + Record); > >>> + ASSERT_EFI_ERROR (Status); > >>> + > >>> + FreePool (Record); > >>> + > >>> + return Status; > >>> +} > >>> + > >>> +/** > >>> + Installs a memory descriptor (type19) for the given address rang= e > >>> + > >>> + @param Smbios SMBIOS protocol. > >>> + @param StartingAddress Start address of the memory chunk. > >>> + @param RegionLength Memory chunk size. > >>> + > >>> +**/ > >>> +EFI_STATUS > >>> +SmbiosInstallMemoryStructure ( > >>> + IN EFI_SMBIOS_PROTOCOL *Smbios, > >>> + IN UINT64 StartingAddress, > >>> + IN UINT64 RegionLength > >>> + ) > >>> +{ > >>> + EFI_SMBIOS_HANDLE SmbiosHandle; > >>> + SMBIOS_TABLE_TYPE19 MemoryDescriptor; > >>> + EFI_STATUS Status =3D EFI_SUCCESS; > >>> + > >>> + CopyMem (&MemoryDescriptor, > >>> + &mArmadaDefaultType19, > >>> + sizeof (SMBIOS_TABLE_TYPE19)); > >>> + > >>> + MemoryDescriptor.ExtendedStartingAddress =3D StartingAddress; > >>> + MemoryDescriptor.ExtendedEndingAddress =3D StartingAddress + > >> RegionLength; > >>> + SmbiosHandle =3D MemoryDescriptor.Hdr.Handle; > >>> + > >>> + Status =3D Smbios->Add (Smbios, > >>> + NULL, > >>> + &SmbiosHandle, > >>> + (EFI_SMBIOS_TABLE_HEADER*) &MemoryDescriptor); > >>> + > >>> + return Status; > >>> +} > >>> + > >>> +/** > >>> + Install a whole table worth of structructures > >>> + > >>> + @param Smbios SMBIOS protocol. > >>> + @param DefaultTables A pointer to the default SMBIOS tab= le > >> structure. > >>> + > >>> +**/ > >>> +EFI_STATUS > >>> +SmbiosInstallStructures ( > >>> + IN EFI_SMBIOS_PROTOCOL *Smbios, > >>> + IN CONST VOID *DefaultTables[][2] > >>> + ) > >>> +{ > >>> + EFI_STATUS Status =3D EFI_SUCCESS; > >>> + INTN TableEntry; > >>> + > >>> + for (TableEntry =3D 0; DefaultTables[TableEntry][0] !=3D NULL; > >> TableEntry++) { > >>> + // Omit disabled tables > >>> + if (((EFI_SMBIOS_TABLE_HEADER > >> *)DefaultTables[TableEntry][0])->Type =3D=3D > >>> + EFI_SMBIOS_TYPE_INACTIVE) { > >>> + continue; > >>> + } > >>> + > >>> + Status =3D LogSmbiosData (Smbios, > >>> + ((EFI_SMBIOS_TABLE_HEADER > >> *)DefaultTables[TableEntry][0]), > >>> + DefaultTables[TableEntry][1]); > >>> + if (EFI_ERROR (Status)) > >>> + break; > >>> + } > >>> + > >>> + return Status; > >>> +} > >>> + > >>> +/** > >>> + Update memory information basing on the HOB list. > >>> + > >>> + @param Smbios SMBIOS protocol > >>> + > >>> +**/ > >>> +STATIC > >>> +EFI_STATUS > >>> +SmbiosMemoryInstall ( > >>> + IN EFI_SMBIOS_PROTOCOL *Smbios > >>> + ) > >>> +{ > >>> + EFI_PEI_HOB_POINTERS Hob; > >>> + UINT64 MemorySize; > >>> + EFI_STATUS Status; > >>> + > >>> + MemorySize =3D 0; > >>> + > >>> + // > >>> + // Get the HOB list for processing > >>> + // > >>> + Hob.Raw =3D GetHobList (); > >>> + > >>> + // > >>> + // Collect memory ranges > >>> + // > >>> + while (!END_OF_HOB_LIST (Hob)) { > >>> + if (Hob.Header->HobType =3D=3D EFI_HOB_TYPE_RESOURCE_DESCRIPTOR= ) { > >>> + if (Hob.ResourceDescriptor->ResourceType =3D=3D > >> EFI_RESOURCE_SYSTEM_MEMORY) { > >>> + MemorySize +=3D > >> (UINT64)(Hob.ResourceDescriptor->ResourceLength); > >>> + > >>> + Status =3D SmbiosInstallMemoryStructure (Smbios, > >>> + Hob.ResourceDescriptor->PhysicalStart, > >>> + Hob.ResourceDescriptor->ResourceLength); > >>> + if (EFI_ERROR(Status)) { > >>> + return Status; > >>> + } > >>> + } > >>> + } > >>> + Hob.Raw =3D GET_NEXT_HOB (Hob); > >>> + } > >>> + > >>> + // > >>> + // Update TYPE17 memory size field > >>> + // > >>> + mArmadaDefaultType17.Size =3D (UINT16)(MemorySize >> 20); > >>> + > >>> + return EFI_SUCCESS; > >>> +} > >>> + > >>> +/** > >>> + Install all structures from the DefaultTables structure > >>> + > >>> + @param Smbios SMBIOS protocol > >>> + > >>> +**/ > >>> +EFI_STATUS > >>> +SmbiosInstallAllStructures ( > >>> + IN EFI_SMBIOS_PROTOCOL *Smbios > >>> + ) > >>> +{ > >>> + EFI_STATUS Status; > >>> + UINT32 FirmwareMajorRevisionNumber; > >>> + UINT32 FirmwareMinorRevisionNumber; > >>> + > >>> + FirmwareMajorRevisionNumber =3D (PcdGet32 (PcdFirmwareRevision) >= > 16) > >> & 0xFF; > >>> + FirmwareMinorRevisionNumber =3D PcdGet32 (PcdFirmwareRevision) & = 0xFF; > >>> + > >>> + // > >>> + // Update Firmware Revision, CPU and DRAM frequencies. > >>> + // > >>> + mArmadaDefaultType0.SystemBiosMajorRelease =3D > >> FirmwareMajorRevisionNumber; > >>> + mArmadaDefaultType0.SystemBiosMinorRelease =3D > >> FirmwareMinorRevisionNumber; > >>> + mArmadaDefaultType4.CurrentSpeed =3D SampleAtResetGetCpuFrequency= (); > >>> + mArmadaDefaultType17.Speed =3D SampleAtResetGetDramFrequency (); > >>> + > >>> + // > >>> + // Generate memory descriptors. > >>> + // > >>> + Status =3D SmbiosMemoryInstall (Smbios); > >>> + ASSERT_EFI_ERROR (Status); > >>> + > >>> + // > >>> + // Install all tables. > >>> + // > >>> + Status =3D SmbiosInstallStructures (Smbios, DefaultCommonTables); > >>> + ASSERT_EFI_ERROR (Status); > >>> + > >>> + return EFI_SUCCESS; > >>> +} > >>> + > >>> +/** > >>> + Installs SMBIOS information for Armada platforms > >>> + > >>> + @param ImageHandle Module's image handle > >>> + @param SystemTable Pointer of EFI_SYSTEM_TABLE > >>> + > >>> + @retval EFI_SUCCESS Smbios data successfully installed > >>> + @retval Other Smbios data was not installed > >>> + > >>> +**/ > >>> +EFI_STATUS > >>> +EFIAPI > >>> +SmbiosPlatformDriverEntryPoint ( > >>> + IN EFI_HANDLE ImageHandle, > >>> + IN EFI_SYSTEM_TABLE *SystemTable > >>> + ) > >>> +{ > >>> + EFI_STATUS Status; > >>> + EFI_SMBIOS_PROTOCOL *Smbios; > >>> + > >>> + // > >>> + // Find the SMBIOS protocol > >>> + // > >>> + Status =3D gBS->LocateProtocol (&gEfiSmbiosProtocolGuid, > >>> + NULL, > >>> + (VOID **)&Smbios); > >>> + if (EFI_ERROR (Status)) { > >>> + return Status; > >>> + } > >>> + > >>> + Status =3D SmbiosInstallAllStructures (Smbios); > >>> + > >>> + return Status; > >>> +} > >>> > >> > >> > >> > >> > >> > > > > >=20 >